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Added LVTTimer union structure

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This commit is contained in:
Alex 2022-10-23 02:48:42 +03:00
parent 21478ca5b8
commit fd154bc547
Signed by untrusted user who does not match committer: enderice2
GPG Key ID: EACC3AD603BAB4DD
2 changed files with 48 additions and 5 deletions
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12
Architecture/amd64/cpu/AdvancedProgrammableInterruptController.cpp
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@ -237,7 +237,10 @@ namespace APIC
void Timer::OneShot(uint32_t Vector, uint64_t Miliseconds)
{
this->lapic->Write(APIC_TDCR, 0x03);
this->lapic->Write(APIC_TIMER, (APIC_ONESHOT | Vector));
LVTTimer timer = {0, 0, 0, 0, 0, 0, 0};
timer.Vector = Vector;
timer.TimerMode = 0;
this->lapic->Write(APIC_TIMER, timer.raw);
this->lapic->Write(APIC_TICR, (TicksIn10ms / 10) * Miliseconds);
}
@ -279,7 +282,12 @@ namespace APIC
TicksIn10ms = 0xFFFFFFFF - this->lapic->Read(APIC_TCCR);
this->lapic->Write(APIC_TIMER, (long)CPU::x64::IRQ0 | (long)APIC_PERIODIC);
LVTTimer timer = {0, 0, 0, 0, 0, 0, 0};
timer.Vector = CPU::x64::IRQ0;
timer.Mask = 0;
timer.TimerMode = 1;
this->lapic->Write(APIC_TIMER, timer.raw);
this->lapic->Write(APIC_TDCR, 0x3);
this->lapic->Write(APIC_TICR, TicksIn10ms / 10);
trace("APIC Timer (CPU %d): %d ticks in 10ms", GetCurrentCPU()->ID, TicksIn10ms / 10);

41
Architecture/amd64/cpu/apic.hpp
View File

@ -10,9 +10,6 @@ namespace APIC
{
enum APICRegisters
{
APIC_ONESHOT = (0 << 17), // LVT One-Shot Mode (for Timer)
APIC_PERIODIC = (1 << 17), // LVT Periodic Mode (for Timer)
APIC_TSC_DEADLINE = (2 << 17), // LVT Timer/sDeadline (for Timer)
// source from: https://github.com/pdoane/osdev/blob/master/intr/local_apic.c
APIC_ID = 0x20, // Local APIC ID
APIC_VER = 0x30, // Local APIC Version
@ -40,6 +37,44 @@ namespace APIC
APIC_TCCR = 0x390, // Current Count (for Timer)
APIC_TDCR = 0x3E0, // Divide Configuration (for Timer)
};
union LVTTimer
{
struct
{
/** @brief Interrupt Vector */
uint64_t Vector : 8;
/** @brief Reserved */
uint64_t Reserved0 : 4;
/**
* @brief Delivery Status
*
* 0: Idle
* 1: Send Pending
*/
uint64_t DeliveryStatus : 1;
/** @brief Reserved */
uint64_t Reserved1 : 3;
/**
* @brief Mask
*
* 0: Not masked
* 1: Masked
*/
uint64_t Mask : 1;
/** @brief Timer Mode
*
* 0: One-shot
* 1: Periodic
* 2: TSC-Deadline
*/
uint64_t TimerMode : 1;
/** @brief Reserved */
uint64_t Reserved2 : 14;
};
uint64_t raw;
};
class APIC
{
private: