diff --git a/Architecture/amd64/cpu/AdvancedProgrammableInterruptController.cpp b/Architecture/amd64/cpu/AdvancedProgrammableInterruptController.cpp index cc9e16c..e9466c0 100644 --- a/Architecture/amd64/cpu/AdvancedProgrammableInterruptController.cpp +++ b/Architecture/amd64/cpu/AdvancedProgrammableInterruptController.cpp @@ -237,7 +237,10 @@ namespace APIC void Timer::OneShot(uint32_t Vector, uint64_t Miliseconds) { this->lapic->Write(APIC_TDCR, 0x03); - this->lapic->Write(APIC_TIMER, (APIC_ONESHOT | Vector)); + LVTTimer timer = {0, 0, 0, 0, 0, 0, 0}; + timer.Vector = Vector; + timer.TimerMode = 0; + this->lapic->Write(APIC_TIMER, timer.raw); this->lapic->Write(APIC_TICR, (TicksIn10ms / 10) * Miliseconds); } @@ -279,7 +282,12 @@ namespace APIC TicksIn10ms = 0xFFFFFFFF - this->lapic->Read(APIC_TCCR); - this->lapic->Write(APIC_TIMER, (long)CPU::x64::IRQ0 | (long)APIC_PERIODIC); + LVTTimer timer = {0, 0, 0, 0, 0, 0, 0}; + timer.Vector = CPU::x64::IRQ0; + timer.Mask = 0; + timer.TimerMode = 1; + + this->lapic->Write(APIC_TIMER, timer.raw); this->lapic->Write(APIC_TDCR, 0x3); this->lapic->Write(APIC_TICR, TicksIn10ms / 10); trace("APIC Timer (CPU %d): %d ticks in 10ms", GetCurrentCPU()->ID, TicksIn10ms / 10); diff --git a/Architecture/amd64/cpu/apic.hpp b/Architecture/amd64/cpu/apic.hpp index 6e54a8a..aac2bed 100644 --- a/Architecture/amd64/cpu/apic.hpp +++ b/Architecture/amd64/cpu/apic.hpp @@ -10,9 +10,6 @@ namespace APIC { enum APICRegisters { - APIC_ONESHOT = (0 << 17), // LVT One-Shot Mode (for Timer) - APIC_PERIODIC = (1 << 17), // LVT Periodic Mode (for Timer) - APIC_TSC_DEADLINE = (2 << 17), // LVT Timer/sDeadline (for Timer) // source from: https://github.com/pdoane/osdev/blob/master/intr/local_apic.c APIC_ID = 0x20, // Local APIC ID APIC_VER = 0x30, // Local APIC Version @@ -40,6 +37,44 @@ namespace APIC APIC_TCCR = 0x390, // Current Count (for Timer) APIC_TDCR = 0x3E0, // Divide Configuration (for Timer) }; + + union LVTTimer + { + struct + { + /** @brief Interrupt Vector */ + uint64_t Vector : 8; + /** @brief Reserved */ + uint64_t Reserved0 : 4; + /** + * @brief Delivery Status + * + * 0: Idle + * 1: Send Pending + */ + uint64_t DeliveryStatus : 1; + /** @brief Reserved */ + uint64_t Reserved1 : 3; + /** + * @brief Mask + * + * 0: Not masked + * 1: Masked + */ + uint64_t Mask : 1; + /** @brief Timer Mode + * + * 0: One-shot + * 1: Periodic + * 2: TSC-Deadline + */ + uint64_t TimerMode : 1; + /** @brief Reserved */ + uint64_t Reserved2 : 14; + }; + uint64_t raw; + }; + class APIC { private: