pci.h File Reference

Go to the source code of this file.

Data Structures
struct	__attribute__

Enumerations
enum	PCI_COMMANDS {   PCI_COMMAND_IO = 0x1 , PCI_COMMAND_MEMORY = 0x2 , PCI_COMMAND_MASTER = 0x4 , PCI_COMMAND_SPECIAL = 0x8 ,   PCI_COMMAND_INVALIDATE = 0x10 , PCI_COMMAND_VGA_PALETTE = 0x20 , PCI_COMMAND_PARITY = 0x40 , PCI_COMMAND_WAIT = 0x80 ,   PCI_COMMAND_SERR = 0x100 , PCI_COMMAND_FAST_BACK = 0x200 , PCI_COMMAND_INTX_DISABLE = 0x400 }

Functions
PCIArray *	GetPCIDevices (uint16_t Vendors[], uint16_t Devices[])
void	InitializePCI (PCIDevice *Device)
uint32_t	GetBAR (uint8_t Index, PCIDevice *Device)
uint8_t	iLine (PCIDevice *Device)
uint8_t	iPin (PCIDevice *Device)

---

Data Structure Documentation

__attribute__

struct __attribute__

Definition at line 50 of file pci.h.

Data Fields
uint32_t	BAR0
uint32_t	BAR1
uint32_t	BAR2
uint32_t	BAR3
uint32_t	BAR4
uint32_t	BAR5
uint64_t	BaseAddress
uint8_t	BIST
uint16_t	BridgeControl
uint32_t	Bus
uint8_t	CacheLineSize
uint8_t	CapabilitiesPointer
uint8_t	CardbusBusNumber
uint32_t	CardbusCISPointer
uint8_t	CardbusLatencyTimer
uint32_t	CardbusSocketRegistersBaseAddress
uint8_t	Class
uint16_t	Command
DeviceConfig *	Config
uint32_t	Device
PCIDevice *	Device
uint16_t	DeviceID
uint8_t	EndBus
uint32_t	ExpansionROMBaseAddress
uint32_t	Function
PCIDeviceHeader	Header
PCIDeviceHeader *	Header
uint8_t	HeaderType
uint8_t	InterruptLine
uint8_t	InterruptPin
uint8_t	IOBase
uint32_t	IOBase0
uint32_t	IOBase1
uint16_t	IOBaseUpper16
uint8_t	IOLimit
uint32_t	IOLimit0
uint32_t	IOLimit1
uint16_t	IOLimitUpper16
uint8_t	LatencyTimer
uint32_t	LegacyBaseAddress
uint8_t	MaxLatency
uint16_t	MemoryBase
uint32_t	MemoryBase0
uint32_t	MemoryBase1
uint16_t	MemoryLimit
uint32_t	MemoryLimit0
uint32_t	MemoryLimit1
uint8_t	MinGrant
void *	Next
uint8_t	PCIbusNumber
uint16_t	PCISegGroup
uint16_t	PrefetchableMemoryBase
uint32_t	PrefetchableMemoryBaseUpper32
uint16_t	PrefetchableMemoryLimit
uint32_t	PrefetchableMemoryLimitUpper32
uint8_t	PrimaryBusNumber
uint8_t	ProgIF
uint32_t	Reserved
uint8_t	Reserved0
uint16_t	Reserved1
uint32_t	Reserved2
uint8_t	RevisionID
uint8_t	SecondaryBusNumber
uint8_t	SecondaryLatencyTimer
uint16_t	SecondaryStatus
uint8_t	StartBus
uint16_t	Status
uint8_t	Subclass
uint8_t	SubordinateBusNumber
uint16_t	SubsystemID
uint16_t	SubsystemVendorID
uint16_t	VendorID

Enumeration Type Documentation

PCI_COMMANDS

enum PCI_COMMANDS

Enumerator
PCI_COMMAND_IO	Enable response in I/O space.
PCI_COMMAND_MEMORY	Enable response in Memory space.
PCI_COMMAND_MASTER	Enable bus mastering.
PCI_COMMAND_SPECIAL	Enable response to special cycles.
PCI_COMMAND_INVALIDATE	Use memory write and invalidate.
PCI_COMMAND_VGA_PALETTE	Enable palette snooping.
PCI_COMMAND_PARITY	Enable parity checking.
PCI_COMMAND_WAIT	Enable address/data stepping.
PCI_COMMAND_SERR	Enable SERR.
PCI_COMMAND_FAST_BACK	Enable back-to-back writes.
PCI_COMMAND_INTX_DISABLE	INTx Emulation Disable.

Definition at line 24 of file pci.h.

{
    PCI_COMMAND_IO = 0x1,
    PCI_COMMAND_MEMORY = 0x2,
    PCI_COMMAND_MASTER = 0x4,
    PCI_COMMAND_SPECIAL = 0x8,
    PCI_COMMAND_INVALIDATE = 0x10,
    PCI_COMMAND_VGA_PALETTE = 0x20,
    PCI_COMMAND_PARITY = 0x40,
    PCI_COMMAND_WAIT = 0x80,
    PCI_COMMAND_SERR = 0x100,
    PCI_COMMAND_FAST_BACK = 0x200,
    PCI_COMMAND_INTX_DISABLE = 0x400
} PCI_COMMANDS;

Function Documentation

GetBAR()

uint32_t GetBAR	(	uint8_t	Index,
		PCIDevice *	Device
	)

GetPCIDevices()

PCIArray * GetPCIDevices	(	uint16_t	Vendors[],
		uint16_t	Devices[]
	)

iLine()

uint8_t iLine

(

PCIDevice *

Device

)

InitializePCI()

void InitializePCI

(

PCIDevice *

Device

)

iPin()

uint8_t iPin

(

PCIDevice *

Device

)