18#ifndef __FENNIX_API_PCI_H__
19#define __FENNIX_API_PCI_H__
91 PCIDeviceHeader Header;
109 uint8_t CapabilitiesPointer;
112 uint32_t ExpansionROMBaseAddress;
113 uint8_t InterruptLine;
114 uint8_t InterruptPin;
120 PCIDeviceHeader Header;
122 uint8_t CapabilitiesPointer;
124 uint16_t SecondaryStatus;
127 uint8_t SubordinateBusNumber;
137 uint8_t InterruptLine;
138 uint8_t InterruptPin;
139 uint16_t BridgeControl;
140 uint16_t SubsystemVendorID;
141 uint16_t SubsystemID;
177 uint32_t
GetBAR(uint8_t Index, PCIDevice *Device);
179 uint8_t
iPin(PCIDevice *Device);
uint16_t SubsystemVendorID
uint8_t iLine(PCIDevice *Device)
uint32_t LegacyBaseAddress
uint8_t iPin(PCIDevice *Device)
PCIArray * GetPCIDevices(uint16_t Vendors[], uint16_t Devices[])
uint32_t GetBAR(uint8_t Index, PCIDevice *Device)
uint32_t PrefetchableMemoryBaseUpper32
uint8_t CardbusLatencyTimer
uint16_t PrefetchableMemoryLimit
uint8_t CapabilitiesPointer
uint32_t PrefetchableMemoryLimitUpper32
uint32_t CardbusCISPointer
uint32_t CardbusSocketRegistersBaseAddress
uint8_t SecondaryLatencyTimer
uint8_t SecondaryBusNumber
uint16_t PrefetchableMemoryBase
uint8_t SubordinateBusNumber
uint32_t ExpansionROMBaseAddress
@ PCI_COMMAND_SERR
Enable SERR.
@ PCI_COMMAND_PARITY
Enable parity checking.
@ PCI_COMMAND_WAIT
Enable address/data stepping.
@ PCI_COMMAND_MEMORY
Enable response in Memory space.
@ PCI_COMMAND_INVALIDATE
Use memory write and invalidate.
@ PCI_COMMAND_IO
Enable response in I/O space.
@ PCI_COMMAND_MASTER
Enable bus mastering.
@ PCI_COMMAND_SPECIAL
Enable response to special cycles.
@ PCI_COMMAND_VGA_PALETTE
Enable palette snooping.
@ PCI_COMMAND_FAST_BACK
Enable back-to-back writes.
@ PCI_COMMAND_INTX_DISABLE
INTx Emulation Disable.
void InitializePCI(PCIDevice *Device)