Fennix  1.0.0
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pci.h
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1/*
2 This file is part of Fennix Kernel.
3
4 Fennix Kernel is free software: you can redistribute it and/or
5 modify it under the terms of the GNU General Public License as
6 published by the Free Software Foundation, either version 3 of
7 the License, or (at your option) any later version.
8
9 Fennix Kernel is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
16*/
17
18#ifndef __FENNIX_API_PCI_H__
19#define __FENNIX_API_PCI_H__
20
21#include <types.h>
22
23/* https://sites.uclouvain.be/SystInfo/usr/include/linux/pci_regs.h.html */
49
50typedef struct
51{
52 uint16_t VendorID;
53 uint16_t DeviceID;
54 uint16_t Command;
55 uint16_t Status;
56 uint8_t RevisionID;
57 uint8_t ProgIF;
58 uint8_t Subclass;
59 uint8_t Class;
61 uint8_t LatencyTimer;
62 uint8_t HeaderType;
63 uint8_t BIST;
64} __attribute__((packed)) PCIDeviceHeader;
65
66typedef struct
67{
68 PCIDeviceHeader Header;
69 uint32_t BAR0;
70 uint32_t BAR1;
71 uint32_t BAR2;
72 uint32_t BAR3;
73 uint32_t BAR4;
74 uint32_t BAR5;
77 uint16_t SubsystemID;
80 uint8_t Reserved0;
81 uint16_t Reserved1;
82 uint32_t Reserved2;
84 uint8_t InterruptPin;
85 uint8_t MinGrant;
86 uint8_t MaxLatency;
87} __attribute__((packed)) PCIHeader0;
88
89typedef struct
90{
91 PCIDeviceHeader Header;
92 uint32_t BAR0;
93 uint32_t BAR1;
98 uint8_t IOBase;
99 uint8_t IOLimit;
101 uint16_t MemoryBase;
102 uint16_t MemoryLimit;
109 uint8_t CapabilitiesPointer;
110 uint8_t Reserved0;
111 uint16_t Reserved1;
112 uint32_t ExpansionROMBaseAddress;
113 uint8_t InterruptLine;
114 uint8_t InterruptPin;
116} __attribute__((packed)) PCIHeader1;
117
118typedef struct
119{
120 PCIDeviceHeader Header;
122 uint8_t CapabilitiesPointer;
123 uint8_t Reserved0;
124 uint16_t SecondaryStatus;
127 uint8_t SubordinateBusNumber;
129 uint32_t MemoryBase0;
130 uint32_t MemoryLimit0;
131 uint32_t MemoryBase1;
132 uint32_t MemoryLimit1;
133 uint32_t IOBase0;
134 uint32_t IOLimit0;
135 uint32_t IOBase1;
136 uint32_t IOLimit1;
137 uint8_t InterruptLine;
138 uint8_t InterruptPin;
139 uint16_t BridgeControl;
140 uint16_t SubsystemVendorID;
141 uint16_t SubsystemID;
143} __attribute__((packed)) PCIHeader2;
144
145typedef struct
146{
147 uint64_t BaseAddress;
148 uint16_t PCISegGroup;
149 uint8_t StartBus;
150 uint8_t EndBus;
151 uint32_t Reserved;
152} __attribute__((packed)) DeviceConfig;
153
154typedef struct
155{
156 PCIDeviceHeader *Header;
157 DeviceConfig *Config;
158 uint32_t Bus;
159 uint32_t Device;
160 uint32_t Function;
161} __attribute__((packed)) PCIDevice;
162
163typedef struct
164{
165 PCIDevice *Device;
166 /* PCIArray */ void *Next;
167} __attribute__((packed)) PCIArray;
168
169#ifdef __cplusplus
170extern "C"
171{
172#endif
173
174#ifndef __kernel__
175 PCIArray *GetPCIDevices(uint16_t Vendors[], uint16_t Devices[]);
176 void InitializePCI(PCIDevice *Device);
177 uint32_t GetBAR(uint8_t Index, PCIDevice *Device);
178 uint8_t iLine(PCIDevice *Device);
179 uint8_t iPin(PCIDevice *Device);
180#endif // !__kernel__
181
182#ifdef __cplusplus
183}
184#endif
185
186#endif // !__FENNIX_API_PCI_H__
uint8_t IOLimit
Definition pci.h:99
uint8_t PCIbusNumber
Definition pci.h:125
uint16_t SubsystemVendorID
Definition pci.h:76
uint8_t Class
Definition pci.h:59
uint8_t iLine(PCIDevice *Device)
uint8_t RevisionID
Definition pci.h:56
uint16_t MemoryBase
Definition pci.h:101
PCIDeviceHeader Header
Definition pci.h:68
uint32_t LegacyBaseAddress
Definition pci.h:142
uint32_t BAR2
Definition pci.h:71
uint16_t Status
Definition pci.h:55
uint8_t iPin(PCIDevice *Device)
PCIArray * GetPCIDevices(uint16_t Vendors[], uint16_t Devices[])
uint32_t MemoryLimit0
Definition pci.h:130
uint32_t GetBAR(uint8_t Index, PCIDevice *Device)
uint32_t PrefetchableMemoryBaseUpper32
Definition pci.h:105
uint8_t LatencyTimer
Definition pci.h:61
uint8_t CardbusLatencyTimer
Definition pci.h:128
uint32_t Function
Definition pci.h:160
uint8_t MinGrant
Definition pci.h:85
uint8_t CardbusBusNumber
Definition pci.h:126
uint16_t Reserved1
Definition pci.h:81
uint8_t CacheLineSize
Definition pci.h:60
PCIDeviceHeader * Header
Definition pci.h:156
uint16_t PrefetchableMemoryLimit
Definition pci.h:104
uint8_t CapabilitiesPointer
Definition pci.h:79
uint32_t Reserved
Definition pci.h:151
uint32_t MemoryBase1
Definition pci.h:131
uint32_t IOLimit0
Definition pci.h:134
PCIDevice * Device
Definition pci.h:165
uint16_t BridgeControl
Definition pci.h:115
uint32_t IOBase1
Definition pci.h:135
uint8_t InterruptPin
Definition pci.h:84
uint32_t Device
Definition pci.h:159
uint32_t MemoryLimit1
Definition pci.h:132
uint8_t MaxLatency
Definition pci.h:86
uint32_t PrefetchableMemoryLimitUpper32
Definition pci.h:106
uint8_t EndBus
Definition pci.h:150
void * Next
Definition pci.h:166
uint32_t CardbusCISPointer
Definition pci.h:75
uint32_t BAR4
Definition pci.h:73
uint16_t MemoryLimit
Definition pci.h:102
uint32_t BAR5
Definition pci.h:74
uint32_t CardbusSocketRegistersBaseAddress
Definition pci.h:121
uint8_t Reserved0
Definition pci.h:80
uint16_t IOLimitUpper16
Definition pci.h:108
uint8_t StartBus
Definition pci.h:149
uint16_t DeviceID
Definition pci.h:53
uint32_t IOBase0
Definition pci.h:133
uint8_t SecondaryLatencyTimer
Definition pci.h:97
uint8_t IOBase
Definition pci.h:98
uint32_t BAR1
Definition pci.h:70
uint32_t MemoryBase0
Definition pci.h:129
uint8_t SecondaryBusNumber
Definition pci.h:95
uint16_t PrefetchableMemoryBase
Definition pci.h:103
uint8_t Subclass
Definition pci.h:58
uint16_t VendorID
Definition pci.h:52
uint8_t InterruptLine
Definition pci.h:83
uint8_t SubordinateBusNumber
Definition pci.h:96
DeviceConfig * Config
Definition pci.h:157
uint32_t ExpansionROMBaseAddress
Definition pci.h:78
uint32_t Bus
Definition pci.h:158
PCI_COMMANDS
Definition pci.h:25
@ PCI_COMMAND_SERR
Enable SERR.
Definition pci.h:43
@ PCI_COMMAND_PARITY
Enable parity checking.
Definition pci.h:39
@ PCI_COMMAND_WAIT
Enable address/data stepping.
Definition pci.h:41
@ PCI_COMMAND_MEMORY
Enable response in Memory space.
Definition pci.h:29
@ PCI_COMMAND_INVALIDATE
Use memory write and invalidate.
Definition pci.h:35
@ PCI_COMMAND_IO
Enable response in I/O space.
Definition pci.h:27
@ PCI_COMMAND_MASTER
Enable bus mastering.
Definition pci.h:31
@ PCI_COMMAND_SPECIAL
Enable response to special cycles.
Definition pci.h:33
@ PCI_COMMAND_VGA_PALETTE
Enable palette snooping.
Definition pci.h:37
@ PCI_COMMAND_FAST_BACK
Enable back-to-back writes.
Definition pci.h:45
@ PCI_COMMAND_INTX_DISABLE
INTx Emulation Disable.
Definition pci.h:47
uint16_t IOBaseUpper16
Definition pci.h:107
uint8_t HeaderType
Definition pci.h:62
uint8_t BIST
Definition pci.h:63
uint32_t BAR3
Definition pci.h:72
uint32_t Reserved2
Definition pci.h:82
uint32_t BAR0
Definition pci.h:69
void InitializePCI(PCIDevice *Device)
uint16_t PCISegGroup
Definition pci.h:148
uint32_t IOLimit1
Definition pci.h:136
uint64_t BaseAddress
Definition pci.h:147
uint8_t ProgIF
Definition pci.h:57
uint16_t Command
Definition pci.h:54
uint8_t PrimaryBusNumber
Definition pci.h:94
uint16_t SubsystemID
Definition pci.h:77
uint16_t SecondaryStatus
Definition pci.h:100