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chore: Update makefiles & macros

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EnderIce2
2024-11-29 04:24:27 +02:00
parent ce3cf8162a
commit 7948d0c6e5
116 changed files with 682 additions and 740 deletions
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16
Kernel/include/cpu/membar.hpp
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@ -26,10 +26,10 @@ namespace CPU
{
nsa static inline void Barrier()
{
#if defined(a86)
#if defined(__amd64__) || defined(__i386__)
asmv("" ::
: "memory");
#elif defined(aa64)
#elif defined(__aarch64__)
asmv("dmb ish" ::
: "memory");
#endif
@ -37,10 +37,10 @@ namespace CPU
nsa static inline void Fence()
{
#if defined(a86)
#if defined(__amd64__) || defined(__i386__)
asmv("mfence" ::
: "memory");
#elif defined(aa64)
#elif defined(__aarch64__)
asmv("dmb ish" ::
: "memory");
#endif
@ -48,10 +48,10 @@ namespace CPU
nsa static inline void StoreFence()
{
#if defined(a86)
#if defined(__amd64__) || defined(__i386__)
asmv("sfence" ::
: "memory");
#elif defined(aa64)
#elif defined(__aarch64__)
asmv("dmb ishst" ::
: "memory");
#endif
@ -59,10 +59,10 @@ namespace CPU
nsa static inline void LoadFence()
{
#if defined(a86)
#if defined(__amd64__) || defined(__i386__)
asmv("lfence" ::
: "memory");
#elif defined(aa64)
#elif defined(__aarch64__)
asmv("dmb ishld" ::
: "memory");
#endif

8
Kernel/include/cpu/x86/cpuid_amd.hpp
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@ -21,15 +21,15 @@
#include <types.h>
#include <debug.h>
#if defined(a64)
#if defined(__amd64__)
typedef uint64_t cpuid_t;
#elif defined(a32)
#elif defined(__i386__)
typedef uint32_t cpuid_t;
#else
typedef uint64_t cpuid_t;
#endif // a64 || a32
#endif // __amd64__ || __i386__
#if defined(a86)
#if defined(__amd64__) || defined(__i386__)
#define __amd_cpuid_init(leaf) \
CPUID##leaf() \
{ \

8
Kernel/include/cpu/x86/cpuid_intel.hpp
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@ -21,15 +21,15 @@
#include <types.h>
#include <debug.h>
#if defined(a64)
#if defined(__amd64__)
typedef uint64_t cpuid_t;
#elif defined(a32)
#elif defined(__i386__)
typedef uint32_t cpuid_t;
#else
typedef uint64_t cpuid_t;
#endif // a64 || a32
#endif // __amd64__ || __i386__
#if defined(a86)
#if defined(__amd64__) || defined(__i386__)
#define __intel_cpuid_init(leaf) \
CPUID##leaf() \
{ \

2
Kernel/include/cpu/x86/x32/cr.hpp
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@ -141,7 +141,7 @@ namespace CPU
};
uint32_t raw;
} CR4;
#if defined(a32)
#if defined(__i386__)
nsa static inline CR0 readcr0()
{
uint32_t Result = 0;

2
Kernel/include/cpu/x86/x32/msr.hpp
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@ -400,7 +400,7 @@ namespace CPU
MSR_CR_PAT = 0x00000277,
};
#if defined(a32)
#if defined(__i386__)
nsa static inline uint64_t rdmsr(uint32_t msr)
{
uint32_t Low, High;

2
Kernel/include/cpu/x86/x64/cr.hpp
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@ -191,7 +191,7 @@ namespace CPU
uint64_t raw;
} XCR0;
#if defined(a64)
#if defined(__amd64__)
nsa static inline CR0 readcr0()
{
uint64_t Result = 0;

2
Kernel/include/cpu/x86/x64/msr.hpp
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@ -401,7 +401,7 @@ namespace CPU
MSR_CR_PAT_RESET = 0x0007040600070406ULL
};
#if defined(a64)
#if defined(__amd64__)
nsa static inline uint64_t rdmsr(uint32_t msr)
{
uint32_t Low, High;