mirror of
https://github.com/EnderIce2/Fennix.git
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297 lines
6.6 KiB
C++
297 lines
6.6 KiB
C++
/*
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This file is part of Fennix Kernel.
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Fennix Kernel is free software: you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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Fennix Kernel is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef __FENNIX_KERNEL_CPU_x64_CR_H__
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#define __FENNIX_KERNEL_CPU_x64_CR_H__
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#include <types.h>
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namespace CPU
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{
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namespace x64
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{
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typedef union CR0
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{
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struct
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{
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/** Protection Enable */
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uint64_t PE : 1;
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/** Monitor Coprocessor */
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uint64_t MP : 1;
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/** Emulation */
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uint64_t EM : 1;
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/** Task Switched */
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uint64_t TS : 1;
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/** Extension Type */
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uint64_t ET : 1;
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/** Numeric Error */
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uint64_t NE : 1;
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/** Reserved */
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uint64_t Reserved0 : 10;
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/** Write Protect */
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uint64_t WP : 1;
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/** Reserved */
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uint64_t Reserved1 : 1;
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/** Alignment Mask */
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uint64_t AM : 1;
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/** Reserved */
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uint64_t Reserved2 : 10;
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/** Not Write-through */
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uint64_t NW : 1;
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/** Cache Disable */
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uint64_t CD : 1;
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/** Paging */
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uint64_t PG : 1;
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};
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uint64_t raw;
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} CR0;
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typedef union CR2
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{
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struct
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{
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/** Page Fault Linear Address */
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uint64_t PFLA;
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};
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uint64_t raw;
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} CR2;
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typedef union CR3
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{
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struct
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{
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/** Not used if bit 17 of CR4 is 1 */
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uint64_t PWT : 1;
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/** Not used if bit 17 of CR4 is 1 */
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uint64_t PCD : 1;
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/** Base of PML4T/PML5T */
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uint64_t PDBR;
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};
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uint64_t raw;
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} CR3;
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typedef union CR4
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{
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struct
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{
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/** Virtual-8086 Mode Extensions */
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uint64_t VME : 1;
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/** Protected-Mode Virtual Interrupts */
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uint64_t PVI : 1;
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/** Time Stamp Disable */
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uint64_t TSD : 1;
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/** Debugging Extensions */
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uint64_t DE : 1;
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/** Page Size Extensions */
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uint64_t PSE : 1;
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/** Physical Address Extension */
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uint64_t PAE : 1;
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/** Machine Check Enable */
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uint64_t MCE : 1;
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/** Page Global Enable */
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uint64_t PGE : 1;
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/** Performance Monitoring Counter */
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uint64_t PCE : 1;
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/** FXSAVE/FXRSTOR Support */
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uint64_t OSFXSR : 1;
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/** Unmasked Exception Support */
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uint64_t OSXMMEXCPT : 1;
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/** User-Mode Instruction Prevention */
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uint64_t UMIP : 1;
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/** Linear Address 57bit */
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uint64_t LA57 : 1;
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/** VMX Enable */
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uint64_t VMXE : 1;
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/** SMX Enable */
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uint64_t SMXE : 1;
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/** Reserved */
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uint64_t Reserved0 : 1;
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/** FSGSBASE Enable */
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uint64_t FSGSBASE : 1;
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/** PCID Enable */
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uint64_t PCIDE : 1;
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/** XSAVE and Processor Extended States Enable */
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uint64_t OSXSAVE : 1;
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/** Reserved */
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uint64_t Reserved1 : 1;
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/** SMEP Enable */
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uint64_t SMEP : 1;
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/** SMAP Enable */
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uint64_t SMAP : 1;
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/** Protection-Key Enable */
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uint64_t PKE : 1;
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/** Control-flow Enforcement Technology*/
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uint32_t CET : 1;
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/* Enable Protection Keys for Supervisor Mode Pages */
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uint32_t PKS : 1;
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/** Reserved */
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uint64_t Reserved2 : 7; // TODO: This could be wrong
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};
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uint64_t raw;
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} CR4;
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typedef union CR8
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{
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struct
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{
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/** Task Priority Register */
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uint64_t TPR : 4;
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/** Reserved */
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uint64_t Reserved : 60;
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};
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uint64_t raw;
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} CR8;
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typedef union XCR0
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{
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/*
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On https://wiki.osdev.org/CPU_Registers_x86#XCR0 says that the PKRU bit is 9?
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*/
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struct
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{
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/** X87 FPU/MMX/SSE Support (must be 1) */
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uint64_t X87 : 1;
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/** XSAVE support for MXCSR and XMM registers */
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uint64_t SSE : 1;
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/** AVX support for YMM registers */
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uint64_t AVX : 1;
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/** MPX support for BND registers */
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uint64_t BNDREG : 1;
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/** MPX support for BNDCFGU and BNDSTATUS registers */
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uint64_t BNDCSR : 1;
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/** AVX-512 support for opmask registers */
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uint64_t OpMask : 1;
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/** AVX-512 enabled and XSAVE support for upper halves of lower ZMM registers */
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uint64_t ZMM_HI256 : 1;
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/** AVX-512 enabled and XSAVE support for upper ZMM registers */
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uint64_t HI16_ZMM : 1;
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/** XSAVE support for PKRU register */
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uint64_t PKRU : 1;
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/** Reserved */
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uint64_t Reserved0 : 53;
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/** AMD lightweight profiling */
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uint64_t LWP : 1;
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/** Reserved */
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uint64_t Reserved1 : 1;
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};
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uint64_t raw;
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} XCR0;
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#if defined(__amd64__)
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nsa static inline CR0 readcr0()
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{
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uint64_t Result = 0;
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asmv("mov %%cr0, %[Result]"
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: [Result] "=q"(Result));
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return (CR0){.raw = Result};
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}
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nsa static inline CR2 readcr2()
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{
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uint64_t Result = 0;
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asmv("mov %%cr2, %[Result]"
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: [Result] "=q"(Result));
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return (CR2){.raw = Result};
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}
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nsa static inline CR3 readcr3()
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{
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uint64_t Result = 0;
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asmv("mov %%cr3, %[Result]"
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: [Result] "=q"(Result));
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return (CR3){.raw = Result};
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}
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nsa static inline CR4 readcr4()
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{
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uint64_t Result = 0;
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asmv("mov %%cr4, %[Result]"
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: [Result] "=q"(Result));
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return (CR4){.raw = Result};
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}
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nsa static inline CR8 readcr8()
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{
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uint64_t Result = 0;
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asmv("mov %%cr8, %[Result]"
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: [Result] "=q"(Result));
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return (CR8){.raw = Result};
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}
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nsa static inline XCR0 readxcr0()
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{
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uint64_t Result = 0;
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asmv("xgetbv"
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: "=a"(Result)
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: "c"(0)
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: "edx");
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return (XCR0){.raw = Result};
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}
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nsa static inline void writecr0(CR0 ControlRegister)
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{
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asmv("mov %[ControlRegister], %%cr0"
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:
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: [ControlRegister] "q"(ControlRegister.raw)
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: "memory");
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}
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nsa static inline void writecr2(CR2 ControlRegister)
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{
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asmv("mov %[ControlRegister], %%cr2"
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:
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: [ControlRegister] "q"(ControlRegister.raw)
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: "memory");
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}
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nsa static inline void writecr3(CR3 ControlRegister)
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{
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asmv("mov %[ControlRegister], %%cr3"
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:
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: [ControlRegister] "q"(ControlRegister.raw)
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: "memory");
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}
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nsa static inline void writecr4(CR4 ControlRegister)
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{
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asmv("mov %[ControlRegister], %%cr4"
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:
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: [ControlRegister] "q"(ControlRegister.raw)
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: "memory");
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}
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nsa static inline void writecr8(CR8 ControlRegister)
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{
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asmv("mov %[ControlRegister], %%cr8"
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:
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: [ControlRegister] "q"(ControlRegister.raw)
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: "memory");
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}
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nsa static inline void writexcr0(XCR0 ControlRegister)
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{
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asmv("xsetbv"
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:
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: "a"(ControlRegister.raw), "c"(0)
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: "edx");
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}
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#endif
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}
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}
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#endif // !__FENNIX_KERNEL_CPU_x64_CR_H__
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