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https://github.com/Fennix-Project/Drivers.git
synced 2025-05-28 15:34:29 +00:00
Added AHCI driver
This commit is contained in:
Alex
parent
4969e1fee0
commit
d162ea1398
GPG Key ID:
EACC3AD603BAB4DD
@ -31,6 +31,145 @@ KernelAPI *KAPI;
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/* --------------------------------------------------------------------------------------------------------- */
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#define ATA_DEV_BUSY 0x80
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#define ATA_DEV_DRQ 0x08
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#define ATA_CMD_WRITE_DMA_EX 0x35
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#define ATA_CMD_READ_DMA_EX 0x25
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#define HBA_PxIS_TFES (1 << 30)
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#define HBA_PORT_DEV_PRESENT 0x3
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#define HBA_PORT_IPM_ACTIVE 0x1
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#define SATA_SIG_ATAPI 0xEB140101
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#define SATA_SIG_ATA 0x00000101
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#define SATA_SIG_SEMB 0xC33C0101
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#define SATA_SIG_PM 0x96690101
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#define HBA_PxCMD_CR 0x8000
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#define HBA_PxCMD_FRE 0x0010
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#define HBA_PxCMD_ST 0x0001
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#define HBA_PxCMD_FR 0x4000
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enum PortType
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{
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None = 0,
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SATA = 1,
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SEMB = 2,
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PM = 3,
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SATAPI = 4,
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};
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enum FIS_TYPE
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{
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FIS_TYPE_REG_H2D = 0x27,
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FIS_TYPE_REG_D2H = 0x34,
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FIS_TYPE_DMA_ACT = 0x39,
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FIS_TYPE_DMA_SETUP = 0x41,
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FIS_TYPE_DATA = 0x46,
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FIS_TYPE_BIST = 0x58,
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FIS_TYPE_PIO_SETUP = 0x5F,
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FIS_TYPE_DEV_BITS = 0xA1,
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};
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struct HBAPort
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{
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uint32_t CommandListBase;
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uint32_t CommandListBaseUpper;
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uint32_t FISBaseAddress;
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uint32_t FISBaseAddressUpper;
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uint32_t InterruptStatus;
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uint32_t InterruptEnable;
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uint32_t CommandStatus;
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uint32_t Reserved0;
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uint32_t TaskFileData;
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uint32_t Signature;
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uint32_t SataStatus;
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uint32_t SataControl;
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uint32_t SataError;
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uint32_t SataActive;
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uint32_t CommandIssue;
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uint32_t SataNotification;
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uint32_t FISSwitchControl;
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uint32_t Reserved1[11];
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uint32_t Vendor[4];
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};
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struct HBAMemory
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{
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uint32_t HostCapability;
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uint32_t GlobalHostControl;
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uint32_t InterruptStatus;
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uint32_t PortsImplemented;
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uint32_t Version;
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uint32_t CCCControl;
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uint32_t CCCPorts;
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uint32_t EnclosureManagementLocation;
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uint32_t EnclosureManagementControl;
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uint32_t HostCapabilitiesExtended;
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uint32_t BIOSHandoffControlStatus;
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uint8_t Reserved0[0x74];
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uint8_t Vendor[0x60];
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HBAPort Ports[1];
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};
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struct HBACommandHeader
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{
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uint8_t CommandFISLength : 5;
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uint8_t ATAPI : 1;
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uint8_t Write : 1;
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uint8_t Prefetchable : 1;
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uint8_t Reset : 1;
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uint8_t BIST : 1;
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uint8_t ClearBusy : 1;
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uint8_t Reserved0 : 1;
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uint8_t PortMultiplier : 4;
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uint16_t PRDTLength;
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uint32_t PRDBCount;
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uint32_t CommandTableBaseAddress;
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uint32_t CommandTableBaseAddressUpper;
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uint32_t Reserved1[4];
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};
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struct HBAPRDTEntry
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{
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uint32_t DataBaseAddress;
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uint32_t DataBaseAddressUpper;
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uint32_t Reserved0;
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uint32_t ByteCount : 22;
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uint32_t Reserved1 : 9;
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uint32_t InterruptOnCompletion : 1;
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};
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struct HBACommandTable
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{
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uint8_t CommandFIS[64];
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uint8_t ATAPICommand[16];
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uint8_t Reserved[48];
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HBAPRDTEntry PRDTEntry[];
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};
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struct FIS_REG_H2D
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{
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uint8_t FISType;
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uint8_t PortMultiplier : 4;
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uint8_t Reserved0 : 3;
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uint8_t CommandControl : 1;
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uint8_t Command;
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uint8_t FeatureLow;
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uint8_t LBA0;
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uint8_t LBA1;
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uint8_t LBA2;
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uint8_t DeviceRegister;
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uint8_t LBA3;
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uint8_t LBA4;
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uint8_t LBA5;
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uint8_t FeatureHigh;
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uint8_t CountLow;
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uint8_t CountHigh;
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uint8_t ISOCommandCompletion;
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uint8_t Control;
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uint8_t Reserved1[4];
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};
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struct BARData
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{
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uint8_t Type;
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@ -38,8 +177,194 @@ struct BARData
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uint64_t MemoryBase;
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};
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void *operator new(size_t Size) { return KAPI->Memory.RequestPage(Size / KAPI->Memory.PageSize + 1); }
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class Port
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{
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public:
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HBAPort *HBAPortPtr;
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PortType AHCIPortType;
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uint8_t *Buffer;
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uint8_t PortNumber;
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void StartCMD()
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{
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while (HBAPortPtr->CommandStatus & HBA_PxCMD_CR)
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;
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HBAPortPtr->CommandStatus |= HBA_PxCMD_FRE;
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HBAPortPtr->CommandStatus |= HBA_PxCMD_ST;
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}
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void StopCMD()
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{
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HBAPortPtr->CommandStatus &= ~HBA_PxCMD_ST;
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HBAPortPtr->CommandStatus &= ~HBA_PxCMD_FRE;
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while (true)
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{
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if (HBAPortPtr->CommandStatus & HBA_PxCMD_FR)
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continue;
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if (HBAPortPtr->CommandStatus & HBA_PxCMD_CR)
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continue;
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break;
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}
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}
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void Configure()
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{
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StopCMD();
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void *NewBase = KAPI->Memory.RequestPage(1);
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HBAPortPtr->CommandListBase = (uint32_t)(uint64_t)NewBase;
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HBAPortPtr->CommandListBaseUpper = (uint32_t)((uint64_t)NewBase >> 32);
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KAPI->Util.memset(reinterpret_cast<void *>(HBAPortPtr->CommandListBase), 0, 1024);
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void *FISBase = KAPI->Memory.RequestPage(1);
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HBAPortPtr->FISBaseAddress = (uint32_t)(uint64_t)FISBase;
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HBAPortPtr->FISBaseAddressUpper = (uint32_t)((uint64_t)FISBase >> 32);
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KAPI->Util.memset(FISBase, 0, 256);
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HBACommandHeader *CommandHeader = (HBACommandHeader *)((uint64_t)HBAPortPtr->CommandListBase + ((uint64_t)HBAPortPtr->CommandListBaseUpper << 32));
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for (int i = 0; i < 32; i++)
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{
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CommandHeader[i].PRDTLength = 8;
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void *CommandTableAddress = KAPI->Memory.RequestPage(1);
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uint64_t Address = (uint64_t)CommandTableAddress + (i << 8);
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CommandHeader[i].CommandTableBaseAddress = (uint32_t)(uint64_t)Address;
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CommandHeader[i].CommandTableBaseAddressUpper = (uint32_t)((uint64_t)Address >> 32);
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KAPI->Util.memset(CommandTableAddress, 0, 256);
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}
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StartCMD();
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}
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bool ReadWrite(uint64_t Sector, uint32_t SectorCount, uint8_t *Buffer, bool Write)
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{
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if (this->PortNumber == PortType::SATAPI && Write)
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{
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// err("SATAPI port does not support write.");
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KAPI->Util.DebugPrint(((char *)"SATAPI port does not support write." + KAPI->Info.Offset), KAPI->Info.DriverUID);
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return false;
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}
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uint32_t SectorL = (uint32_t)Sector;
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uint32_t SectorH = (uint32_t)(Sector >> 32);
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HBAPortPtr->InterruptStatus = (uint32_t)-1; // Clear pending interrupt bits
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HBACommandHeader *CommandHeader = reinterpret_cast<HBACommandHeader *>(HBAPortPtr->CommandListBase);
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CommandHeader->CommandFISLength = sizeof(FIS_REG_H2D) / sizeof(uint32_t);
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if (Write)
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CommandHeader->Write = 1;
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else
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CommandHeader->Write = 0;
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CommandHeader->PRDTLength = 1;
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HBACommandTable *CommandTable = reinterpret_cast<HBACommandTable *>(CommandHeader->CommandTableBaseAddress);
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KAPI->Util.memset(CommandTable, 0, sizeof(HBACommandTable) + (CommandHeader->PRDTLength - 1) * sizeof(HBAPRDTEntry));
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CommandTable->PRDTEntry[0].DataBaseAddress = (uint32_t)(uint64_t)Buffer;
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CommandTable->PRDTEntry[0].DataBaseAddressUpper = (uint32_t)((uint64_t)Buffer >> 32);
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CommandTable->PRDTEntry[0].ByteCount = (SectorCount << 9) - 1; // 512 bytes per sector
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CommandTable->PRDTEntry[0].InterruptOnCompletion = 1;
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FIS_REG_H2D *CommandFIS = (FIS_REG_H2D *)(&CommandTable->CommandFIS);
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CommandFIS->FISType = FIS_TYPE_REG_H2D;
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CommandFIS->CommandControl = 1;
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if (Write)
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CommandFIS->Command = ATA_CMD_WRITE_DMA_EX;
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else
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CommandFIS->Command = ATA_CMD_READ_DMA_EX;
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CommandFIS->LBA0 = (uint8_t)SectorL;
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CommandFIS->LBA1 = (uint8_t)(SectorL >> 8);
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CommandFIS->LBA2 = (uint8_t)(SectorL >> 16);
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CommandFIS->LBA3 = (uint8_t)SectorH;
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CommandFIS->LBA4 = (uint8_t)(SectorH >> 8);
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CommandFIS->LBA5 = (uint8_t)(SectorH >> 16);
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CommandFIS->DeviceRegister = 1 << 6; // LBA mode
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CommandFIS->CountLow = SectorCount & 0xFF;
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CommandFIS->CountHigh = (SectorCount >> 8) & 0xFF;
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uint64_t Spin = 0;
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while ((HBAPortPtr->TaskFileData & (ATA_DEV_BUSY | ATA_DEV_DRQ)) && Spin < 1000000)
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Spin++;
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if (Spin == 1000000)
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{
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// err("Port not responding.");
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KAPI->Util.DebugPrint(((char *)"Port not responding." + KAPI->Info.Offset), KAPI->Info.DriverUID);
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return false;
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}
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HBAPortPtr->CommandIssue = 1;
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Spin = 0;
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int TryCount = 0;
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while (true)
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{
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if (Spin > 100000000)
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{
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// err("Port %d not responding. (%d)", this->PortNumber, TryCount);
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KAPI->Util.DebugPrint(((char *)"Port not responding." + KAPI->Info.Offset), KAPI->Info.DriverUID);
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Spin = 0;
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TryCount++;
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if (TryCount > 10)
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return false;
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}
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if ((HBAPortPtr->CommandIssue == 0))
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break;
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Spin++;
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if (HBAPortPtr->InterruptStatus & HBA_PxIS_TFES)
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{
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// err("Error reading/writing (%d).", Write);
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KAPI->Util.DebugPrint(((char *)"Error reading/writing." + KAPI->Info.Offset), KAPI->Info.DriverUID);
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return false;
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}
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}
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return true;
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}
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};
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HBAMemory *ABAR;
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Port *Ports[32];
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uint8_t PortCount = 0;
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PCIDeviceHeader *PCIBaseAddress;
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const char *PortTypeName[] = {"None",
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"SATA",
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"SEMB",
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"PM",
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"SATAPI"};
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PortType CheckPortType(HBAPort *Port)
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{
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uint32_t SataStatus = Port->SataStatus;
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uint8_t InterfacePowerManagement = (SataStatus >> 8) & 0b111;
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uint8_t DeviceDetection = SataStatus & 0b111;
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if (DeviceDetection != HBA_PORT_DEV_PRESENT)
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return PortType::None;
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if (InterfacePowerManagement != HBA_PORT_IPM_ACTIVE)
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return PortType::None;
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switch (Port->Signature)
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{
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case SATA_SIG_ATAPI:
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return PortType::SATAPI;
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case SATA_SIG_ATA:
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return PortType::SATA;
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case SATA_SIG_PM:
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return PortType::PM;
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case SATA_SIG_SEMB:
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return PortType::SEMB;
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default:
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return PortType::None;
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}
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}
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int DriverEntry(KernelAPI *Data)
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{
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if (!Data)
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@ -63,14 +388,45 @@ int CallbackHandler(KernelCallback *Data)
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{
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KAPI->Util.DebugPrint(((char *)"Kernel received configuration data." + KAPI->Info.Offset), KAPI->Info.DriverUID);
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PCIBaseAddress = reinterpret_cast<PCIDeviceHeader *>(Data->RawPtr);
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break;
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}
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case InterruptReason:
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{
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ABAR = reinterpret_cast<HBAMemory *>(((PCIHeader0 *)PCIBaseAddress)->BAR5);
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KAPI->Memory.Map((void *)ABAR, (void *)ABAR, (1 << 1));
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uint32_t PortsImplemented = ABAR->PortsImplemented;
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for (int i = 0; i < 32; i++)
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{
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if (PortsImplemented & (1 << i))
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{
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PortType portType = CheckPortType(&ABAR->Ports[i]);
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if (portType == PortType::SATA || portType == PortType::SATAPI)
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{
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// trace("%s drive found at port %d", PortTypeName[portType], i);
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KAPI->Util.DebugPrint(((char *)"SATA drive found." + KAPI->Info.Offset), KAPI->Info.DriverUID);
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Ports[PortCount] = new Port;
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Ports[PortCount]->AHCIPortType = portType;
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Ports[PortCount]->HBAPortPtr = &ABAR->Ports[i];
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Ports[PortCount]->PortNumber = PortCount;
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Ports[PortCount]->Buffer = static_cast<uint8_t *>(KAPI->Memory.RequestPage(1));
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PortCount++;
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}
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else
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{
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if (portType != PortType::None)
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KAPI->Util.DebugPrint(((char *)"Unsupported port type found." + KAPI->Info.Offset), KAPI->Info.DriverUID);
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// warn("Unsupported drive type %s found at port %d", PortTypeName[portType], i);
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}
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}
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}
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for (int i = 0; i < PortCount; i++)
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Ports[i]->Configure();
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break;
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}
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case SendReason:
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{
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Ports[Data->DiskCallback.Port]->ReadWrite(Data->DiskCallback.Sector,
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Data->DiskCallback.SectorCount,
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Data->DiskCallback.Buffer,
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Data->DiskCallback.Write);
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break;
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}
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default:
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