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https://github.com/Fennix-Project/Drivers.git
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Add stub RS-232 implementation
This commit is contained in:
EnderIce2
parent
75a558abc1
commit
84451d9510
GPG Key ID:
EACC3AD603BAB4DD
@ -34,5 +34,6 @@ void PS2MouseInterruptHandler(TrapFrame *);
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int InitializeMouse();
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int FinalizeMouse();
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int DetectPS2Mouse();
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int DetectUART();
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#endif // !__FENNIX_DRIVER_AIP_H__
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@ -194,10 +194,11 @@ int DriverProbe()
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int kbd = DetectPS2Keyboard();
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int mouse = DetectPS2Mouse();
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int uart = DetectUART();
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UnregisterAllInterruptHandlers(__intStub);
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if (kbd != 0 && mouse != 0)
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if (kbd != 0 && mouse != 0 && uart != 0)
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return -ENODEV;
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if (kbd == 0)
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@ -219,11 +220,11 @@ int DriverProbe()
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}
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KernelPrint("PS/2 Port 1: %s (0x%X 0x%X)",
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GetPS2DeviceName(Device1ID[0], Device1ID[1]),
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Device1ID[0], Device1ID[1]);
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GetPS2DeviceName(Device1ID[0], Device1ID[1]),
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Device1ID[0], Device1ID[1]);
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KernelPrint("PS/2 Port 2: %s (0x%X 0x%X)",
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GetPS2DeviceName(Device2ID[0], Device2ID[1]),
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Device2ID[0], Device2ID[1]);
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GetPS2DeviceName(Device2ID[0], Device2ID[1]),
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Device2ID[0], Device2ID[1]);
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return 0;
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}
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646
input/aip/uart.c
Normal file
646
input/aip/uart.c
Normal file
@ -0,0 +1,646 @@
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/*
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This file is part of Fennix Drivers.
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Fennix Drivers is free software: you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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Fennix Drivers is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Fennix Drivers. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include "aip.h"
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#include <errno.h>
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#include <base.h>
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#include <fs.h>
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#include <input.h>
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#include <io.h>
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#define SERIAL_ENABLE_DLAB 0x80
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#define SERIAL_BUFFER_EMPTY 0x20
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enum Ports
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{
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COM1 = 0x3F8,
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COM2 = 0x2F8,
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COM3 = 0x3E8,
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COM4 = 0x2E8,
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COM5 = 0x5F8,
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COM6 = 0x4F8,
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COM7 = 0x5E8,
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COM8 = 0x4E8,
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LPT1 = 0x378,
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LPT2 = 0x278,
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LPT3 = 0x3BC
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};
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enum SerialSpeed
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{
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RATE_50_HI = 0x09,
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RATE_50_LO = 0x00,
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RATE_300_HI = 0x01,
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RATE_300_LO = 0x80,
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RATE_600_HI = 0x00,
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RATE_600_LO = 0xC0,
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RATE_2400_HI = 0x00,
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RATE_2400_LO = 0x30,
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RATE_4800_HI = 0x00,
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RATE_4800_LO = 0x18,
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RATE_9600_HI = 0x00,
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RATE_9600_LO = 0x0C,
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RATE_19200_HI = 0x00,
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RATE_19200_LO = 0x06,
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RATE_38400_HI = 0x00,
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RATE_38400_LO = 0x03,
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RATE_57600_HI = 0x00,
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RATE_57600_LO = 0x02,
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RATE_115200_HI = 0x00,
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RATE_115200_LO = 0x01
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};
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/*
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. Table of Registers .
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/---------------------------------------------------------------------\
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| Base Address | DLAB | R/W | Abr | Register Name |
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|---------------------------------------------------------------------|
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| +0 | =0 | W | - | Transmitter Holding Buffer |
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| | =0 | R | - | Receiver Buffer |
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| | =1 | R/W | - | Divisor Latch Low Byte |
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| +1 | =0 | R/W | IER | Interrupt Enable Register |
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| | =1 | R/W | - | Divisor Latch High Byte |
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| +2 | - | R | IIR | Interrupt Identification Register |
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| | - | W | FCR | FIFO Control Register |
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| +3 | - | R/W | LCR | Line Control Register |
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| +4 | - | R/W | MCR | Modem Control Register |
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| +5 | - | R | LSR | Line Status Register |
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| +6 | - | R | MSR | Modem Status Register |
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| +7 | - | R/W | - | Scratch Register |
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\---------------------------------------------------------------------/
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Source:
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Interfacing the Serial / RS232 Port V5.0
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Table 5 : Table of Registers
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*/
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/** Interrupt Enable Register */
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typedef union
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{
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struct
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{
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/* Enable Received Data Available Interrupt */
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uint8_t InterruptOnReceive : 1;
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/* Enable Transmitter Holding Register Empty Interrupt */
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uint8_t InterruptOnTransmitter : 1;
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/* Enable Receiver Line Status Interrupt */
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uint8_t LineStatusInterrupt : 1;
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/* Enable Modem Status Interrupt */
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uint8_t ModemStatusInterrupt : 1;
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/* Enables Sleep Mode (16750) */
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uint8_t SleepMode : 1;
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/* Enables Low Power Mode (16750) */
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uint8_t LowPowerMode : 1;
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/* Reserved */
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uint8_t __reserved : 2;
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};
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uint8_t raw;
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} IER;
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/** Interrupt Identification Register */
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typedef union
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{
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struct
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{
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/* Interrupt pending */
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uint8_t InterruptPending : 1;
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/**
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* Interrupt Status
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*
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* 00b = Modem Status Interrupt
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* 01b = Transmitter Holding Register Empty Interrupt
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* 10b = Received Data Available Interrupt
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* 11b = Receiver Line Status Interrupt
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*/
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uint8_t InterruptStatus : 2;
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/**
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* 16550 Time-out Interrupt Pending
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*
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* @note Reserved on 8250, 16450
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*/
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uint8_t TimeOutIP : 1;
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/** Reserved */
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uint8_t __reserved : 1;
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/** 64 Byte Fifo Enabled (16750 only) */
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uint8_t FIFO64 : 1;
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/**
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* Enable FIFO
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*
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* 00b = No FIFO
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* 01b = FIFO Enabled but Unusable
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* 11b = FIFO Enabled
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*/
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uint8_t FIFO : 2;
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};
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uint8_t raw;
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} IIR;
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/** First In / First Out Control Register */
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typedef union
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{
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struct
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{
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/** Enable FIFO's */
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uint8_t FIFO : 1;
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/** Clear Receive FIFO */
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uint8_t ClearRX : 1;
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/** Clear Transmit FIFO */
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uint8_t ClearTX : 1;
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/** DMA Mode Select.
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*
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* Change status of RXRDY & TXRDY pins from mode 1 to mode 2.
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*/
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uint8_t DMAMode : 1;
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/** Reserved */
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uint8_t __reserved : 1;
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/** Enable 64 Byte FIFO (16750 only) */
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uint8_t FIFO64 : 1;
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/** Interrupt Trigger Level
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*
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* 00b = 1 Byte
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* 01b = 4 Bytes
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* 10b = 8 Bytes
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* 11b = 14 Bytes
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*/
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uint8_t TriggerLevel : 2;
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};
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uint8_t raw;
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} FCR;
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/** Line Control Register */
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typedef union
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{
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struct
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{
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/** Word Length
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*
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* 00b = 5 bits
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* 01b = 6 bits
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* 10b = 7 bits
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* 11b = 8 bits
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*/
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uint8_t WordLength : 2;
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/** Length of Stop Bit
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*
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* 0b = One Stop Bit
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* 1b = 2 Stop bits for words of length 6,7 or 8 bits or 1.5 Stop Bits for Word lengths of 5 bits.
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*/
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uint8_t StopBit : 1;
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/** Parity Select
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*
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* 0b = No Parity
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* 001b = Odd Parity
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* 011b = Even Parity
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* 101b = High Parity (Sticky)
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* 111b = Low Parity (Sticky)
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*/
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uint8_t Parity : 3;
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/** Set Break Enable */
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uint8_t SetBreak : 1;
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/**
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* Divisor Latch Access
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*
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* 0b = Access to Receiver buffer, Transmitter buffer & Interrupt Enable Register
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* 1b = Divisor Latch Access Bit
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*/
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uint8_t DLAB : 1;
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};
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uint8_t raw;
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} LCR;
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/** Modem Control Register */
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typedef union
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{
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struct
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{
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/** Force Data Terminal Ready */
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uint8_t DataTerminalReady : 1;
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/** Force Request to Send */
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uint8_t RequestToSend : 1;
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/** Auxiliary Output 1 */
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uint8_t Out1 : 1;
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/** Auxiliary Output 2 */
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uint8_t Out2 : 1;
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/** Loopback Mode */
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uint8_t Loopback : 1;
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/** Autoflow Control Enabled (16750 only) */
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uint8_t Autoflow : 1;
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/** Reserved */
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uint8_t __reserved : 2;
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};
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uint8_t raw;
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} MCR;
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/** Line Status Register */
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typedef union
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{
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struct
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{
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/** Data Ready */
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uint8_t DataReady : 1;
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/** Overrun Error */
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uint8_t OverrunError : 1;
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/** Parity Error */
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uint8_t ParityError : 1;
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/** Framing Error */
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uint8_t FramingError : 1;
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/** Break Interrupt */
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uint8_t BreakInterrupt : 1;
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/** Empty Transmitter Holding Register */
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uint8_t EmptyTransmitterHolding : 1;
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/** Empty Data Holding Registers */
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uint8_t EmptyDataHolding : 1;
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/** Error in Received FIFO */
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uint8_t ErrorReceivedFIFO : 1;
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};
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uint8_t raw;
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} LSR;
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/** Modem Status Register */
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typedef union
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{
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struct
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{
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/** Delta Clear to Send */
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uint8_t DeltaClearToSend : 1;
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/** Delta Data Set Ready */
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uint8_t DeltaDataSetReady : 1;
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/** Trailing Edge Ring Indicator */
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uint8_t TrailingEdgeRingIndicator : 1;
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/** Delta Data Carrier Detect */
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uint8_t DeltaDataCarrierDetect : 1;
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/** Clear To Send */
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uint8_t ClearToSend : 1;
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/** Data Set Ready */
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uint8_t DataSetReady : 1;
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/** Ring Indicator */
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uint8_t RingIndicator : 1;
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/** Carrier Detect */
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uint8_t CarrierDetect : 1;
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};
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uint8_t raw;
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} MSR;
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union UARTs
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{
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struct
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{
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uint8_t com1 : 1;
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uint8_t com2 : 1;
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uint8_t com3 : 1;
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uint8_t com4 : 1;
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uint8_t com5 : 1;
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uint8_t com6 : 1;
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uint8_t com7 : 1;
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uint8_t com8 : 1;
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uint8_t lpt1 : 1;
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uint8_t lpt2 : 1;
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uint8_t lpt3 : 1;
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uint8_t __reserved : 5;
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};
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uint16_t raw;
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} uart;
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bool IsDataReady(uint16_t Port)
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{
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LSR lsr;
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lsr.raw = inb(Port + 5);
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return lsr.DataReady;
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}
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bool IsTransmitEmpty(uint16_t Port)
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{
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LSR lsr;
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lsr.raw = inb(Port + 5);
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return lsr.EmptyTransmitterHolding;
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}
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char ReadSerial(uint16_t Port)
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{
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while (!IsDataReady(Port))
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Yield();
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return inb(Port);
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}
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void WriteSerial(uint16_t Port, char Character)
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{
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while (!IsTransmitEmpty(Port))
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Yield();
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outb(Port, Character);
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}
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void ReportSerialReceived(uint8_t Data)
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{
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DebugLog("%c", Data);
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}
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void UartCOM24(TrapFrame *)
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{
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LSR lsr2, lsr4;
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do
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{
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lsr2.raw = inb(COM2 + 5);
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if (lsr2.DataReady)
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ReportSerialReceived(inb(COM2));
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lsr4.raw = inb(COM4 + 5);
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if (lsr4.DataReady)
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ReportSerialReceived(inb(COM4));
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} while (lsr2.DataReady || lsr4.DataReady);
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}
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void UartCOM13(TrapFrame *)
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{
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LSR lsr1, lsr3;
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do
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{
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lsr1.raw = inb(COM1 + 5);
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if (lsr1.DataReady)
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ReportSerialReceived(inb(COM1));
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lsr3.raw = inb(COM3 + 5);
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if (lsr3.DataReady)
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ReportSerialReceived(inb(COM3));
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} while (lsr1.DataReady || lsr3.DataReady);
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}
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bool InitializePort(uint16_t Port)
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{
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ECS;
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LCR lcr = {0};
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IER ier = {0};
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FCR fcr = {0};
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MCR mcr = {0};
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outb(Port + 3, lcr.raw);
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outb(Port + 1, ier.raw);
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lcr.DLAB = 1;
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outb(Port + 3, lcr.raw);
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outb(Port + 0, RATE_115200_LO);
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outb(Port + 1, RATE_115200_HI);
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lcr.DLAB = 0;
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lcr.WordLength = 0b11;
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outb(Port + 3, lcr.raw);
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fcr.FIFO = 1;
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fcr.ClearRX = 1;
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fcr.ClearTX = 1;
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fcr.TriggerLevel = 0b11;
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outb(Port + 2, fcr.raw);
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mcr.DataTerminalReady = 1;
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mcr.RequestToSend = 1;
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mcr.Out2 = 1;
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mcr.Loopback = 1;
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outb(Port + 4, mcr.raw);
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/* Test the serial port */
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outb(Port + 0, 0x48);
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uint8_t result = inb(Port + 0);
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if (result != 0x48)
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{
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/* FIXME: DETECT BAUD RATE
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Do multiple test to check if the output is garbage.
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If so, reduce the baud rate until it works. */
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LCS;
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KernelPrint("Port %#X test failed!", Port);
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return false;
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}
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/* Set normal operation mode */
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mcr.DataTerminalReady = 1;
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mcr.RequestToSend = 1;
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mcr.Out1 = 1;
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mcr.Out2 = 1;
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mcr.Loopback = 0;
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outb(Port + 4, mcr.raw);
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/* Enable interrupts on receive */
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ier.InterruptOnReceive = 1;
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outb(Port + 1, ier.raw);
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RegisterInterruptHandler(3, UartCOM24);
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RegisterInterruptHandler(4, UartCOM13);
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LCS;
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KernelPrint("Port %#X initialized", Port);
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return true;
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}
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int DetectUART()
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{
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uart.com1 = inb(COM1) != 0xFF ? true : false;
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uart.com2 = inb(COM2) != 0xFF ? true : false;
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uart.com3 = inb(COM3) != 0xFF ? true : false;
|
||||
uart.com4 = inb(COM4) != 0xFF ? true : false;
|
||||
uart.com5 = inb(COM5) != 0xFF ? true : false;
|
||||
uart.com6 = inb(COM6) != 0xFF ? true : false;
|
||||
uart.com7 = inb(COM7) != 0xFF ? true : false;
|
||||
uart.com8 = inb(COM8) != 0xFF ? true : false;
|
||||
|
||||
uart.lpt1 = inb(LPT1) != 0xFF ? true : false;
|
||||
uart.lpt2 = inb(LPT2) != 0xFF ? true : false;
|
||||
uart.lpt3 = inb(LPT3) != 0xFF ? true : false;
|
||||
|
||||
if (uart.com1 == true)
|
||||
if (InitializePort(COM1) == false)
|
||||
uart.com1 = false;
|
||||
|
||||
if (uart.com2 == true)
|
||||
if (InitializePort(COM2) == false)
|
||||
uart.com1 = false;
|
||||
|
||||
if (uart.com3 == true)
|
||||
if (InitializePort(COM3) == false)
|
||||
uart.com1 = false;
|
||||
|
||||
if (uart.com4 == true)
|
||||
if (InitializePort(COM4) == false)
|
||||
uart.com1 = false;
|
||||
|
||||
if (uart.com5 == true)
|
||||
if (InitializePort(COM5) == false)
|
||||
uart.com1 = false;
|
||||
|
||||
if (uart.com6 == true)
|
||||
if (InitializePort(COM6) == false)
|
||||
uart.com1 = false;
|
||||
|
||||
if (uart.com7 == true)
|
||||
if (InitializePort(COM7) == false)
|
||||
uart.com1 = false;
|
||||
|
||||
if (uart.com8 == true)
|
||||
if (InitializePort(COM8) == false)
|
||||
uart.com1 = false;
|
||||
|
||||
if (uart.lpt1 == true)
|
||||
KernelPrint("LPT1 is present");
|
||||
|
||||
if (uart.lpt2 == true)
|
||||
KernelPrint("LPT2 is present");
|
||||
|
||||
if (uart.lpt3 == true)
|
||||
KernelPrint("LPT3 is present");
|
||||
return 0;
|
||||
}
|
||||
|
||||
// static int once = 0;
|
||||
// static uint8_t com4 = 0xFF;
|
||||
// if (!once++)
|
||||
// com4 = inb(0x2E8);
|
||||
// if (com4 == 0xFF)
|
||||
// CPU::Halt(true);
|
||||
// char UserInputBuffer[256]{'\0'};
|
||||
// int BackSpaceLimit = 0;
|
||||
// while (true)
|
||||
// {
|
||||
// while ((inb(0x2E8 + 5) & 1) == 0)
|
||||
// CPU::Pause();
|
||||
// char key = inb(0x2E8);
|
||||
// // debug("key: %d", key);
|
||||
// if (key == '\x7f') /* Backspace (DEL) */
|
||||
// {
|
||||
// if (BackSpaceLimit <= 0)
|
||||
// continue;
|
||||
// char keyBuf[5] = {'\b', '\x1b', '[', 'K', '\0'};
|
||||
// ExPrint(keyBuf);
|
||||
// backspace(UserInputBuffer);
|
||||
// BackSpaceLimit--;
|
||||
// continue;
|
||||
// }
|
||||
// else if (key == '\x0d') /* Enter (CR) */
|
||||
// {
|
||||
// UserInput(UserInputBuffer);
|
||||
// BackSpaceLimit = 0;
|
||||
// UserInputBuffer[0] = '\0';
|
||||
// continue;
|
||||
// }
|
||||
// else if (key == '\x1b') /* Escape */
|
||||
// {
|
||||
// char tmp[16]{'\0'};
|
||||
// append(tmp, key);
|
||||
// while ((inb(0x2E8 + 5) & 1) == 0)
|
||||
// CPU::Pause();
|
||||
// char key = inb(0x2E8);
|
||||
// append(tmp, key);
|
||||
// if (key == '[')
|
||||
// {
|
||||
// // 27 91
|
||||
// // < 68
|
||||
// // > 67
|
||||
// // down 66
|
||||
// // up 65
|
||||
// while ((inb(0x2E8 + 5) & 1) == 0)
|
||||
// CPU::Pause();
|
||||
// key = inb(0x2E8);
|
||||
// append(tmp, key);
|
||||
// switch (key)
|
||||
// {
|
||||
// case 'A':
|
||||
// key = KEY_D_UP;
|
||||
// break;
|
||||
// case 'B':
|
||||
// key = KEY_D_DOWN;
|
||||
// break;
|
||||
// case 'C':
|
||||
// key = KEY_D_RIGHT;
|
||||
// break;
|
||||
// case 'D':
|
||||
// key = KEY_D_LEFT;
|
||||
// break;
|
||||
// default:
|
||||
// {
|
||||
// for (size_t i = 0; i < strlen(tmp); i++)
|
||||
// {
|
||||
// if ((int)sizeof(UserInputBuffer) <= BackSpaceLimit)
|
||||
// continue;
|
||||
// append(UserInputBuffer, tmp[i]);
|
||||
// BackSpaceLimit++;
|
||||
// char keyBuf[2] = {(char)tmp[i], '\0'};
|
||||
// ExPrint(keyBuf);
|
||||
// }
|
||||
// continue;
|
||||
// }
|
||||
// }
|
||||
// ArrowInput(key);
|
||||
// continue;
|
||||
// }
|
||||
// }
|
||||
|
||||
// if ((int)sizeof(UserInputBuffer) <= BackSpaceLimit)
|
||||
// continue;
|
||||
// append(UserInputBuffer, key);
|
||||
// BackSpaceLimit++;
|
||||
// char keyBuf[2] = {(char)key, '\0'};
|
||||
// ExPrint(keyBuf);
|
||||
// }
|
||||
Loading…
x
Reference in New Issue
Block a user