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Moved Initialization code

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This commit is contained in:
Alex 2022-10-15 15:31:09 +03:00
parent 004fa99590
commit f7ea052a51
Signed by untrusted user who does not match committer: enderice2
GPG Key ID: EACC3AD603BAB4DD
4 changed files with 95 additions and 108 deletions
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44
Architecture/amd64/cpu/SymmetricMultiprocessing.cpp
View File

@ -58,47 +58,13 @@ CPUData *GetCurrentCPU()
extern "C" void StartCPU() extern "C" void StartCPU()
{ {
CPU::Interrupts(CPU::Disable); CPU::Interrupts(CPU::Disable);
uint64_t CPU_ID; CPU::InitializeFeatures();
// Enable CPU features
{
CPU::x64::CR0 cr0 = CPU::x64::readcr0();
CPU::x64::CR4 cr4 = CPU::x64::readcr4();
uint32_t rax, rbx, rcx, rdx;
CPU::x64::cpuid(0x1, &rax, &rbx, &rcx, &rdx);
if (rdx & CPU::x64::CPUID_FEAT_RDX_SSE)
{
cr0.EM = 0;
cr0.MP = 1;
cr4.OSFXSR = 1;
cr4.OSXMMEXCPT = 1;
}
// Enable cpu cache but... how to use it?
cr0.NW = 0;
cr0.CD = 0;
CPU::x64::cpuid(0x1, &rax, &rbx, &rcx, &rdx);
if (rdx & CPU::x64::CPUID_FEAT_RDX_UMIP)
{
fixme("Not going to enable UMIP.");
// cr4.UMIP = 1;
}
if (rdx & CPU::x64::CPUID_FEAT_RDX_SMEP)
cr4.SMEP = 1;
if (rdx & CPU::x64::CPUID_FEAT_RDX_SMAP)
cr4.SMAP = 1;
CPU::x64::writecr0(cr0);
CPU::x64::writecr4(cr4);
CPU::x64::wrmsr(CPU::x64::MSR_CR_PAT, 0x6 | (0x0 << 8) | (0x1 << 16));
}
// Enable APIC // Enable APIC
{ CPU::x64::wrmsr(CPU::x64::MSR_APIC_BASE, (CPU::x64::rdmsr(CPU::x64::MSR_APIC_BASE) | 0x800) & ~(1 << 10));
CPU::x64::wrmsr(CPU::x64::MSR_APIC_BASE, (CPU::x64::rdmsr(CPU::x64::MSR_APIC_BASE) | 0x800) & ~(1 << 10)); ((APIC::APIC *)Interrupts::apic)->Write(APIC::APIC::APIC_SVR, ((APIC::APIC *)Interrupts::apic)->Read(APIC::APIC::APIC_SVR) | 0x1FF);
((APIC::APIC *)Interrupts::apic)->Write(APIC::APIC::APIC_SVR, ((APIC::APIC *)Interrupts::apic)->Read(APIC::APIC::APIC_SVR) | 0x1FF);
}
uint64_t CPU_ID;
// Set CPU_ID variable using APIC // Set CPU_ID variable using APIC
CPU_ID = ((APIC::APIC *)Interrupts::apic)->Read(APIC::APIC::APIC_ID) >> 24; CPU_ID = ((APIC::APIC *)Interrupts::apic)->Read(APIC::APIC::APIC_ID) >> 24;
@ -120,7 +86,7 @@ namespace SMP
KPrint("VirtualBox detected, disabling SMP"); KPrint("VirtualBox detected, disabling SMP");
return; return;
} }
for (uint8_t i = 0; i < ((ACPI::MADT *)madt)->CPUCores; i++) for (uint8_t i = 0; i < ((ACPI::MADT *)madt)->CPUCores + 1; i++)
{ {
if ((((APIC::APIC *)Interrupts::apic)->Read(APIC::APIC::APIC_ID) >> 24) != ((ACPI::MADT *)madt)->lapic[i]->ACPIProcessorId) if ((((APIC::APIC *)Interrupts::apic)->Read(APIC::APIC::APIC_ID) >> 24) != ((ACPI::MADT *)madt)->lapic[i]->ACPIProcessorId)
{ {

66
Core/CPU.cpp
View File

@ -2,6 +2,9 @@
#include <memory.hpp> #include <memory.hpp>
#include <string.h> #include <string.h>
#include <debug.h>
#include "../kernel.h"
namespace CPU namespace CPU
{ {
@ -201,4 +204,67 @@ namespace CPU
#endif #endif
return PT; return PT;
} }
void InitializeFeatures()
{
#if defined(__amd64__)
static int BSP;
CPU::x64::CR0 cr0 = CPU::x64::readcr0();
CPU::x64::CR4 cr4 = CPU::x64::readcr4();
uint32_t rax, rbx, rcx, rdx;
CPU::x64::cpuid(0x1, &rax, &rbx, &rcx, &rdx);
if (rdx & CPU::x64::CPUID_FEAT_RDX_SSE)
{
debug("Enabling SSE support...");
if (!BSP)
KPrint("SSE is supported.");
cr0.EM = 0;
cr0.MP = 1;
cr4.OSFXSR = 1;
cr4.OSXMMEXCPT = 1;
}
// Enable cpu cache but... how to use it?
cr0.NW = 0;
cr0.CD = 0;
if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_VIRTUALBOX) != 0)
{
debug("Enabling UMIP, SMEP & SMAP support...");
CPU::x64::cpuid(0x1, &rax, &rbx, &rcx, &rdx);
if (rdx & CPU::x64::CPUID_FEAT_RDX_UMIP)
{
if (!BSP)
KPrint("UMIP is supported.");
fixme("Not going to enable UMIP.");
// cr4.UMIP = 1;
}
if (rdx & CPU::x64::CPUID_FEAT_RDX_SMEP)
{
if (!BSP)
KPrint("SMEP is supported.");
cr4.SMEP = 1;
}
if (rdx & CPU::x64::CPUID_FEAT_RDX_SMAP)
{
if (!BSP)
KPrint("SMAP is supported.");
cr4.SMAP = 1;
}
CPU::x64::writecr4(cr4);
}
else
{
if (!BSP)
KPrint("VirtualBox detected. Not using UMIP, SMEP & SMAP");
}
CPU::x64::writecr0(cr0);
debug("Enabling PAT support...");
CPU::x64::wrmsr(CPU::x64::MSR_CR_PAT, 0x6 | (0x0 << 8) | (0x1 << 16));
if (!BSP++)
trace("Features for BSP initialized.");
#elif defined(__i386__)
#elif defined(__aarch64__)
#endif
}
} }

50
Kernel.cpp
View File

@ -62,55 +62,7 @@ EXTERNC void Entry(BootInfo *Info)
KPrint("Initializing GDT and IDT"); KPrint("Initializing GDT and IDT");
Interrupts::Initialize(0); Interrupts::Initialize(0);
KPrint("Initializing CPU features"); KPrint("Initializing CPU features");
#if defined(__amd64__) CPU::InitializeFeatures();
CPU::x64::CR0 cr0 = CPU::x64::readcr0();
CPU::x64::CR4 cr4 = CPU::x64::readcr4();
uint32_t rax, rbx, rcx, rdx;
CPU::x64::cpuid(0x1, &rax, &rbx, &rcx, &rdx);
if (rdx & CPU::x64::CPUID_FEAT_RDX_SSE)
{
debug("Enabling SSE support...");
KPrint("SSE is supported.");
cr0.EM = 0;
cr0.MP = 1;
cr4.OSFXSR = 1;
cr4.OSXMMEXCPT = 1;
}
// Enable cpu cache but... how to use it?
cr0.NW = 0;
cr0.CD = 0;
if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_VIRTUALBOX) != 0)
{
debug("Enabling UMIP, SMEP & SMAP support...");
CPU::x64::cpuid(0x1, &rax, &rbx, &rcx, &rdx);
if (rdx & CPU::x64::CPUID_FEAT_RDX_UMIP)
{
KPrint("UMIP is supported.");
fixme("Not going to enable UMIP.");
// cr4.UMIP = 1;
}
if (rdx & CPU::x64::CPUID_FEAT_RDX_SMEP)
{
KPrint("SMEP is supported.");
cr4.SMEP = 1;
}
if (rdx & CPU::x64::CPUID_FEAT_RDX_SMAP)
{
KPrint("SMAP is supported.");
cr4.SMAP = 1;
}
CPU::x64::writecr4(cr4);
}
else
KPrint("VirtualBox detected. Not using UMIP, SMEP & SMAP");
CPU::x64::writecr0(cr0);
debug("Enabling PAT support...");
CPU::x64::wrmsr(CPU::x64::MSR_CR_PAT, 0x6 | (0x0 << 8) | (0x1 << 16));
#elif defined(__i386__)
#elif defined(__aarch64__)
#endif
KPrint("Loading kernel symbols"); KPrint("Loading kernel symbols");
KernelSymbolTable = new SymbolResolver::Symbols((uint64_t)Info->Kernel.FileBase); KernelSymbolTable = new SymbolResolver::Symbols((uint64_t)Info->Kernel.FileBase);
KPrint("Initializing Power Manager"); KPrint("Initializing Power Manager");

43
include/cpu.hpp
View File

@ -164,6 +164,9 @@ namespace CPU
*/ */
void *PageTable(void *PT = nullptr); void *PageTable(void *PT = nullptr);
/** @brief Used only once. */
void InitializeFeatures();
namespace MemBar namespace MemBar
{ {
static inline void Barrier() static inline void Barrier()
@ -1240,7 +1243,7 @@ namespace CPU
uint64_t Result; uint64_t Result;
#if defined(__amd64__) #if defined(__amd64__)
asmv("mov %%cr0, %[Result]" asmv("mov %%cr0, %[Result]"
: [Result] "=q"(Result)); : [Result] "=q"(Result));
#endif #endif
return (CR0){.raw = Result}; return (CR0){.raw = Result};
} }
@ -1250,7 +1253,7 @@ namespace CPU
uint64_t Result; uint64_t Result;
#if defined(__amd64__) #if defined(__amd64__)
asmv("mov %%cr2, %[Result]" asmv("mov %%cr2, %[Result]"
: [Result] "=q"(Result)); : [Result] "=q"(Result));
#endif #endif
return (CR2){.raw = Result}; return (CR2){.raw = Result};
} }
@ -1260,7 +1263,7 @@ namespace CPU
uint64_t Result; uint64_t Result;
#if defined(__amd64__) #if defined(__amd64__)
asmv("mov %%cr3, %[Result]" asmv("mov %%cr3, %[Result]"
: [Result] "=q"(Result)); : [Result] "=q"(Result));
#endif #endif
return (CR3){.raw = Result}; return (CR3){.raw = Result};
} }
@ -1270,7 +1273,7 @@ namespace CPU
uint64_t Result; uint64_t Result;
#if defined(__amd64__) #if defined(__amd64__)
asmv("mov %%cr4, %[Result]" asmv("mov %%cr4, %[Result]"
: [Result] "=q"(Result)); : [Result] "=q"(Result));
#endif #endif
return (CR4){.raw = Result}; return (CR4){.raw = Result};
} }
@ -1280,7 +1283,7 @@ namespace CPU
uint64_t Result; uint64_t Result;
#if defined(__amd64__) #if defined(__amd64__)
asmv("mov %%cr8, %[Result]" asmv("mov %%cr8, %[Result]"
: [Result] "=q"(Result)); : [Result] "=q"(Result));
#endif #endif
return (CR8){.raw = Result}; return (CR8){.raw = Result};
} }
@ -1289,9 +1292,9 @@ namespace CPU
{ {
#if defined(__amd64__) #if defined(__amd64__)
asmv("mov %[ControlRegister], %%cr0" asmv("mov %[ControlRegister], %%cr0"
: :
: [ControlRegister] "q"(ControlRegister.raw) : [ControlRegister] "q"(ControlRegister.raw)
: "memory"); : "memory");
#endif #endif
} }
@ -1299,9 +1302,9 @@ namespace CPU
{ {
#if defined(__amd64__) #if defined(__amd64__)
asmv("mov %[ControlRegister], %%cr2" asmv("mov %[ControlRegister], %%cr2"
: :
: [ControlRegister] "q"(ControlRegister.raw) : [ControlRegister] "q"(ControlRegister.raw)
: "memory"); : "memory");
#endif #endif
} }
@ -1309,9 +1312,9 @@ namespace CPU
{ {
#if defined(__amd64__) #if defined(__amd64__)
asmv("mov %[ControlRegister], %%cr3" asmv("mov %[ControlRegister], %%cr3"
: :
: [ControlRegister] "q"(ControlRegister.raw) : [ControlRegister] "q"(ControlRegister.raw)
: "memory"); : "memory");
#endif #endif
} }
@ -1319,9 +1322,9 @@ namespace CPU
{ {
#if defined(__amd64__) #if defined(__amd64__)
asmv("mov %[ControlRegister], %%cr4" asmv("mov %[ControlRegister], %%cr4"
: :
: [ControlRegister] "q"(ControlRegister.raw) : [ControlRegister] "q"(ControlRegister.raw)
: "memory"); : "memory");
#endif #endif
} }
@ -1329,9 +1332,9 @@ namespace CPU
{ {
#if defined(__amd64__) #if defined(__amd64__)
asmv("mov %[ControlRegister], %%cr8" asmv("mov %[ControlRegister], %%cr8"
: :
: [ControlRegister] "q"(ControlRegister.raw) : [ControlRegister] "q"(ControlRegister.raw)
: "memory"); : "memory");
#endif #endif
} }