From f7ea052a517edd1c8906096e74a8ce3e07f7ce81 Mon Sep 17 00:00:00 2001 From: Alex Date: Sat, 15 Oct 2022 15:31:09 +0300 Subject: [PATCH] Moved Initialization code --- .../amd64/cpu/SymmetricMultiprocessing.cpp | 44 ++----------- Core/CPU.cpp | 66 +++++++++++++++++++ Kernel.cpp | 50 +------------- include/cpu.hpp | 43 ++++++------ 4 files changed, 95 insertions(+), 108 deletions(-) diff --git a/Architecture/amd64/cpu/SymmetricMultiprocessing.cpp b/Architecture/amd64/cpu/SymmetricMultiprocessing.cpp index c91073e..1725545 100644 --- a/Architecture/amd64/cpu/SymmetricMultiprocessing.cpp +++ b/Architecture/amd64/cpu/SymmetricMultiprocessing.cpp @@ -58,47 +58,13 @@ CPUData *GetCurrentCPU() extern "C" void StartCPU() { CPU::Interrupts(CPU::Disable); - uint64_t CPU_ID; - - // Enable CPU features - { - CPU::x64::CR0 cr0 = CPU::x64::readcr0(); - CPU::x64::CR4 cr4 = CPU::x64::readcr4(); - uint32_t rax, rbx, rcx, rdx; - CPU::x64::cpuid(0x1, &rax, &rbx, &rcx, &rdx); - if (rdx & CPU::x64::CPUID_FEAT_RDX_SSE) - { - cr0.EM = 0; - cr0.MP = 1; - cr4.OSFXSR = 1; - cr4.OSXMMEXCPT = 1; - } - - // Enable cpu cache but... how to use it? - cr0.NW = 0; - cr0.CD = 0; - - CPU::x64::cpuid(0x1, &rax, &rbx, &rcx, &rdx); - if (rdx & CPU::x64::CPUID_FEAT_RDX_UMIP) - { - fixme("Not going to enable UMIP."); - // cr4.UMIP = 1; - } - if (rdx & CPU::x64::CPUID_FEAT_RDX_SMEP) - cr4.SMEP = 1; - if (rdx & CPU::x64::CPUID_FEAT_RDX_SMAP) - cr4.SMAP = 1; - CPU::x64::writecr0(cr0); - CPU::x64::writecr4(cr4); - CPU::x64::wrmsr(CPU::x64::MSR_CR_PAT, 0x6 | (0x0 << 8) | (0x1 << 16)); - } + CPU::InitializeFeatures(); // Enable APIC - { - CPU::x64::wrmsr(CPU::x64::MSR_APIC_BASE, (CPU::x64::rdmsr(CPU::x64::MSR_APIC_BASE) | 0x800) & ~(1 << 10)); - ((APIC::APIC *)Interrupts::apic)->Write(APIC::APIC::APIC_SVR, ((APIC::APIC *)Interrupts::apic)->Read(APIC::APIC::APIC_SVR) | 0x1FF); - } + CPU::x64::wrmsr(CPU::x64::MSR_APIC_BASE, (CPU::x64::rdmsr(CPU::x64::MSR_APIC_BASE) | 0x800) & ~(1 << 10)); + ((APIC::APIC *)Interrupts::apic)->Write(APIC::APIC::APIC_SVR, ((APIC::APIC *)Interrupts::apic)->Read(APIC::APIC::APIC_SVR) | 0x1FF); + uint64_t CPU_ID; // Set CPU_ID variable using APIC CPU_ID = ((APIC::APIC *)Interrupts::apic)->Read(APIC::APIC::APIC_ID) >> 24; @@ -120,7 +86,7 @@ namespace SMP KPrint("VirtualBox detected, disabling SMP"); return; } - for (uint8_t i = 0; i < ((ACPI::MADT *)madt)->CPUCores; i++) + for (uint8_t i = 0; i < ((ACPI::MADT *)madt)->CPUCores + 1; i++) { if ((((APIC::APIC *)Interrupts::apic)->Read(APIC::APIC::APIC_ID) >> 24) != ((ACPI::MADT *)madt)->lapic[i]->ACPIProcessorId) { diff --git a/Core/CPU.cpp b/Core/CPU.cpp index ce99ae0..b49994f 100644 --- a/Core/CPU.cpp +++ b/Core/CPU.cpp @@ -2,6 +2,9 @@ #include #include +#include + +#include "../kernel.h" namespace CPU { @@ -201,4 +204,67 @@ namespace CPU #endif return PT; } + + void InitializeFeatures() + { +#if defined(__amd64__) + static int BSP; + CPU::x64::CR0 cr0 = CPU::x64::readcr0(); + CPU::x64::CR4 cr4 = CPU::x64::readcr4(); + uint32_t rax, rbx, rcx, rdx; + CPU::x64::cpuid(0x1, &rax, &rbx, &rcx, &rdx); + if (rdx & CPU::x64::CPUID_FEAT_RDX_SSE) + { + debug("Enabling SSE support..."); + if (!BSP) + KPrint("SSE is supported."); + cr0.EM = 0; + cr0.MP = 1; + cr4.OSFXSR = 1; + cr4.OSXMMEXCPT = 1; + } + + // Enable cpu cache but... how to use it? + cr0.NW = 0; + cr0.CD = 0; + + if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_VIRTUALBOX) != 0) + { + debug("Enabling UMIP, SMEP & SMAP support..."); + CPU::x64::cpuid(0x1, &rax, &rbx, &rcx, &rdx); + if (rdx & CPU::x64::CPUID_FEAT_RDX_UMIP) + { + if (!BSP) + KPrint("UMIP is supported."); + fixme("Not going to enable UMIP."); + // cr4.UMIP = 1; + } + if (rdx & CPU::x64::CPUID_FEAT_RDX_SMEP) + { + if (!BSP) + KPrint("SMEP is supported."); + cr4.SMEP = 1; + } + if (rdx & CPU::x64::CPUID_FEAT_RDX_SMAP) + { + if (!BSP) + KPrint("SMAP is supported."); + cr4.SMAP = 1; + } + CPU::x64::writecr4(cr4); + } + else + { + if (!BSP) + KPrint("VirtualBox detected. Not using UMIP, SMEP & SMAP"); + } + CPU::x64::writecr0(cr0); + debug("Enabling PAT support..."); + CPU::x64::wrmsr(CPU::x64::MSR_CR_PAT, 0x6 | (0x0 << 8) | (0x1 << 16)); + if (!BSP++) + trace("Features for BSP initialized."); +#elif defined(__i386__) +#elif defined(__aarch64__) +#endif + } } diff --git a/Kernel.cpp b/Kernel.cpp index c1aebe4..3fe5f13 100644 --- a/Kernel.cpp +++ b/Kernel.cpp @@ -62,55 +62,7 @@ EXTERNC void Entry(BootInfo *Info) KPrint("Initializing GDT and IDT"); Interrupts::Initialize(0); KPrint("Initializing CPU features"); -#if defined(__amd64__) - CPU::x64::CR0 cr0 = CPU::x64::readcr0(); - CPU::x64::CR4 cr4 = CPU::x64::readcr4(); - uint32_t rax, rbx, rcx, rdx; - CPU::x64::cpuid(0x1, &rax, &rbx, &rcx, &rdx); - if (rdx & CPU::x64::CPUID_FEAT_RDX_SSE) - { - debug("Enabling SSE support..."); - KPrint("SSE is supported."); - cr0.EM = 0; - cr0.MP = 1; - cr4.OSFXSR = 1; - cr4.OSXMMEXCPT = 1; - } - - // Enable cpu cache but... how to use it? - cr0.NW = 0; - cr0.CD = 0; - - if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_VIRTUALBOX) != 0) - { - debug("Enabling UMIP, SMEP & SMAP support..."); - CPU::x64::cpuid(0x1, &rax, &rbx, &rcx, &rdx); - if (rdx & CPU::x64::CPUID_FEAT_RDX_UMIP) - { - KPrint("UMIP is supported."); - fixme("Not going to enable UMIP."); - // cr4.UMIP = 1; - } - if (rdx & CPU::x64::CPUID_FEAT_RDX_SMEP) - { - KPrint("SMEP is supported."); - cr4.SMEP = 1; - } - if (rdx & CPU::x64::CPUID_FEAT_RDX_SMAP) - { - KPrint("SMAP is supported."); - cr4.SMAP = 1; - } - CPU::x64::writecr4(cr4); - } - else - KPrint("VirtualBox detected. Not using UMIP, SMEP & SMAP"); - CPU::x64::writecr0(cr0); - debug("Enabling PAT support..."); - CPU::x64::wrmsr(CPU::x64::MSR_CR_PAT, 0x6 | (0x0 << 8) | (0x1 << 16)); -#elif defined(__i386__) -#elif defined(__aarch64__) -#endif + CPU::InitializeFeatures(); KPrint("Loading kernel symbols"); KernelSymbolTable = new SymbolResolver::Symbols((uint64_t)Info->Kernel.FileBase); KPrint("Initializing Power Manager"); diff --git a/include/cpu.hpp b/include/cpu.hpp index c782572..e1abfaf 100644 --- a/include/cpu.hpp +++ b/include/cpu.hpp @@ -164,6 +164,9 @@ namespace CPU */ void *PageTable(void *PT = nullptr); + /** @brief Used only once. */ + void InitializeFeatures(); + namespace MemBar { static inline void Barrier() @@ -1240,7 +1243,7 @@ namespace CPU uint64_t Result; #if defined(__amd64__) asmv("mov %%cr0, %[Result]" - : [Result] "=q"(Result)); + : [Result] "=q"(Result)); #endif return (CR0){.raw = Result}; } @@ -1250,7 +1253,7 @@ namespace CPU uint64_t Result; #if defined(__amd64__) asmv("mov %%cr2, %[Result]" - : [Result] "=q"(Result)); + : [Result] "=q"(Result)); #endif return (CR2){.raw = Result}; } @@ -1260,7 +1263,7 @@ namespace CPU uint64_t Result; #if defined(__amd64__) asmv("mov %%cr3, %[Result]" - : [Result] "=q"(Result)); + : [Result] "=q"(Result)); #endif return (CR3){.raw = Result}; } @@ -1270,7 +1273,7 @@ namespace CPU uint64_t Result; #if defined(__amd64__) asmv("mov %%cr4, %[Result]" - : [Result] "=q"(Result)); + : [Result] "=q"(Result)); #endif return (CR4){.raw = Result}; } @@ -1280,7 +1283,7 @@ namespace CPU uint64_t Result; #if defined(__amd64__) asmv("mov %%cr8, %[Result]" - : [Result] "=q"(Result)); + : [Result] "=q"(Result)); #endif return (CR8){.raw = Result}; } @@ -1289,9 +1292,9 @@ namespace CPU { #if defined(__amd64__) asmv("mov %[ControlRegister], %%cr0" - : - : [ControlRegister] "q"(ControlRegister.raw) - : "memory"); + : + : [ControlRegister] "q"(ControlRegister.raw) + : "memory"); #endif } @@ -1299,9 +1302,9 @@ namespace CPU { #if defined(__amd64__) asmv("mov %[ControlRegister], %%cr2" - : - : [ControlRegister] "q"(ControlRegister.raw) - : "memory"); + : + : [ControlRegister] "q"(ControlRegister.raw) + : "memory"); #endif } @@ -1309,9 +1312,9 @@ namespace CPU { #if defined(__amd64__) asmv("mov %[ControlRegister], %%cr3" - : - : [ControlRegister] "q"(ControlRegister.raw) - : "memory"); + : + : [ControlRegister] "q"(ControlRegister.raw) + : "memory"); #endif } @@ -1319,9 +1322,9 @@ namespace CPU { #if defined(__amd64__) asmv("mov %[ControlRegister], %%cr4" - : - : [ControlRegister] "q"(ControlRegister.raw) - : "memory"); + : + : [ControlRegister] "q"(ControlRegister.raw) + : "memory"); #endif } @@ -1329,9 +1332,9 @@ namespace CPU { #if defined(__amd64__) asmv("mov %[ControlRegister], %%cr8" - : - : [ControlRegister] "q"(ControlRegister.raw) - : "memory"); + : + : [ControlRegister] "q"(ControlRegister.raw) + : "memory"); #endif }