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Refactor code to use tab spaces
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EnderIce2
parent
d247dcd4a3
commit
f009f181b0
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EACC3AD603BAB4DD
@ -28,33 +28,33 @@ namespace CPU
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{
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struct
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{
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/** @brief Protection Enable */
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/** Protection Enable */
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uint32_t PE : 1;
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/** @brief Monitor Coprocessor */
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/** Monitor Coprocessor */
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uint32_t MP : 1;
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/** @brief Emulation */
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/** Emulation */
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uint32_t EM : 1;
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/** @brief Task Switched */
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/** Task Switched */
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uint32_t TS : 1;
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/** @brief Extension Type */
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/** Extension Type */
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uint32_t ET : 1;
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/** @brief Numeric Error */
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/** Numeric Error */
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uint32_t NE : 1;
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/** @brief Reserved */
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/** Reserved */
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uint32_t Reserved0 : 10;
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/** @brief Write Protect */
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/** Write Protect */
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uint32_t WP : 1;
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/** @brief Reserved */
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/** Reserved */
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uint32_t Reserved1 : 1;
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/** @brief Alignment Mask */
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/** Alignment Mask */
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uint32_t AM : 1;
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/** @brief Reserved */
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/** Reserved */
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uint32_t Reserved2 : 10;
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/** @brief Not Write-through */
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/** Not Write-through */
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uint32_t NW : 1;
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/** @brief Cache Disable */
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/** Cache Disable */
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uint32_t CD : 1;
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/** @brief Paging */
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/** Paging */
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uint32_t PG : 1;
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};
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uint32_t raw;
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@ -64,7 +64,7 @@ namespace CPU
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{
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struct
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{
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/** @brief Page Fault Linear Address */
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/** Page Fault Linear Address */
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uint32_t PFLA;
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};
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uint32_t raw;
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@ -74,11 +74,11 @@ namespace CPU
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{
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struct
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{
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/** @brief Not used if bit 17 of CR4 is 1 */
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/** Not used if bit 17 of CR4 is 1 */
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uint32_t PWT : 1;
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/** @brief Not used if bit 17 of CR4 is 1 */
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/** Not used if bit 17 of CR4 is 1 */
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uint32_t PCD : 1;
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/** @brief Base of PML4T/PML5T */
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/** Base of PML4T/PML5T */
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uint32_t PDBR;
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};
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uint32_t raw;
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@ -88,55 +88,55 @@ namespace CPU
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{
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struct
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{
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/** @brief Virtual-8086 Mode Extensions */
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/** Virtual-8086 Mode Extensions */
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uint32_t VME : 1;
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/** @brief Protected-Mode Virtual Interrupts */
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/** Protected-Mode Virtual Interrupts */
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uint32_t PVI : 1;
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/** @brief Time Stamp Disable */
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/** Time Stamp Disable */
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uint32_t TSD : 1;
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/** @brief Debugging Extensions */
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/** Debugging Extensions */
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uint32_t DE : 1;
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/** @brief Page Size Extensions */
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/** Page Size Extensions */
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uint32_t PSE : 1;
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/** @brief Physical Address Extension */
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/** Physical Address Extension */
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uint32_t PAE : 1;
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/** @brief Machine Check Enable */
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/** Machine Check Enable */
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uint32_t MCE : 1;
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/** @brief Page Global Enable */
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/** Page Global Enable */
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uint32_t PGE : 1;
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/** @brief Performance Monitoring Counter */
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/** Performance Monitoring Counter */
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uint32_t PCE : 1;
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/** @brief Operating System Support */
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/** Operating System Support */
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uint32_t OSFXSR : 1;
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/** @brief Operating System Support */
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/** Operating System Support */
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uint32_t OSXMMEXCPT : 1;
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/** @brief User-Mode Instruction Prevention */
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/** User-Mode Instruction Prevention */
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uint32_t UMIP : 1;
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/** @brief Linear Address 57bit */
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/** Linear Address 57bit */
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uint32_t LA57 : 1;
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/** @brief VMX Enable */
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/** VMX Enable */
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uint32_t VMXE : 1;
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/** @brief SMX Enable */
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/** SMX Enable */
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uint32_t SMXE : 1;
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/** @brief Reserved */
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/** Reserved */
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uint32_t Reserved0 : 1;
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/** @brief FSGSBASE Enable */
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/** FSGSBASE Enable */
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uint32_t FSGSBASE : 1;
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/** @brief PCID Enable */
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/** PCID Enable */
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uint32_t PCIDE : 1;
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/** @brief XSAVE and Processor Extended States Enable */
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/** XSAVE and Processor Extended States Enable */
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uint32_t OSXSAVE : 1;
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/** @brief Reserved */
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/** Reserved */
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uint32_t Reserved1 : 1;
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/** @brief SMEP Enable */
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/** SMEP Enable */
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uint32_t SMEP : 1;
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/** @brief SMAP Enable */
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/** SMAP Enable */
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uint32_t SMAP : 1;
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/** @brief Protection-Key Enable */
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/** Protection-Key Enable */
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uint32_t PKE : 1;
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/** @brief Control-flow Enforcement Technology*/
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/** Control-flow Enforcement Technology*/
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uint32_t CET : 1;
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/* @brief Enable Protection Keys for Supervisor Mode Pages */
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/* Enable Protection Keys for Supervisor Mode Pages */
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uint32_t PKS : 1;
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};
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uint32_t raw;
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@ -28,33 +28,33 @@ namespace CPU
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{
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struct
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{
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/** @brief Protection Enable */
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/** Protection Enable */
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uint64_t PE : 1;
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/** @brief Monitor Coprocessor */
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/** Monitor Coprocessor */
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uint64_t MP : 1;
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/** @brief Emulation */
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/** Emulation */
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uint64_t EM : 1;
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/** @brief Task Switched */
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/** Task Switched */
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uint64_t TS : 1;
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/** @brief Extension Type */
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/** Extension Type */
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uint64_t ET : 1;
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/** @brief Numeric Error */
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/** Numeric Error */
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uint64_t NE : 1;
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/** @brief Reserved */
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/** Reserved */
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uint64_t Reserved0 : 10;
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/** @brief Write Protect */
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/** Write Protect */
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uint64_t WP : 1;
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/** @brief Reserved */
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/** Reserved */
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uint64_t Reserved1 : 1;
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/** @brief Alignment Mask */
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/** Alignment Mask */
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uint64_t AM : 1;
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/** @brief Reserved */
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/** Reserved */
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uint64_t Reserved2 : 10;
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/** @brief Not Write-through */
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/** Not Write-through */
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uint64_t NW : 1;
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/** @brief Cache Disable */
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/** Cache Disable */
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uint64_t CD : 1;
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/** @brief Paging */
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/** Paging */
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uint64_t PG : 1;
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};
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uint64_t raw;
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@ -64,7 +64,7 @@ namespace CPU
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{
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struct
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{
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/** @brief Page Fault Linear Address */
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/** Page Fault Linear Address */
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uint64_t PFLA;
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};
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uint64_t raw;
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@ -74,11 +74,11 @@ namespace CPU
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{
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struct
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{
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/** @brief Not used if bit 17 of CR4 is 1 */
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/** Not used if bit 17 of CR4 is 1 */
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uint64_t PWT : 1;
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/** @brief Not used if bit 17 of CR4 is 1 */
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/** Not used if bit 17 of CR4 is 1 */
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uint64_t PCD : 1;
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/** @brief Base of PML4T/PML5T */
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/** Base of PML4T/PML5T */
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uint64_t PDBR;
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};
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uint64_t raw;
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@ -88,57 +88,57 @@ namespace CPU
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{
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struct
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{
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/** @brief Virtual-8086 Mode Extensions */
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/** Virtual-8086 Mode Extensions */
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uint64_t VME : 1;
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/** @brief Protected-Mode Virtual Interrupts */
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/** Protected-Mode Virtual Interrupts */
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uint64_t PVI : 1;
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/** @brief Time Stamp Disable */
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/** Time Stamp Disable */
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uint64_t TSD : 1;
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/** @brief Debugging Extensions */
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/** Debugging Extensions */
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uint64_t DE : 1;
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/** @brief Page Size Extensions */
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/** Page Size Extensions */
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uint64_t PSE : 1;
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/** @brief Physical Address Extension */
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/** Physical Address Extension */
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uint64_t PAE : 1;
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/** @brief Machine Check Enable */
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/** Machine Check Enable */
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uint64_t MCE : 1;
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/** @brief Page Global Enable */
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/** Page Global Enable */
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uint64_t PGE : 1;
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/** @brief Performance Monitoring Counter */
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/** Performance Monitoring Counter */
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uint64_t PCE : 1;
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/** @brief FXSAVE/FXRSTOR Support */
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/** FXSAVE/FXRSTOR Support */
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uint64_t OSFXSR : 1;
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/** @brief Unmasked Exception Support */
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/** Unmasked Exception Support */
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uint64_t OSXMMEXCPT : 1;
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/** @brief User-Mode Instruction Prevention */
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/** User-Mode Instruction Prevention */
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uint64_t UMIP : 1;
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/** @brief Linear Address 57bit */
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/** Linear Address 57bit */
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uint64_t LA57 : 1;
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/** @brief VMX Enable */
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/** VMX Enable */
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uint64_t VMXE : 1;
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/** @brief SMX Enable */
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/** SMX Enable */
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uint64_t SMXE : 1;
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/** @brief Reserved */
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/** Reserved */
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uint64_t Reserved0 : 1;
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/** @brief FSGSBASE Enable */
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/** FSGSBASE Enable */
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uint64_t FSGSBASE : 1;
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/** @brief PCID Enable */
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/** PCID Enable */
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uint64_t PCIDE : 1;
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/** @brief XSAVE and Processor Extended States Enable */
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/** XSAVE and Processor Extended States Enable */
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uint64_t OSXSAVE : 1;
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/** @brief Reserved */
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/** Reserved */
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uint64_t Reserved1 : 1;
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/** @brief SMEP Enable */
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/** SMEP Enable */
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uint64_t SMEP : 1;
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/** @brief SMAP Enable */
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/** SMAP Enable */
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uint64_t SMAP : 1;
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/** @brief Protection-Key Enable */
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/** Protection-Key Enable */
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uint64_t PKE : 1;
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/** @brief Control-flow Enforcement Technology*/
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/** Control-flow Enforcement Technology*/
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uint32_t CET : 1;
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/* @brief Enable Protection Keys for Supervisor Mode Pages */
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/* Enable Protection Keys for Supervisor Mode Pages */
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uint32_t PKS : 1;
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/** @brief Reserved */
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/** Reserved */
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uint64_t Reserved2 : 7; // TODO: This could be wrong
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};
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uint64_t raw;
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@ -148,9 +148,9 @@ namespace CPU
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{
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struct
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{
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/** @brief Task Priority Register */
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/** Task Priority Register */
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uint64_t TPR : 4;
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/** @brief Reserved */
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/** Reserved */
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uint64_t Reserved : 60;
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};
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uint64_t raw;
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@ -163,29 +163,29 @@ namespace CPU
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*/
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struct
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{
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/** @brief X87 FPU/MMX/SSE Support (must be 1) */
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/** X87 FPU/MMX/SSE Support (must be 1) */
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uint64_t X87 : 1;
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/** @brief XSAVE support for MXCSR and XMM registers */
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/** XSAVE support for MXCSR and XMM registers */
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uint64_t SSE : 1;
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/** @brief AVX support for YMM registers */
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/** AVX support for YMM registers */
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uint64_t AVX : 1;
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/** @brief MPX support for BND registers */
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/** MPX support for BND registers */
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uint64_t BNDREG : 1;
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/** @brief MPX support for BNDCFGU and BNDSTATUS registers */
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/** MPX support for BNDCFGU and BNDSTATUS registers */
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uint64_t BNDCSR : 1;
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/** @brief AVX-512 support for opmask registers */
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/** AVX-512 support for opmask registers */
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uint64_t OpMask : 1;
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/** @brief AVX-512 enabled and XSAVE support for upper halves of lower ZMM registers */
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/** AVX-512 enabled and XSAVE support for upper halves of lower ZMM registers */
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uint64_t ZMM_HI256 : 1;
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/** @brief AVX-512 enabled and XSAVE support for upper ZMM registers */
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/** AVX-512 enabled and XSAVE support for upper ZMM registers */
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uint64_t HI16_ZMM : 1;
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/** @brief XSAVE support for PKRU register */
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/** XSAVE support for PKRU register */
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uint64_t PKRU : 1;
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/** @brief Reserved */
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/** Reserved */
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uint64_t Reserved0 : 53;
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/** @brief AMD lightweight profiling */
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/** AMD lightweight profiling */
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uint64_t LWP : 1;
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/** @brief Reserved */
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/** Reserved */
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uint64_t Reserved1 : 1;
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};
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uint64_t raw;
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