From f009f181b035a4420286af958583369dfb0e26ad Mon Sep 17 00:00:00 2001 From: EnderIce2 Date: Wed, 13 Mar 2024 18:09:42 +0200 Subject: [PATCH] Refactor code to use tab spaces --- include/cpu/x86/x32/cr.hpp | 374 ++++++++++++++-------------- include/cpu/x86/x64/cr.hpp | 498 ++++++++++++++++++------------------- 2 files changed, 436 insertions(+), 436 deletions(-) diff --git a/include/cpu/x86/x32/cr.hpp b/include/cpu/x86/x32/cr.hpp index 6ecf257..707882f 100644 --- a/include/cpu/x86/x32/cr.hpp +++ b/include/cpu/x86/x32/cr.hpp @@ -22,207 +22,207 @@ namespace CPU { - namespace x32 - { - typedef union CR0 - { - struct - { - /** @brief Protection Enable */ - uint32_t PE : 1; - /** @brief Monitor Coprocessor */ - uint32_t MP : 1; - /** @brief Emulation */ - uint32_t EM : 1; - /** @brief Task Switched */ - uint32_t TS : 1; - /** @brief Extension Type */ - uint32_t ET : 1; - /** @brief Numeric Error */ - uint32_t NE : 1; - /** @brief Reserved */ - uint32_t Reserved0 : 10; - /** @brief Write Protect */ - uint32_t WP : 1; - /** @brief Reserved */ - uint32_t Reserved1 : 1; - /** @brief Alignment Mask */ - uint32_t AM : 1; - /** @brief Reserved */ - uint32_t Reserved2 : 10; - /** @brief Not Write-through */ - uint32_t NW : 1; - /** @brief Cache Disable */ - uint32_t CD : 1; - /** @brief Paging */ - uint32_t PG : 1; - }; - uint32_t raw; - } CR0; + namespace x32 + { + typedef union CR0 + { + struct + { + /** Protection Enable */ + uint32_t PE : 1; + /** Monitor Coprocessor */ + uint32_t MP : 1; + /** Emulation */ + uint32_t EM : 1; + /** Task Switched */ + uint32_t TS : 1; + /** Extension Type */ + uint32_t ET : 1; + /** Numeric Error */ + uint32_t NE : 1; + /** Reserved */ + uint32_t Reserved0 : 10; + /** Write Protect */ + uint32_t WP : 1; + /** Reserved */ + uint32_t Reserved1 : 1; + /** Alignment Mask */ + uint32_t AM : 1; + /** Reserved */ + uint32_t Reserved2 : 10; + /** Not Write-through */ + uint32_t NW : 1; + /** Cache Disable */ + uint32_t CD : 1; + /** Paging */ + uint32_t PG : 1; + }; + uint32_t raw; + } CR0; - typedef union CR2 - { - struct - { - /** @brief Page Fault Linear Address */ - uint32_t PFLA; - }; - uint32_t raw; - } CR2; + typedef union CR2 + { + struct + { + /** Page Fault Linear Address */ + uint32_t PFLA; + }; + uint32_t raw; + } CR2; - typedef union CR3 - { - struct - { - /** @brief Not used if bit 17 of CR4 is 1 */ - uint32_t PWT : 1; - /** @brief Not used if bit 17 of CR4 is 1 */ - uint32_t PCD : 1; - /** @brief Base of PML4T/PML5T */ - uint32_t PDBR; - }; - uint32_t raw; - } CR3; + typedef union CR3 + { + struct + { + /** Not used if bit 17 of CR4 is 1 */ + uint32_t PWT : 1; + /** Not used if bit 17 of CR4 is 1 */ + uint32_t PCD : 1; + /** Base of PML4T/PML5T */ + uint32_t PDBR; + }; + uint32_t raw; + } CR3; - typedef union CR4 - { - struct - { - /** @brief Virtual-8086 Mode Extensions */ - uint32_t VME : 1; - /** @brief Protected-Mode Virtual Interrupts */ - uint32_t PVI : 1; - /** @brief Time Stamp Disable */ - uint32_t TSD : 1; - /** @brief Debugging Extensions */ - uint32_t DE : 1; - /** @brief Page Size Extensions */ - uint32_t PSE : 1; - /** @brief Physical Address Extension */ - uint32_t PAE : 1; - /** @brief Machine Check Enable */ - uint32_t MCE : 1; - /** @brief Page Global Enable */ - uint32_t PGE : 1; - /** @brief Performance Monitoring Counter */ - uint32_t PCE : 1; - /** @brief Operating System Support */ - uint32_t OSFXSR : 1; - /** @brief Operating System Support */ - uint32_t OSXMMEXCPT : 1; - /** @brief User-Mode Instruction Prevention */ - uint32_t UMIP : 1; - /** @brief Linear Address 57bit */ - uint32_t LA57 : 1; - /** @brief VMX Enable */ - uint32_t VMXE : 1; - /** @brief SMX Enable */ - uint32_t SMXE : 1; - /** @brief Reserved */ - uint32_t Reserved0 : 1; - /** @brief FSGSBASE Enable */ - uint32_t FSGSBASE : 1; - /** @brief PCID Enable */ - uint32_t PCIDE : 1; - /** @brief XSAVE and Processor Extended States Enable */ - uint32_t OSXSAVE : 1; - /** @brief Reserved */ - uint32_t Reserved1 : 1; - /** @brief SMEP Enable */ - uint32_t SMEP : 1; - /** @brief SMAP Enable */ - uint32_t SMAP : 1; - /** @brief Protection-Key Enable */ - uint32_t PKE : 1; - /** @brief Control-flow Enforcement Technology*/ - uint32_t CET : 1; - /* @brief Enable Protection Keys for Supervisor Mode Pages */ - uint32_t PKS : 1; - }; - uint32_t raw; - } CR4; + typedef union CR4 + { + struct + { + /** Virtual-8086 Mode Extensions */ + uint32_t VME : 1; + /** Protected-Mode Virtual Interrupts */ + uint32_t PVI : 1; + /** Time Stamp Disable */ + uint32_t TSD : 1; + /** Debugging Extensions */ + uint32_t DE : 1; + /** Page Size Extensions */ + uint32_t PSE : 1; + /** Physical Address Extension */ + uint32_t PAE : 1; + /** Machine Check Enable */ + uint32_t MCE : 1; + /** Page Global Enable */ + uint32_t PGE : 1; + /** Performance Monitoring Counter */ + uint32_t PCE : 1; + /** Operating System Support */ + uint32_t OSFXSR : 1; + /** Operating System Support */ + uint32_t OSXMMEXCPT : 1; + /** User-Mode Instruction Prevention */ + uint32_t UMIP : 1; + /** Linear Address 57bit */ + uint32_t LA57 : 1; + /** VMX Enable */ + uint32_t VMXE : 1; + /** SMX Enable */ + uint32_t SMXE : 1; + /** Reserved */ + uint32_t Reserved0 : 1; + /** FSGSBASE Enable */ + uint32_t FSGSBASE : 1; + /** PCID Enable */ + uint32_t PCIDE : 1; + /** XSAVE and Processor Extended States Enable */ + uint32_t OSXSAVE : 1; + /** Reserved */ + uint32_t Reserved1 : 1; + /** SMEP Enable */ + uint32_t SMEP : 1; + /** SMAP Enable */ + uint32_t SMAP : 1; + /** Protection-Key Enable */ + uint32_t PKE : 1; + /** Control-flow Enforcement Technology*/ + uint32_t CET : 1; + /* Enable Protection Keys for Supervisor Mode Pages */ + uint32_t PKS : 1; + }; + uint32_t raw; + } CR4; #if defined(a32) - nsa static inline CR0 readcr0() - { - uint32_t Result = 0; - asmv("mov %%cr0, %[Result]" - : [Result] "=q"(Result)); - return (CR0){.raw = Result}; - } + nsa static inline CR0 readcr0() + { + uint32_t Result = 0; + asmv("mov %%cr0, %[Result]" + : [Result] "=q"(Result)); + return (CR0){.raw = Result}; + } - nsa static inline CR2 readcr2() - { - uint32_t Result = 0; - asmv("mov %%cr2, %[Result]" - : [Result] "=q"(Result)); - return (CR2){.raw = Result}; - } + nsa static inline CR2 readcr2() + { + uint32_t Result = 0; + asmv("mov %%cr2, %[Result]" + : [Result] "=q"(Result)); + return (CR2){.raw = Result}; + } - nsa static inline CR3 readcr3() - { - uint32_t Result = 0; - asmv("mov %%cr3, %[Result]" - : [Result] "=q"(Result)); - return (CR3){.raw = Result}; - } + nsa static inline CR3 readcr3() + { + uint32_t Result = 0; + asmv("mov %%cr3, %[Result]" + : [Result] "=q"(Result)); + return (CR3){.raw = Result}; + } - nsa static inline CR4 readcr4() - { - uint32_t Result = 0; - asmv("mov %%cr4, %[Result]" - : [Result] "=q"(Result)); - return (CR4){.raw = Result}; - } + nsa static inline CR4 readcr4() + { + uint32_t Result = 0; + asmv("mov %%cr4, %[Result]" + : [Result] "=q"(Result)); + return (CR4){.raw = Result}; + } - nsa static inline CR8 readcr8() - { - uint32_t Result = 0; - asmv("mov %%cr8, %[Result]" - : [Result] "=q"(Result)); - return (CR8){.raw = Result}; - } + nsa static inline CR8 readcr8() + { + uint32_t Result = 0; + asmv("mov %%cr8, %[Result]" + : [Result] "=q"(Result)); + return (CR8){.raw = Result}; + } - nsa static inline void writecr0(CR0 ControlRegister) - { - asmv("mov %[ControlRegister], %%cr0" - : - : [ControlRegister] "q"(ControlRegister.raw) - : "memory"); - } + nsa static inline void writecr0(CR0 ControlRegister) + { + asmv("mov %[ControlRegister], %%cr0" + : + : [ControlRegister] "q"(ControlRegister.raw) + : "memory"); + } - nsa static inline void writecr2(CR2 ControlRegister) - { - asmv("mov %[ControlRegister], %%cr2" - : - : [ControlRegister] "q"(ControlRegister.raw) - : "memory"); - } + nsa static inline void writecr2(CR2 ControlRegister) + { + asmv("mov %[ControlRegister], %%cr2" + : + : [ControlRegister] "q"(ControlRegister.raw) + : "memory"); + } - nsa static inline void writecr3(CR3 ControlRegister) - { - asmv("mov %[ControlRegister], %%cr3" - : - : [ControlRegister] "q"(ControlRegister.raw) - : "memory"); - } + nsa static inline void writecr3(CR3 ControlRegister) + { + asmv("mov %[ControlRegister], %%cr3" + : + : [ControlRegister] "q"(ControlRegister.raw) + : "memory"); + } - nsa static inline void writecr4(CR4 ControlRegister) - { - asmv("mov %[ControlRegister], %%cr4" - : - : [ControlRegister] "q"(ControlRegister.raw) - : "memory"); - } + nsa static inline void writecr4(CR4 ControlRegister) + { + asmv("mov %[ControlRegister], %%cr4" + : + : [ControlRegister] "q"(ControlRegister.raw) + : "memory"); + } - nsa static inline void writecr8(CR8 ControlRegister) - { - asmv("mov %[ControlRegister], %%cr8" - : - : [ControlRegister] "q"(ControlRegister.raw) - : "memory"); - } + nsa static inline void writecr8(CR8 ControlRegister) + { + asmv("mov %[ControlRegister], %%cr8" + : + : [ControlRegister] "q"(ControlRegister.raw) + : "memory"); + } #endif - } + } } #endif // !__FENNIX_KERNEL_CPU_x32_CR_H__ diff --git a/include/cpu/x86/x64/cr.hpp b/include/cpu/x86/x64/cr.hpp index adfa982..1ed53aa 100644 --- a/include/cpu/x86/x64/cr.hpp +++ b/include/cpu/x86/x64/cr.hpp @@ -22,275 +22,275 @@ namespace CPU { - namespace x64 - { - typedef union CR0 - { - struct - { - /** @brief Protection Enable */ - uint64_t PE : 1; - /** @brief Monitor Coprocessor */ - uint64_t MP : 1; - /** @brief Emulation */ - uint64_t EM : 1; - /** @brief Task Switched */ - uint64_t TS : 1; - /** @brief Extension Type */ - uint64_t ET : 1; - /** @brief Numeric Error */ - uint64_t NE : 1; - /** @brief Reserved */ - uint64_t Reserved0 : 10; - /** @brief Write Protect */ - uint64_t WP : 1; - /** @brief Reserved */ - uint64_t Reserved1 : 1; - /** @brief Alignment Mask */ - uint64_t AM : 1; - /** @brief Reserved */ - uint64_t Reserved2 : 10; - /** @brief Not Write-through */ - uint64_t NW : 1; - /** @brief Cache Disable */ - uint64_t CD : 1; - /** @brief Paging */ - uint64_t PG : 1; - }; - uint64_t raw; - } CR0; + namespace x64 + { + typedef union CR0 + { + struct + { + /** Protection Enable */ + uint64_t PE : 1; + /** Monitor Coprocessor */ + uint64_t MP : 1; + /** Emulation */ + uint64_t EM : 1; + /** Task Switched */ + uint64_t TS : 1; + /** Extension Type */ + uint64_t ET : 1; + /** Numeric Error */ + uint64_t NE : 1; + /** Reserved */ + uint64_t Reserved0 : 10; + /** Write Protect */ + uint64_t WP : 1; + /** Reserved */ + uint64_t Reserved1 : 1; + /** Alignment Mask */ + uint64_t AM : 1; + /** Reserved */ + uint64_t Reserved2 : 10; + /** Not Write-through */ + uint64_t NW : 1; + /** Cache Disable */ + uint64_t CD : 1; + /** Paging */ + uint64_t PG : 1; + }; + uint64_t raw; + } CR0; - typedef union CR2 - { - struct - { - /** @brief Page Fault Linear Address */ - uint64_t PFLA; - }; - uint64_t raw; - } CR2; + typedef union CR2 + { + struct + { + /** Page Fault Linear Address */ + uint64_t PFLA; + }; + uint64_t raw; + } CR2; - typedef union CR3 - { - struct - { - /** @brief Not used if bit 17 of CR4 is 1 */ - uint64_t PWT : 1; - /** @brief Not used if bit 17 of CR4 is 1 */ - uint64_t PCD : 1; - /** @brief Base of PML4T/PML5T */ - uint64_t PDBR; - }; - uint64_t raw; - } CR3; + typedef union CR3 + { + struct + { + /** Not used if bit 17 of CR4 is 1 */ + uint64_t PWT : 1; + /** Not used if bit 17 of CR4 is 1 */ + uint64_t PCD : 1; + /** Base of PML4T/PML5T */ + uint64_t PDBR; + }; + uint64_t raw; + } CR3; - typedef union CR4 - { - struct - { - /** @brief Virtual-8086 Mode Extensions */ - uint64_t VME : 1; - /** @brief Protected-Mode Virtual Interrupts */ - uint64_t PVI : 1; - /** @brief Time Stamp Disable */ - uint64_t TSD : 1; - /** @brief Debugging Extensions */ - uint64_t DE : 1; - /** @brief Page Size Extensions */ - uint64_t PSE : 1; - /** @brief Physical Address Extension */ - uint64_t PAE : 1; - /** @brief Machine Check Enable */ - uint64_t MCE : 1; - /** @brief Page Global Enable */ - uint64_t PGE : 1; - /** @brief Performance Monitoring Counter */ - uint64_t PCE : 1; - /** @brief FXSAVE/FXRSTOR Support */ - uint64_t OSFXSR : 1; - /** @brief Unmasked Exception Support */ - uint64_t OSXMMEXCPT : 1; - /** @brief User-Mode Instruction Prevention */ - uint64_t UMIP : 1; - /** @brief Linear Address 57bit */ - uint64_t LA57 : 1; - /** @brief VMX Enable */ - uint64_t VMXE : 1; - /** @brief SMX Enable */ - uint64_t SMXE : 1; - /** @brief Reserved */ - uint64_t Reserved0 : 1; - /** @brief FSGSBASE Enable */ - uint64_t FSGSBASE : 1; - /** @brief PCID Enable */ - uint64_t PCIDE : 1; - /** @brief XSAVE and Processor Extended States Enable */ - uint64_t OSXSAVE : 1; - /** @brief Reserved */ - uint64_t Reserved1 : 1; - /** @brief SMEP Enable */ - uint64_t SMEP : 1; - /** @brief SMAP Enable */ - uint64_t SMAP : 1; - /** @brief Protection-Key Enable */ - uint64_t PKE : 1; - /** @brief Control-flow Enforcement Technology*/ - uint32_t CET : 1; - /* @brief Enable Protection Keys for Supervisor Mode Pages */ - uint32_t PKS : 1; - /** @brief Reserved */ - uint64_t Reserved2 : 7; // TODO: This could be wrong - }; - uint64_t raw; - } CR4; + typedef union CR4 + { + struct + { + /** Virtual-8086 Mode Extensions */ + uint64_t VME : 1; + /** Protected-Mode Virtual Interrupts */ + uint64_t PVI : 1; + /** Time Stamp Disable */ + uint64_t TSD : 1; + /** Debugging Extensions */ + uint64_t DE : 1; + /** Page Size Extensions */ + uint64_t PSE : 1; + /** Physical Address Extension */ + uint64_t PAE : 1; + /** Machine Check Enable */ + uint64_t MCE : 1; + /** Page Global Enable */ + uint64_t PGE : 1; + /** Performance Monitoring Counter */ + uint64_t PCE : 1; + /** FXSAVE/FXRSTOR Support */ + uint64_t OSFXSR : 1; + /** Unmasked Exception Support */ + uint64_t OSXMMEXCPT : 1; + /** User-Mode Instruction Prevention */ + uint64_t UMIP : 1; + /** Linear Address 57bit */ + uint64_t LA57 : 1; + /** VMX Enable */ + uint64_t VMXE : 1; + /** SMX Enable */ + uint64_t SMXE : 1; + /** Reserved */ + uint64_t Reserved0 : 1; + /** FSGSBASE Enable */ + uint64_t FSGSBASE : 1; + /** PCID Enable */ + uint64_t PCIDE : 1; + /** XSAVE and Processor Extended States Enable */ + uint64_t OSXSAVE : 1; + /** Reserved */ + uint64_t Reserved1 : 1; + /** SMEP Enable */ + uint64_t SMEP : 1; + /** SMAP Enable */ + uint64_t SMAP : 1; + /** Protection-Key Enable */ + uint64_t PKE : 1; + /** Control-flow Enforcement Technology*/ + uint32_t CET : 1; + /* Enable Protection Keys for Supervisor Mode Pages */ + uint32_t PKS : 1; + /** Reserved */ + uint64_t Reserved2 : 7; // TODO: This could be wrong + }; + uint64_t raw; + } CR4; - typedef union CR8 - { - struct - { - /** @brief Task Priority Register */ - uint64_t TPR : 4; - /** @brief Reserved */ + typedef union CR8 + { + struct + { + /** Task Priority Register */ + uint64_t TPR : 4; + /** Reserved */ uint64_t Reserved : 60; - }; - uint64_t raw; - } CR8; + }; + uint64_t raw; + } CR8; - typedef union XCR0 - { - /* - On https://wiki.osdev.org/CPU_Registers_x86#XCR0 says that the PKRU bit is 9? - */ - struct - { - /** @brief X87 FPU/MMX/SSE Support (must be 1) */ - uint64_t X87 : 1; - /** @brief XSAVE support for MXCSR and XMM registers */ - uint64_t SSE : 1; - /** @brief AVX support for YMM registers */ - uint64_t AVX : 1; - /** @brief MPX support for BND registers */ - uint64_t BNDREG : 1; - /** @brief MPX support for BNDCFGU and BNDSTATUS registers */ - uint64_t BNDCSR : 1; - /** @brief AVX-512 support for opmask registers */ - uint64_t OpMask : 1; - /** @brief AVX-512 enabled and XSAVE support for upper halves of lower ZMM registers */ - uint64_t ZMM_HI256 : 1; - /** @brief AVX-512 enabled and XSAVE support for upper ZMM registers */ - uint64_t HI16_ZMM : 1; - /** @brief XSAVE support for PKRU register */ - uint64_t PKRU : 1; - /** @brief Reserved */ - uint64_t Reserved0 : 53; - /** @brief AMD lightweight profiling */ - uint64_t LWP : 1; - /** @brief Reserved */ - uint64_t Reserved1 : 1; - }; - uint64_t raw; - } XCR0; + typedef union XCR0 + { + /* + On https://wiki.osdev.org/CPU_Registers_x86#XCR0 says that the PKRU bit is 9? + */ + struct + { + /** X87 FPU/MMX/SSE Support (must be 1) */ + uint64_t X87 : 1; + /** XSAVE support for MXCSR and XMM registers */ + uint64_t SSE : 1; + /** AVX support for YMM registers */ + uint64_t AVX : 1; + /** MPX support for BND registers */ + uint64_t BNDREG : 1; + /** MPX support for BNDCFGU and BNDSTATUS registers */ + uint64_t BNDCSR : 1; + /** AVX-512 support for opmask registers */ + uint64_t OpMask : 1; + /** AVX-512 enabled and XSAVE support for upper halves of lower ZMM registers */ + uint64_t ZMM_HI256 : 1; + /** AVX-512 enabled and XSAVE support for upper ZMM registers */ + uint64_t HI16_ZMM : 1; + /** XSAVE support for PKRU register */ + uint64_t PKRU : 1; + /** Reserved */ + uint64_t Reserved0 : 53; + /** AMD lightweight profiling */ + uint64_t LWP : 1; + /** Reserved */ + uint64_t Reserved1 : 1; + }; + uint64_t raw; + } XCR0; #if defined(a64) - nsa static inline CR0 readcr0() - { - uint64_t Result = 0; - asmv("mov %%cr0, %[Result]" - : [Result] "=q"(Result)); - return (CR0){.raw = Result}; - } + nsa static inline CR0 readcr0() + { + uint64_t Result = 0; + asmv("mov %%cr0, %[Result]" + : [Result] "=q"(Result)); + return (CR0){.raw = Result}; + } - nsa static inline CR2 readcr2() - { - uint64_t Result = 0; - asmv("mov %%cr2, %[Result]" - : [Result] "=q"(Result)); - return (CR2){.raw = Result}; - } + nsa static inline CR2 readcr2() + { + uint64_t Result = 0; + asmv("mov %%cr2, %[Result]" + : [Result] "=q"(Result)); + return (CR2){.raw = Result}; + } - nsa static inline CR3 readcr3() - { - uint64_t Result = 0; - asmv("mov %%cr3, %[Result]" - : [Result] "=q"(Result)); - return (CR3){.raw = Result}; - } + nsa static inline CR3 readcr3() + { + uint64_t Result = 0; + asmv("mov %%cr3, %[Result]" + : [Result] "=q"(Result)); + return (CR3){.raw = Result}; + } - nsa static inline CR4 readcr4() - { - uint64_t Result = 0; - asmv("mov %%cr4, %[Result]" - : [Result] "=q"(Result)); - return (CR4){.raw = Result}; - } + nsa static inline CR4 readcr4() + { + uint64_t Result = 0; + asmv("mov %%cr4, %[Result]" + : [Result] "=q"(Result)); + return (CR4){.raw = Result}; + } - nsa static inline CR8 readcr8() - { - uint64_t Result = 0; - asmv("mov %%cr8, %[Result]" - : [Result] "=q"(Result)); - return (CR8){.raw = Result}; - } + nsa static inline CR8 readcr8() + { + uint64_t Result = 0; + asmv("mov %%cr8, %[Result]" + : [Result] "=q"(Result)); + return (CR8){.raw = Result}; + } - nsa static inline XCR0 readxcr0() - { - uint64_t Result = 0; - asmv("xgetbv" - : "=a"(Result) - : "c"(0) - : "edx"); - return (XCR0){.raw = Result}; - } + nsa static inline XCR0 readxcr0() + { + uint64_t Result = 0; + asmv("xgetbv" + : "=a"(Result) + : "c"(0) + : "edx"); + return (XCR0){.raw = Result}; + } - nsa static inline void writecr0(CR0 ControlRegister) - { - asmv("mov %[ControlRegister], %%cr0" - : - : [ControlRegister] "q"(ControlRegister.raw) - : "memory"); - } + nsa static inline void writecr0(CR0 ControlRegister) + { + asmv("mov %[ControlRegister], %%cr0" + : + : [ControlRegister] "q"(ControlRegister.raw) + : "memory"); + } - nsa static inline void writecr2(CR2 ControlRegister) - { - asmv("mov %[ControlRegister], %%cr2" - : - : [ControlRegister] "q"(ControlRegister.raw) - : "memory"); - } + nsa static inline void writecr2(CR2 ControlRegister) + { + asmv("mov %[ControlRegister], %%cr2" + : + : [ControlRegister] "q"(ControlRegister.raw) + : "memory"); + } - nsa static inline void writecr3(CR3 ControlRegister) - { - asmv("mov %[ControlRegister], %%cr3" - : - : [ControlRegister] "q"(ControlRegister.raw) - : "memory"); - } + nsa static inline void writecr3(CR3 ControlRegister) + { + asmv("mov %[ControlRegister], %%cr3" + : + : [ControlRegister] "q"(ControlRegister.raw) + : "memory"); + } - nsa static inline void writecr4(CR4 ControlRegister) - { - asmv("mov %[ControlRegister], %%cr4" - : - : [ControlRegister] "q"(ControlRegister.raw) - : "memory"); - } + nsa static inline void writecr4(CR4 ControlRegister) + { + asmv("mov %[ControlRegister], %%cr4" + : + : [ControlRegister] "q"(ControlRegister.raw) + : "memory"); + } - nsa static inline void writecr8(CR8 ControlRegister) - { - asmv("mov %[ControlRegister], %%cr8" - : - : [ControlRegister] "q"(ControlRegister.raw) - : "memory"); - } + nsa static inline void writecr8(CR8 ControlRegister) + { + asmv("mov %[ControlRegister], %%cr8" + : + : [ControlRegister] "q"(ControlRegister.raw) + : "memory"); + } - nsa static inline void writexcr0(XCR0 ControlRegister) - { - asmv("xsetbv" - : - : "a"(ControlRegister.raw), "c"(0) - : "edx"); - } + nsa static inline void writexcr0(XCR0 ControlRegister) + { + asmv("xsetbv" + : + : "a"(ControlRegister.raw), "c"(0) + : "edx"); + } #endif - } + } } #endif // !__FENNIX_KERNEL_CPU_x64_CR_H__