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Refactor code to use tab spaces
This commit is contained in:
EnderIce2
parent
d247dcd4a3
commit
f009f181b0
GPG Key ID:
EACC3AD603BAB4DD
@ -22,207 +22,207 @@
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namespace CPU
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namespace CPU
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{
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{
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namespace x32
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namespace x32
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{
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{
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typedef union CR0
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typedef union CR0
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{
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{
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struct
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struct
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{
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{
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/** @brief Protection Enable */
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/** Protection Enable */
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uint32_t PE : 1;
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uint32_t PE : 1;
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/** @brief Monitor Coprocessor */
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/** Monitor Coprocessor */
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uint32_t MP : 1;
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uint32_t MP : 1;
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/** @brief Emulation */
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/** Emulation */
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uint32_t EM : 1;
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uint32_t EM : 1;
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/** @brief Task Switched */
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/** Task Switched */
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uint32_t TS : 1;
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uint32_t TS : 1;
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/** @brief Extension Type */
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/** Extension Type */
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uint32_t ET : 1;
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uint32_t ET : 1;
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/** @brief Numeric Error */
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/** Numeric Error */
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uint32_t NE : 1;
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uint32_t NE : 1;
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/** @brief Reserved */
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/** Reserved */
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uint32_t Reserved0 : 10;
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uint32_t Reserved0 : 10;
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/** @brief Write Protect */
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/** Write Protect */
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uint32_t WP : 1;
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uint32_t WP : 1;
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/** @brief Reserved */
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/** Reserved */
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uint32_t Reserved1 : 1;
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uint32_t Reserved1 : 1;
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/** @brief Alignment Mask */
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/** Alignment Mask */
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uint32_t AM : 1;
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uint32_t AM : 1;
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/** @brief Reserved */
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/** Reserved */
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uint32_t Reserved2 : 10;
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uint32_t Reserved2 : 10;
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/** @brief Not Write-through */
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/** Not Write-through */
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uint32_t NW : 1;
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uint32_t NW : 1;
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/** @brief Cache Disable */
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/** Cache Disable */
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uint32_t CD : 1;
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uint32_t CD : 1;
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/** @brief Paging */
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/** Paging */
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uint32_t PG : 1;
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uint32_t PG : 1;
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};
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};
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uint32_t raw;
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uint32_t raw;
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} CR0;
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} CR0;
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typedef union CR2
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typedef union CR2
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{
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{
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struct
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struct
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{
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{
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/** @brief Page Fault Linear Address */
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/** Page Fault Linear Address */
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uint32_t PFLA;
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uint32_t PFLA;
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};
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};
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uint32_t raw;
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uint32_t raw;
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} CR2;
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} CR2;
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typedef union CR3
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typedef union CR3
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{
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{
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struct
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struct
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{
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{
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/** @brief Not used if bit 17 of CR4 is 1 */
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/** Not used if bit 17 of CR4 is 1 */
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uint32_t PWT : 1;
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uint32_t PWT : 1;
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/** @brief Not used if bit 17 of CR4 is 1 */
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/** Not used if bit 17 of CR4 is 1 */
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uint32_t PCD : 1;
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uint32_t PCD : 1;
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/** @brief Base of PML4T/PML5T */
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/** Base of PML4T/PML5T */
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uint32_t PDBR;
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uint32_t PDBR;
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};
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};
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uint32_t raw;
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uint32_t raw;
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} CR3;
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} CR3;
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typedef union CR4
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typedef union CR4
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{
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{
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struct
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struct
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{
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{
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/** @brief Virtual-8086 Mode Extensions */
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/** Virtual-8086 Mode Extensions */
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uint32_t VME : 1;
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uint32_t VME : 1;
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/** @brief Protected-Mode Virtual Interrupts */
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/** Protected-Mode Virtual Interrupts */
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uint32_t PVI : 1;
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uint32_t PVI : 1;
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/** @brief Time Stamp Disable */
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/** Time Stamp Disable */
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uint32_t TSD : 1;
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uint32_t TSD : 1;
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/** @brief Debugging Extensions */
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/** Debugging Extensions */
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uint32_t DE : 1;
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uint32_t DE : 1;
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/** @brief Page Size Extensions */
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/** Page Size Extensions */
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uint32_t PSE : 1;
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uint32_t PSE : 1;
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/** @brief Physical Address Extension */
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/** Physical Address Extension */
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uint32_t PAE : 1;
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uint32_t PAE : 1;
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/** @brief Machine Check Enable */
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/** Machine Check Enable */
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uint32_t MCE : 1;
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uint32_t MCE : 1;
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/** @brief Page Global Enable */
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/** Page Global Enable */
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uint32_t PGE : 1;
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uint32_t PGE : 1;
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/** @brief Performance Monitoring Counter */
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/** Performance Monitoring Counter */
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uint32_t PCE : 1;
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uint32_t PCE : 1;
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/** @brief Operating System Support */
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/** Operating System Support */
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uint32_t OSFXSR : 1;
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uint32_t OSFXSR : 1;
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/** @brief Operating System Support */
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/** Operating System Support */
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uint32_t OSXMMEXCPT : 1;
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uint32_t OSXMMEXCPT : 1;
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/** @brief User-Mode Instruction Prevention */
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/** User-Mode Instruction Prevention */
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uint32_t UMIP : 1;
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uint32_t UMIP : 1;
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/** @brief Linear Address 57bit */
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/** Linear Address 57bit */
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uint32_t LA57 : 1;
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uint32_t LA57 : 1;
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/** @brief VMX Enable */
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/** VMX Enable */
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uint32_t VMXE : 1;
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uint32_t VMXE : 1;
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/** @brief SMX Enable */
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/** SMX Enable */
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uint32_t SMXE : 1;
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uint32_t SMXE : 1;
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/** @brief Reserved */
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/** Reserved */
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uint32_t Reserved0 : 1;
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uint32_t Reserved0 : 1;
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/** @brief FSGSBASE Enable */
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/** FSGSBASE Enable */
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uint32_t FSGSBASE : 1;
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uint32_t FSGSBASE : 1;
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/** @brief PCID Enable */
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/** PCID Enable */
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uint32_t PCIDE : 1;
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uint32_t PCIDE : 1;
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/** @brief XSAVE and Processor Extended States Enable */
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/** XSAVE and Processor Extended States Enable */
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uint32_t OSXSAVE : 1;
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uint32_t OSXSAVE : 1;
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/** @brief Reserved */
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/** Reserved */
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uint32_t Reserved1 : 1;
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uint32_t Reserved1 : 1;
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/** @brief SMEP Enable */
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/** SMEP Enable */
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uint32_t SMEP : 1;
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uint32_t SMEP : 1;
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/** @brief SMAP Enable */
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/** SMAP Enable */
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uint32_t SMAP : 1;
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uint32_t SMAP : 1;
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/** @brief Protection-Key Enable */
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/** Protection-Key Enable */
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uint32_t PKE : 1;
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uint32_t PKE : 1;
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/** @brief Control-flow Enforcement Technology*/
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/** Control-flow Enforcement Technology*/
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uint32_t CET : 1;
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uint32_t CET : 1;
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/* @brief Enable Protection Keys for Supervisor Mode Pages */
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/* Enable Protection Keys for Supervisor Mode Pages */
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uint32_t PKS : 1;
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uint32_t PKS : 1;
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};
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};
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uint32_t raw;
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uint32_t raw;
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} CR4;
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} CR4;
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#if defined(a32)
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#if defined(a32)
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nsa static inline CR0 readcr0()
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nsa static inline CR0 readcr0()
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{
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{
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uint32_t Result = 0;
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uint32_t Result = 0;
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asmv("mov %%cr0, %[Result]"
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asmv("mov %%cr0, %[Result]"
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: [Result] "=q"(Result));
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: [Result] "=q"(Result));
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return (CR0){.raw = Result};
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return (CR0){.raw = Result};
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}
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}
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nsa static inline CR2 readcr2()
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nsa static inline CR2 readcr2()
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{
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{
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uint32_t Result = 0;
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uint32_t Result = 0;
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asmv("mov %%cr2, %[Result]"
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asmv("mov %%cr2, %[Result]"
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: [Result] "=q"(Result));
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: [Result] "=q"(Result));
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return (CR2){.raw = Result};
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return (CR2){.raw = Result};
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}
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}
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nsa static inline CR3 readcr3()
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nsa static inline CR3 readcr3()
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{
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{
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uint32_t Result = 0;
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uint32_t Result = 0;
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asmv("mov %%cr3, %[Result]"
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asmv("mov %%cr3, %[Result]"
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: [Result] "=q"(Result));
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: [Result] "=q"(Result));
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return (CR3){.raw = Result};
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return (CR3){.raw = Result};
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}
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}
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nsa static inline CR4 readcr4()
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nsa static inline CR4 readcr4()
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{
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{
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uint32_t Result = 0;
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uint32_t Result = 0;
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asmv("mov %%cr4, %[Result]"
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asmv("mov %%cr4, %[Result]"
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: [Result] "=q"(Result));
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: [Result] "=q"(Result));
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return (CR4){.raw = Result};
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return (CR4){.raw = Result};
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}
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}
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nsa static inline CR8 readcr8()
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nsa static inline CR8 readcr8()
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{
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{
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uint32_t Result = 0;
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uint32_t Result = 0;
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asmv("mov %%cr8, %[Result]"
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asmv("mov %%cr8, %[Result]"
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: [Result] "=q"(Result));
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: [Result] "=q"(Result));
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return (CR8){.raw = Result};
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return (CR8){.raw = Result};
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}
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}
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nsa static inline void writecr0(CR0 ControlRegister)
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nsa static inline void writecr0(CR0 ControlRegister)
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{
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{
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asmv("mov %[ControlRegister], %%cr0"
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asmv("mov %[ControlRegister], %%cr0"
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:
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:
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: [ControlRegister] "q"(ControlRegister.raw)
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: [ControlRegister] "q"(ControlRegister.raw)
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: "memory");
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: "memory");
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}
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}
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nsa static inline void writecr2(CR2 ControlRegister)
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nsa static inline void writecr2(CR2 ControlRegister)
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{
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{
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asmv("mov %[ControlRegister], %%cr2"
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asmv("mov %[ControlRegister], %%cr2"
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:
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:
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: [ControlRegister] "q"(ControlRegister.raw)
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: [ControlRegister] "q"(ControlRegister.raw)
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: "memory");
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: "memory");
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}
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}
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nsa static inline void writecr3(CR3 ControlRegister)
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nsa static inline void writecr3(CR3 ControlRegister)
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{
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{
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asmv("mov %[ControlRegister], %%cr3"
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asmv("mov %[ControlRegister], %%cr3"
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:
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:
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: [ControlRegister] "q"(ControlRegister.raw)
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: [ControlRegister] "q"(ControlRegister.raw)
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: "memory");
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: "memory");
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}
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}
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nsa static inline void writecr4(CR4 ControlRegister)
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nsa static inline void writecr4(CR4 ControlRegister)
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{
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{
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asmv("mov %[ControlRegister], %%cr4"
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asmv("mov %[ControlRegister], %%cr4"
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:
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:
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: [ControlRegister] "q"(ControlRegister.raw)
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: [ControlRegister] "q"(ControlRegister.raw)
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: "memory");
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: "memory");
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}
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}
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nsa static inline void writecr8(CR8 ControlRegister)
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nsa static inline void writecr8(CR8 ControlRegister)
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{
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{
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asmv("mov %[ControlRegister], %%cr8"
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asmv("mov %[ControlRegister], %%cr8"
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:
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:
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: [ControlRegister] "q"(ControlRegister.raw)
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: [ControlRegister] "q"(ControlRegister.raw)
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: "memory");
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: "memory");
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}
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}
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#endif
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#endif
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}
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}
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}
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}
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#endif // !__FENNIX_KERNEL_CPU_x32_CR_H__
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#endif // !__FENNIX_KERNEL_CPU_x32_CR_H__
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@ -22,275 +22,275 @@
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namespace CPU
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namespace CPU
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{
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{
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namespace x64
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namespace x64
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{
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{
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typedef union CR0
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typedef union CR0
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{
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{
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struct
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struct
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{
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{
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/** @brief Protection Enable */
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/** Protection Enable */
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uint64_t PE : 1;
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uint64_t PE : 1;
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/** @brief Monitor Coprocessor */
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/** Monitor Coprocessor */
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uint64_t MP : 1;
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uint64_t MP : 1;
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/** @brief Emulation */
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/** Emulation */
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uint64_t EM : 1;
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uint64_t EM : 1;
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/** @brief Task Switched */
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/** Task Switched */
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uint64_t TS : 1;
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uint64_t TS : 1;
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/** @brief Extension Type */
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/** Extension Type */
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uint64_t ET : 1;
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uint64_t ET : 1;
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/** @brief Numeric Error */
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/** Numeric Error */
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uint64_t NE : 1;
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uint64_t NE : 1;
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/** @brief Reserved */
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/** Reserved */
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uint64_t Reserved0 : 10;
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uint64_t Reserved0 : 10;
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/** @brief Write Protect */
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/** Write Protect */
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uint64_t WP : 1;
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uint64_t WP : 1;
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/** @brief Reserved */
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/** Reserved */
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uint64_t Reserved1 : 1;
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uint64_t Reserved1 : 1;
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/** @brief Alignment Mask */
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/** Alignment Mask */
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uint64_t AM : 1;
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uint64_t AM : 1;
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/** @brief Reserved */
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/** Reserved */
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uint64_t Reserved2 : 10;
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uint64_t Reserved2 : 10;
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/** @brief Not Write-through */
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/** Not Write-through */
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uint64_t NW : 1;
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uint64_t NW : 1;
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/** @brief Cache Disable */
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/** Cache Disable */
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uint64_t CD : 1;
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uint64_t CD : 1;
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/** @brief Paging */
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/** Paging */
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uint64_t PG : 1;
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uint64_t PG : 1;
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};
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};
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uint64_t raw;
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uint64_t raw;
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} CR0;
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} CR0;
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typedef union CR2
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typedef union CR2
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{
|
{
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struct
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struct
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{
|
{
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/** @brief Page Fault Linear Address */
|
/** Page Fault Linear Address */
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uint64_t PFLA;
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uint64_t PFLA;
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};
|
};
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uint64_t raw;
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uint64_t raw;
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} CR2;
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} CR2;
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typedef union CR3
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typedef union CR3
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{
|
{
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struct
|
struct
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{
|
{
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/** @brief Not used if bit 17 of CR4 is 1 */
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/** Not used if bit 17 of CR4 is 1 */
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uint64_t PWT : 1;
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uint64_t PWT : 1;
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/** @brief Not used if bit 17 of CR4 is 1 */
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/** Not used if bit 17 of CR4 is 1 */
|
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uint64_t PCD : 1;
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uint64_t PCD : 1;
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/** @brief Base of PML4T/PML5T */
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/** Base of PML4T/PML5T */
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uint64_t PDBR;
|
uint64_t PDBR;
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};
|
};
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uint64_t raw;
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uint64_t raw;
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} CR3;
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} CR3;
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|
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typedef union CR4
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typedef union CR4
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{
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{
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struct
|
struct
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{
|
{
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/** @brief Virtual-8086 Mode Extensions */
|
/** Virtual-8086 Mode Extensions */
|
||||||
uint64_t VME : 1;
|
uint64_t VME : 1;
|
||||||
/** @brief Protected-Mode Virtual Interrupts */
|
/** Protected-Mode Virtual Interrupts */
|
||||||
uint64_t PVI : 1;
|
uint64_t PVI : 1;
|
||||||
/** @brief Time Stamp Disable */
|
/** Time Stamp Disable */
|
||||||
uint64_t TSD : 1;
|
uint64_t TSD : 1;
|
||||||
/** @brief Debugging Extensions */
|
/** Debugging Extensions */
|
||||||
uint64_t DE : 1;
|
uint64_t DE : 1;
|
||||||
/** @brief Page Size Extensions */
|
/** Page Size Extensions */
|
||||||
uint64_t PSE : 1;
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uint64_t PSE : 1;
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/** @brief Physical Address Extension */
|
/** Physical Address Extension */
|
||||||
uint64_t PAE : 1;
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uint64_t PAE : 1;
|
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/** @brief Machine Check Enable */
|
/** Machine Check Enable */
|
||||||
uint64_t MCE : 1;
|
uint64_t MCE : 1;
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/** @brief Page Global Enable */
|
/** Page Global Enable */
|
||||||
uint64_t PGE : 1;
|
uint64_t PGE : 1;
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/** @brief Performance Monitoring Counter */
|
/** Performance Monitoring Counter */
|
||||||
uint64_t PCE : 1;
|
uint64_t PCE : 1;
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/** @brief FXSAVE/FXRSTOR Support */
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/** FXSAVE/FXRSTOR Support */
|
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uint64_t OSFXSR : 1;
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uint64_t OSFXSR : 1;
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/** @brief Unmasked Exception Support */
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/** Unmasked Exception Support */
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uint64_t OSXMMEXCPT : 1;
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uint64_t OSXMMEXCPT : 1;
|
||||||
/** @brief User-Mode Instruction Prevention */
|
/** User-Mode Instruction Prevention */
|
||||||
uint64_t UMIP : 1;
|
uint64_t UMIP : 1;
|
||||||
/** @brief Linear Address 57bit */
|
/** Linear Address 57bit */
|
||||||
uint64_t LA57 : 1;
|
uint64_t LA57 : 1;
|
||||||
/** @brief VMX Enable */
|
/** VMX Enable */
|
||||||
uint64_t VMXE : 1;
|
uint64_t VMXE : 1;
|
||||||
/** @brief SMX Enable */
|
/** SMX Enable */
|
||||||
uint64_t SMXE : 1;
|
uint64_t SMXE : 1;
|
||||||
/** @brief Reserved */
|
/** Reserved */
|
||||||
uint64_t Reserved0 : 1;
|
uint64_t Reserved0 : 1;
|
||||||
/** @brief FSGSBASE Enable */
|
/** FSGSBASE Enable */
|
||||||
uint64_t FSGSBASE : 1;
|
uint64_t FSGSBASE : 1;
|
||||||
/** @brief PCID Enable */
|
/** PCID Enable */
|
||||||
uint64_t PCIDE : 1;
|
uint64_t PCIDE : 1;
|
||||||
/** @brief XSAVE and Processor Extended States Enable */
|
/** XSAVE and Processor Extended States Enable */
|
||||||
uint64_t OSXSAVE : 1;
|
uint64_t OSXSAVE : 1;
|
||||||
/** @brief Reserved */
|
/** Reserved */
|
||||||
uint64_t Reserved1 : 1;
|
uint64_t Reserved1 : 1;
|
||||||
/** @brief SMEP Enable */
|
/** SMEP Enable */
|
||||||
uint64_t SMEP : 1;
|
uint64_t SMEP : 1;
|
||||||
/** @brief SMAP Enable */
|
/** SMAP Enable */
|
||||||
uint64_t SMAP : 1;
|
uint64_t SMAP : 1;
|
||||||
/** @brief Protection-Key Enable */
|
/** Protection-Key Enable */
|
||||||
uint64_t PKE : 1;
|
uint64_t PKE : 1;
|
||||||
/** @brief Control-flow Enforcement Technology*/
|
/** Control-flow Enforcement Technology*/
|
||||||
uint32_t CET : 1;
|
uint32_t CET : 1;
|
||||||
/* @brief Enable Protection Keys for Supervisor Mode Pages */
|
/* Enable Protection Keys for Supervisor Mode Pages */
|
||||||
uint32_t PKS : 1;
|
uint32_t PKS : 1;
|
||||||
/** @brief Reserved */
|
/** Reserved */
|
||||||
uint64_t Reserved2 : 7; // TODO: This could be wrong
|
uint64_t Reserved2 : 7; // TODO: This could be wrong
|
||||||
};
|
};
|
||||||
uint64_t raw;
|
uint64_t raw;
|
||||||
} CR4;
|
} CR4;
|
||||||
|
|
||||||
typedef union CR8
|
typedef union CR8
|
||||||
{
|
{
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
/** @brief Task Priority Register */
|
/** Task Priority Register */
|
||||||
uint64_t TPR : 4;
|
uint64_t TPR : 4;
|
||||||
/** @brief Reserved */
|
/** Reserved */
|
||||||
uint64_t Reserved : 60;
|
uint64_t Reserved : 60;
|
||||||
};
|
};
|
||||||
uint64_t raw;
|
uint64_t raw;
|
||||||
} CR8;
|
} CR8;
|
||||||
|
|
||||||
typedef union XCR0
|
typedef union XCR0
|
||||||
{
|
{
|
||||||
/*
|
/*
|
||||||
On https://wiki.osdev.org/CPU_Registers_x86#XCR0 says that the PKRU bit is 9?
|
On https://wiki.osdev.org/CPU_Registers_x86#XCR0 says that the PKRU bit is 9?
|
||||||
*/
|
*/
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
/** @brief X87 FPU/MMX/SSE Support (must be 1) */
|
/** X87 FPU/MMX/SSE Support (must be 1) */
|
||||||
uint64_t X87 : 1;
|
uint64_t X87 : 1;
|
||||||
/** @brief XSAVE support for MXCSR and XMM registers */
|
/** XSAVE support for MXCSR and XMM registers */
|
||||||
uint64_t SSE : 1;
|
uint64_t SSE : 1;
|
||||||
/** @brief AVX support for YMM registers */
|
/** AVX support for YMM registers */
|
||||||
uint64_t AVX : 1;
|
uint64_t AVX : 1;
|
||||||
/** @brief MPX support for BND registers */
|
/** MPX support for BND registers */
|
||||||
uint64_t BNDREG : 1;
|
uint64_t BNDREG : 1;
|
||||||
/** @brief MPX support for BNDCFGU and BNDSTATUS registers */
|
/** MPX support for BNDCFGU and BNDSTATUS registers */
|
||||||
uint64_t BNDCSR : 1;
|
uint64_t BNDCSR : 1;
|
||||||
/** @brief AVX-512 support for opmask registers */
|
/** AVX-512 support for opmask registers */
|
||||||
uint64_t OpMask : 1;
|
uint64_t OpMask : 1;
|
||||||
/** @brief AVX-512 enabled and XSAVE support for upper halves of lower ZMM registers */
|
/** AVX-512 enabled and XSAVE support for upper halves of lower ZMM registers */
|
||||||
uint64_t ZMM_HI256 : 1;
|
uint64_t ZMM_HI256 : 1;
|
||||||
/** @brief AVX-512 enabled and XSAVE support for upper ZMM registers */
|
/** AVX-512 enabled and XSAVE support for upper ZMM registers */
|
||||||
uint64_t HI16_ZMM : 1;
|
uint64_t HI16_ZMM : 1;
|
||||||
/** @brief XSAVE support for PKRU register */
|
/** XSAVE support for PKRU register */
|
||||||
uint64_t PKRU : 1;
|
uint64_t PKRU : 1;
|
||||||
/** @brief Reserved */
|
/** Reserved */
|
||||||
uint64_t Reserved0 : 53;
|
uint64_t Reserved0 : 53;
|
||||||
/** @brief AMD lightweight profiling */
|
/** AMD lightweight profiling */
|
||||||
uint64_t LWP : 1;
|
uint64_t LWP : 1;
|
||||||
/** @brief Reserved */
|
/** Reserved */
|
||||||
uint64_t Reserved1 : 1;
|
uint64_t Reserved1 : 1;
|
||||||
};
|
};
|
||||||
uint64_t raw;
|
uint64_t raw;
|
||||||
} XCR0;
|
} XCR0;
|
||||||
|
|
||||||
#if defined(a64)
|
#if defined(a64)
|
||||||
nsa static inline CR0 readcr0()
|
nsa static inline CR0 readcr0()
|
||||||
{
|
{
|
||||||
uint64_t Result = 0;
|
uint64_t Result = 0;
|
||||||
asmv("mov %%cr0, %[Result]"
|
asmv("mov %%cr0, %[Result]"
|
||||||
: [Result] "=q"(Result));
|
: [Result] "=q"(Result));
|
||||||
return (CR0){.raw = Result};
|
return (CR0){.raw = Result};
|
||||||
}
|
}
|
||||||
|
|
||||||
nsa static inline CR2 readcr2()
|
nsa static inline CR2 readcr2()
|
||||||
{
|
{
|
||||||
uint64_t Result = 0;
|
uint64_t Result = 0;
|
||||||
asmv("mov %%cr2, %[Result]"
|
asmv("mov %%cr2, %[Result]"
|
||||||
: [Result] "=q"(Result));
|
: [Result] "=q"(Result));
|
||||||
return (CR2){.raw = Result};
|
return (CR2){.raw = Result};
|
||||||
}
|
}
|
||||||
|
|
||||||
nsa static inline CR3 readcr3()
|
nsa static inline CR3 readcr3()
|
||||||
{
|
{
|
||||||
uint64_t Result = 0;
|
uint64_t Result = 0;
|
||||||
asmv("mov %%cr3, %[Result]"
|
asmv("mov %%cr3, %[Result]"
|
||||||
: [Result] "=q"(Result));
|
: [Result] "=q"(Result));
|
||||||
return (CR3){.raw = Result};
|
return (CR3){.raw = Result};
|
||||||
}
|
}
|
||||||
|
|
||||||
nsa static inline CR4 readcr4()
|
nsa static inline CR4 readcr4()
|
||||||
{
|
{
|
||||||
uint64_t Result = 0;
|
uint64_t Result = 0;
|
||||||
asmv("mov %%cr4, %[Result]"
|
asmv("mov %%cr4, %[Result]"
|
||||||
: [Result] "=q"(Result));
|
: [Result] "=q"(Result));
|
||||||
return (CR4){.raw = Result};
|
return (CR4){.raw = Result};
|
||||||
}
|
}
|
||||||
|
|
||||||
nsa static inline CR8 readcr8()
|
nsa static inline CR8 readcr8()
|
||||||
{
|
{
|
||||||
uint64_t Result = 0;
|
uint64_t Result = 0;
|
||||||
asmv("mov %%cr8, %[Result]"
|
asmv("mov %%cr8, %[Result]"
|
||||||
: [Result] "=q"(Result));
|
: [Result] "=q"(Result));
|
||||||
return (CR8){.raw = Result};
|
return (CR8){.raw = Result};
|
||||||
}
|
}
|
||||||
|
|
||||||
nsa static inline XCR0 readxcr0()
|
nsa static inline XCR0 readxcr0()
|
||||||
{
|
{
|
||||||
uint64_t Result = 0;
|
uint64_t Result = 0;
|
||||||
asmv("xgetbv"
|
asmv("xgetbv"
|
||||||
: "=a"(Result)
|
: "=a"(Result)
|
||||||
: "c"(0)
|
: "c"(0)
|
||||||
: "edx");
|
: "edx");
|
||||||
return (XCR0){.raw = Result};
|
return (XCR0){.raw = Result};
|
||||||
}
|
}
|
||||||
|
|
||||||
nsa static inline void writecr0(CR0 ControlRegister)
|
nsa static inline void writecr0(CR0 ControlRegister)
|
||||||
{
|
{
|
||||||
asmv("mov %[ControlRegister], %%cr0"
|
asmv("mov %[ControlRegister], %%cr0"
|
||||||
:
|
:
|
||||||
: [ControlRegister] "q"(ControlRegister.raw)
|
: [ControlRegister] "q"(ControlRegister.raw)
|
||||||
: "memory");
|
: "memory");
|
||||||
}
|
}
|
||||||
|
|
||||||
nsa static inline void writecr2(CR2 ControlRegister)
|
nsa static inline void writecr2(CR2 ControlRegister)
|
||||||
{
|
{
|
||||||
asmv("mov %[ControlRegister], %%cr2"
|
asmv("mov %[ControlRegister], %%cr2"
|
||||||
:
|
:
|
||||||
: [ControlRegister] "q"(ControlRegister.raw)
|
: [ControlRegister] "q"(ControlRegister.raw)
|
||||||
: "memory");
|
: "memory");
|
||||||
}
|
}
|
||||||
|
|
||||||
nsa static inline void writecr3(CR3 ControlRegister)
|
nsa static inline void writecr3(CR3 ControlRegister)
|
||||||
{
|
{
|
||||||
asmv("mov %[ControlRegister], %%cr3"
|
asmv("mov %[ControlRegister], %%cr3"
|
||||||
:
|
:
|
||||||
: [ControlRegister] "q"(ControlRegister.raw)
|
: [ControlRegister] "q"(ControlRegister.raw)
|
||||||
: "memory");
|
: "memory");
|
||||||
}
|
}
|
||||||
|
|
||||||
nsa static inline void writecr4(CR4 ControlRegister)
|
nsa static inline void writecr4(CR4 ControlRegister)
|
||||||
{
|
{
|
||||||
asmv("mov %[ControlRegister], %%cr4"
|
asmv("mov %[ControlRegister], %%cr4"
|
||||||
:
|
:
|
||||||
: [ControlRegister] "q"(ControlRegister.raw)
|
: [ControlRegister] "q"(ControlRegister.raw)
|
||||||
: "memory");
|
: "memory");
|
||||||
}
|
}
|
||||||
|
|
||||||
nsa static inline void writecr8(CR8 ControlRegister)
|
nsa static inline void writecr8(CR8 ControlRegister)
|
||||||
{
|
{
|
||||||
asmv("mov %[ControlRegister], %%cr8"
|
asmv("mov %[ControlRegister], %%cr8"
|
||||||
:
|
:
|
||||||
: [ControlRegister] "q"(ControlRegister.raw)
|
: [ControlRegister] "q"(ControlRegister.raw)
|
||||||
: "memory");
|
: "memory");
|
||||||
}
|
}
|
||||||
|
|
||||||
nsa static inline void writexcr0(XCR0 ControlRegister)
|
nsa static inline void writexcr0(XCR0 ControlRegister)
|
||||||
{
|
{
|
||||||
asmv("xsetbv"
|
asmv("xsetbv"
|
||||||
:
|
:
|
||||||
: "a"(ControlRegister.raw), "c"(0)
|
: "a"(ControlRegister.raw), "c"(0)
|
||||||
: "edx");
|
: "edx");
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif // !__FENNIX_KERNEL_CPU_x64_CR_H__
|
#endif // !__FENNIX_KERNEL_CPU_x64_CR_H__
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user