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Refactor code to use tab spaces

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This commit is contained in:
EnderIce2 2024-03-13 18:09:42 +02:00
parent d247dcd4a3
commit f009f181b0
Signed by untrusted user who does not match committer: enderice2
GPG Key ID: EACC3AD603BAB4DD
2 changed files with 436 additions and 436 deletions
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86
include/cpu/x86/x32/cr.hpp
View File

@ -28,33 +28,33 @@ namespace CPU
{ {
struct struct
{ {
/** @brief Protection Enable */ /** Protection Enable */
uint32_t PE : 1; uint32_t PE : 1;
/** @brief Monitor Coprocessor */ /** Monitor Coprocessor */
uint32_t MP : 1; uint32_t MP : 1;
/** @brief Emulation */ /** Emulation */
uint32_t EM : 1; uint32_t EM : 1;
/** @brief Task Switched */ /** Task Switched */
uint32_t TS : 1; uint32_t TS : 1;
/** @brief Extension Type */ /** Extension Type */
uint32_t ET : 1; uint32_t ET : 1;
/** @brief Numeric Error */ /** Numeric Error */
uint32_t NE : 1; uint32_t NE : 1;
/** @brief Reserved */ /** Reserved */
uint32_t Reserved0 : 10; uint32_t Reserved0 : 10;
/** @brief Write Protect */ /** Write Protect */
uint32_t WP : 1; uint32_t WP : 1;
/** @brief Reserved */ /** Reserved */
uint32_t Reserved1 : 1; uint32_t Reserved1 : 1;
/** @brief Alignment Mask */ /** Alignment Mask */
uint32_t AM : 1; uint32_t AM : 1;
/** @brief Reserved */ /** Reserved */
uint32_t Reserved2 : 10; uint32_t Reserved2 : 10;
/** @brief Not Write-through */ /** Not Write-through */
uint32_t NW : 1; uint32_t NW : 1;
/** @brief Cache Disable */ /** Cache Disable */
uint32_t CD : 1; uint32_t CD : 1;
/** @brief Paging */ /** Paging */
uint32_t PG : 1; uint32_t PG : 1;
}; };
uint32_t raw; uint32_t raw;
@ -64,7 +64,7 @@ namespace CPU
{ {
struct struct
{ {
/** @brief Page Fault Linear Address */ /** Page Fault Linear Address */
uint32_t PFLA; uint32_t PFLA;
}; };
uint32_t raw; uint32_t raw;
@ -74,11 +74,11 @@ namespace CPU
{ {
struct struct
{ {
/** @brief Not used if bit 17 of CR4 is 1 */ /** Not used if bit 17 of CR4 is 1 */
uint32_t PWT : 1; uint32_t PWT : 1;
/** @brief Not used if bit 17 of CR4 is 1 */ /** Not used if bit 17 of CR4 is 1 */
uint32_t PCD : 1; uint32_t PCD : 1;
/** @brief Base of PML4T/PML5T */ /** Base of PML4T/PML5T */
uint32_t PDBR; uint32_t PDBR;
}; };
uint32_t raw; uint32_t raw;
@ -88,55 +88,55 @@ namespace CPU
{ {
struct struct
{ {
/** @brief Virtual-8086 Mode Extensions */ /** Virtual-8086 Mode Extensions */
uint32_t VME : 1; uint32_t VME : 1;
/** @brief Protected-Mode Virtual Interrupts */ /** Protected-Mode Virtual Interrupts */
uint32_t PVI : 1; uint32_t PVI : 1;
/** @brief Time Stamp Disable */ /** Time Stamp Disable */
uint32_t TSD : 1; uint32_t TSD : 1;
/** @brief Debugging Extensions */ /** Debugging Extensions */
uint32_t DE : 1; uint32_t DE : 1;
/** @brief Page Size Extensions */ /** Page Size Extensions */
uint32_t PSE : 1; uint32_t PSE : 1;
/** @brief Physical Address Extension */ /** Physical Address Extension */
uint32_t PAE : 1; uint32_t PAE : 1;
/** @brief Machine Check Enable */ /** Machine Check Enable */
uint32_t MCE : 1; uint32_t MCE : 1;
/** @brief Page Global Enable */ /** Page Global Enable */
uint32_t PGE : 1; uint32_t PGE : 1;
/** @brief Performance Monitoring Counter */ /** Performance Monitoring Counter */
uint32_t PCE : 1; uint32_t PCE : 1;
/** @brief Operating System Support */ /** Operating System Support */
uint32_t OSFXSR : 1; uint32_t OSFXSR : 1;
/** @brief Operating System Support */ /** Operating System Support */
uint32_t OSXMMEXCPT : 1; uint32_t OSXMMEXCPT : 1;
/** @brief User-Mode Instruction Prevention */ /** User-Mode Instruction Prevention */
uint32_t UMIP : 1; uint32_t UMIP : 1;
/** @brief Linear Address 57bit */ /** Linear Address 57bit */
uint32_t LA57 : 1; uint32_t LA57 : 1;
/** @brief VMX Enable */ /** VMX Enable */
uint32_t VMXE : 1; uint32_t VMXE : 1;
/** @brief SMX Enable */ /** SMX Enable */
uint32_t SMXE : 1; uint32_t SMXE : 1;
/** @brief Reserved */ /** Reserved */
uint32_t Reserved0 : 1; uint32_t Reserved0 : 1;
/** @brief FSGSBASE Enable */ /** FSGSBASE Enable */
uint32_t FSGSBASE : 1; uint32_t FSGSBASE : 1;
/** @brief PCID Enable */ /** PCID Enable */
uint32_t PCIDE : 1; uint32_t PCIDE : 1;
/** @brief XSAVE and Processor Extended States Enable */ /** XSAVE and Processor Extended States Enable */
uint32_t OSXSAVE : 1; uint32_t OSXSAVE : 1;
/** @brief Reserved */ /** Reserved */
uint32_t Reserved1 : 1; uint32_t Reserved1 : 1;
/** @brief SMEP Enable */ /** SMEP Enable */
uint32_t SMEP : 1; uint32_t SMEP : 1;
/** @brief SMAP Enable */ /** SMAP Enable */
uint32_t SMAP : 1; uint32_t SMAP : 1;
/** @brief Protection-Key Enable */ /** Protection-Key Enable */
uint32_t PKE : 1; uint32_t PKE : 1;
/** @brief Control-flow Enforcement Technology*/ /** Control-flow Enforcement Technology*/
uint32_t CET : 1; uint32_t CET : 1;
/* @brief Enable Protection Keys for Supervisor Mode Pages */ /* Enable Protection Keys for Supervisor Mode Pages */
uint32_t PKS : 1; uint32_t PKS : 1;
}; };
uint32_t raw; uint32_t raw;

116
include/cpu/x86/x64/cr.hpp
View File

@ -28,33 +28,33 @@ namespace CPU
{ {
struct struct
{ {
/** @brief Protection Enable */ /** Protection Enable */
uint64_t PE : 1; uint64_t PE : 1;
/** @brief Monitor Coprocessor */ /** Monitor Coprocessor */
uint64_t MP : 1; uint64_t MP : 1;
/** @brief Emulation */ /** Emulation */
uint64_t EM : 1; uint64_t EM : 1;
/** @brief Task Switched */ /** Task Switched */
uint64_t TS : 1; uint64_t TS : 1;
/** @brief Extension Type */ /** Extension Type */
uint64_t ET : 1; uint64_t ET : 1;
/** @brief Numeric Error */ /** Numeric Error */
uint64_t NE : 1; uint64_t NE : 1;
/** @brief Reserved */ /** Reserved */
uint64_t Reserved0 : 10; uint64_t Reserved0 : 10;
/** @brief Write Protect */ /** Write Protect */
uint64_t WP : 1; uint64_t WP : 1;
/** @brief Reserved */ /** Reserved */
uint64_t Reserved1 : 1; uint64_t Reserved1 : 1;
/** @brief Alignment Mask */ /** Alignment Mask */
uint64_t AM : 1; uint64_t AM : 1;
/** @brief Reserved */ /** Reserved */
uint64_t Reserved2 : 10; uint64_t Reserved2 : 10;
/** @brief Not Write-through */ /** Not Write-through */
uint64_t NW : 1; uint64_t NW : 1;
/** @brief Cache Disable */ /** Cache Disable */
uint64_t CD : 1; uint64_t CD : 1;
/** @brief Paging */ /** Paging */
uint64_t PG : 1; uint64_t PG : 1;
}; };
uint64_t raw; uint64_t raw;
@ -64,7 +64,7 @@ namespace CPU
{ {
struct struct
{ {
/** @brief Page Fault Linear Address */ /** Page Fault Linear Address */
uint64_t PFLA; uint64_t PFLA;
}; };
uint64_t raw; uint64_t raw;
@ -74,11 +74,11 @@ namespace CPU
{ {
struct struct
{ {
/** @brief Not used if bit 17 of CR4 is 1 */ /** Not used if bit 17 of CR4 is 1 */
uint64_t PWT : 1; uint64_t PWT : 1;
/** @brief Not used if bit 17 of CR4 is 1 */ /** Not used if bit 17 of CR4 is 1 */
uint64_t PCD : 1; uint64_t PCD : 1;
/** @brief Base of PML4T/PML5T */ /** Base of PML4T/PML5T */
uint64_t PDBR; uint64_t PDBR;
}; };
uint64_t raw; uint64_t raw;
@ -88,57 +88,57 @@ namespace CPU
{ {
struct struct
{ {
/** @brief Virtual-8086 Mode Extensions */ /** Virtual-8086 Mode Extensions */
uint64_t VME : 1; uint64_t VME : 1;
/** @brief Protected-Mode Virtual Interrupts */ /** Protected-Mode Virtual Interrupts */
uint64_t PVI : 1; uint64_t PVI : 1;
/** @brief Time Stamp Disable */ /** Time Stamp Disable */
uint64_t TSD : 1; uint64_t TSD : 1;
/** @brief Debugging Extensions */ /** Debugging Extensions */
uint64_t DE : 1; uint64_t DE : 1;
/** @brief Page Size Extensions */ /** Page Size Extensions */
uint64_t PSE : 1; uint64_t PSE : 1;
/** @brief Physical Address Extension */ /** Physical Address Extension */
uint64_t PAE : 1; uint64_t PAE : 1;
/** @brief Machine Check Enable */ /** Machine Check Enable */
uint64_t MCE : 1; uint64_t MCE : 1;
/** @brief Page Global Enable */ /** Page Global Enable */
uint64_t PGE : 1; uint64_t PGE : 1;
/** @brief Performance Monitoring Counter */ /** Performance Monitoring Counter */
uint64_t PCE : 1; uint64_t PCE : 1;
/** @brief FXSAVE/FXRSTOR Support */ /** FXSAVE/FXRSTOR Support */
uint64_t OSFXSR : 1; uint64_t OSFXSR : 1;
/** @brief Unmasked Exception Support */ /** Unmasked Exception Support */
uint64_t OSXMMEXCPT : 1; uint64_t OSXMMEXCPT : 1;
/** @brief User-Mode Instruction Prevention */ /** User-Mode Instruction Prevention */
uint64_t UMIP : 1; uint64_t UMIP : 1;
/** @brief Linear Address 57bit */ /** Linear Address 57bit */
uint64_t LA57 : 1; uint64_t LA57 : 1;
/** @brief VMX Enable */ /** VMX Enable */
uint64_t VMXE : 1; uint64_t VMXE : 1;
/** @brief SMX Enable */ /** SMX Enable */
uint64_t SMXE : 1; uint64_t SMXE : 1;
/** @brief Reserved */ /** Reserved */
uint64_t Reserved0 : 1; uint64_t Reserved0 : 1;
/** @brief FSGSBASE Enable */ /** FSGSBASE Enable */
uint64_t FSGSBASE : 1; uint64_t FSGSBASE : 1;
/** @brief PCID Enable */ /** PCID Enable */
uint64_t PCIDE : 1; uint64_t PCIDE : 1;
/** @brief XSAVE and Processor Extended States Enable */ /** XSAVE and Processor Extended States Enable */
uint64_t OSXSAVE : 1; uint64_t OSXSAVE : 1;
/** @brief Reserved */ /** Reserved */
uint64_t Reserved1 : 1; uint64_t Reserved1 : 1;
/** @brief SMEP Enable */ /** SMEP Enable */
uint64_t SMEP : 1; uint64_t SMEP : 1;
/** @brief SMAP Enable */ /** SMAP Enable */
uint64_t SMAP : 1; uint64_t SMAP : 1;
/** @brief Protection-Key Enable */ /** Protection-Key Enable */
uint64_t PKE : 1; uint64_t PKE : 1;
/** @brief Control-flow Enforcement Technology*/ /** Control-flow Enforcement Technology*/
uint32_t CET : 1; uint32_t CET : 1;
/* @brief Enable Protection Keys for Supervisor Mode Pages */ /* Enable Protection Keys for Supervisor Mode Pages */
uint32_t PKS : 1; uint32_t PKS : 1;
/** @brief Reserved */ /** Reserved */
uint64_t Reserved2 : 7; // TODO: This could be wrong uint64_t Reserved2 : 7; // TODO: This could be wrong
}; };
uint64_t raw; uint64_t raw;
@ -148,9 +148,9 @@ namespace CPU
{ {
struct struct
{ {
/** @brief Task Priority Register */ /** Task Priority Register */
uint64_t TPR : 4; uint64_t TPR : 4;
/** @brief Reserved */ /** Reserved */
uint64_t Reserved : 60; uint64_t Reserved : 60;
}; };
uint64_t raw; uint64_t raw;
@ -163,29 +163,29 @@ namespace CPU
*/ */
struct struct
{ {
/** @brief X87 FPU/MMX/SSE Support (must be 1) */ /** X87 FPU/MMX/SSE Support (must be 1) */
uint64_t X87 : 1; uint64_t X87 : 1;
/** @brief XSAVE support for MXCSR and XMM registers */ /** XSAVE support for MXCSR and XMM registers */
uint64_t SSE : 1; uint64_t SSE : 1;
/** @brief AVX support for YMM registers */ /** AVX support for YMM registers */
uint64_t AVX : 1; uint64_t AVX : 1;
/** @brief MPX support for BND registers */ /** MPX support for BND registers */
uint64_t BNDREG : 1; uint64_t BNDREG : 1;
/** @brief MPX support for BNDCFGU and BNDSTATUS registers */ /** MPX support for BNDCFGU and BNDSTATUS registers */
uint64_t BNDCSR : 1; uint64_t BNDCSR : 1;
/** @brief AVX-512 support for opmask registers */ /** AVX-512 support for opmask registers */
uint64_t OpMask : 1; uint64_t OpMask : 1;
/** @brief AVX-512 enabled and XSAVE support for upper halves of lower ZMM registers */ /** AVX-512 enabled and XSAVE support for upper halves of lower ZMM registers */
uint64_t ZMM_HI256 : 1; uint64_t ZMM_HI256 : 1;
/** @brief AVX-512 enabled and XSAVE support for upper ZMM registers */ /** AVX-512 enabled and XSAVE support for upper ZMM registers */
uint64_t HI16_ZMM : 1; uint64_t HI16_ZMM : 1;
/** @brief XSAVE support for PKRU register */ /** XSAVE support for PKRU register */
uint64_t PKRU : 1; uint64_t PKRU : 1;
/** @brief Reserved */ /** Reserved */
uint64_t Reserved0 : 53; uint64_t Reserved0 : 53;
/** @brief AMD lightweight profiling */ /** AMD lightweight profiling */
uint64_t LWP : 1; uint64_t LWP : 1;
/** @brief Reserved */ /** Reserved */
uint64_t Reserved1 : 1; uint64_t Reserved1 : 1;
}; };
uint64_t raw; uint64_t raw;