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Added CPU vendors and signatures and read/write CR*
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Alex
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312
include/cpu.hpp
312
include/cpu.hpp
@ -3,6 +3,91 @@
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#include <types.h>
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#define x86_CPUID_VENDOR_OLDAMD "AMDisbetter!" /* Early engineering samples of AMD K5 processor */
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#define x86_CPUID_VENDOR_AMD "AuthenticAMD"
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#define x86_CPUID_VENDOR_INTEL "GenuineIntel"
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#define x86_CPUID_VENDOR_VIA "CentaurHauls"
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#define x86_CPUID_VENDOR_OLDTRANSMETA "TransmetaCPU"
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#define x86_CPUID_VENDOR_TRANSMETA "GenuineTMx86"
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#define x86_CPUID_VENDOR_CYRIX "CyrixInstead"
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#define x86_CPUID_VENDOR_CENTAUR "CentaurHauls"
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#define x86_CPUID_VENDOR_NEXGEN "NexGenDriven"
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#define x86_CPUID_VENDOR_UMC "UMC UMC UMC "
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#define x86_CPUID_VENDOR_SIS "SiS SiS SiS "
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#define x86_CPUID_VENDOR_NSC "Geode by NSC"
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#define x86_CPUID_VENDOR_RISE "RiseRiseRise"
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#define x86_CPUID_VENDOR_VORTEX "Vortex86 SoC"
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#define x86_CPUID_VENDOR_VIA2 "VIA VIA VIA "
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#define x86_CPUID_VENDOR_HYGON "HygonGenuine"
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#define x86_CPUID_VENDOR_E2K "E2K MACHINE"
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#define x86_CPUID_VENDOR_MISTER "MiSTer AO486"
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/* Vendor-strings from Virtual Machines. */
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#define x86_CPUID_VENDOR_VMWARE "VMwareVMware"
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#define x86_CPUID_VENDOR_XENHVM "XenVMMXenVMM"
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#define x86_CPUID_VENDOR_MICROSOFT_HV "Microsoft Hv"
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#define x86_CPUID_VENDOR_MICROSOFT_XTA "MicrosoftXTA"
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#define x86_CPUID_VENDOR_PARALLELS " lrpepyh vr"
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#define x86_CPUID_VENDOR_KVM "KVMKVMKVM"
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#define x86_CPUID_VENDOR_VIRTUALBOX "VBoxVBoxVBox"
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#define x86_CPUID_VENDOR_TCG "TCGTCGTCGTCG"
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#define x86_CPUID_VENDOR_BHYVE "bhyve bhyve "
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#define x86_CPUID_VENDOR_ACRN "ACRNACRNACRN"
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#define x86_CPUID_VENDOR_QNX "QNXQVMBSQG"
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#define x86_CPUID_VENDOR_APPLE "VirtualApple"
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#define x86_CPUID_SIGNATURE_INTEL_b 0x756e6547
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#define x86_CPUID_SIGNATURE_INTEL_c 0x6c65746e
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#define x86_CPUID_SIGNATURE_INTEL_d 0x49656e69
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#define x86_CPUID_SIGNATURE_AMD_b 0x68747541
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#define x86_CPUID_SIGNATURE_AMD_c 0x444d4163
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#define x86_CPUID_SIGNATURE_AMD_d 0x69746e65
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#define x86_CPUID_SIGNATURE_CENTAUR_b 0x746e6543
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#define x86_CPUID_SIGNATURE_CENTAUR_c 0x736c7561
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#define x86_CPUID_SIGNATURE_CENTAUR_d 0x48727561
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#define x86_CPUID_SIGNATURE_CYRIX_b 0x69727943
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#define x86_CPUID_SIGNATURE_CYRIX_c 0x64616574
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#define x86_CPUID_SIGNATURE_CYRIX_d 0x736e4978
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#define x86_CPUID_SIGNATURE_TM1_b 0x6e617254
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#define x86_CPUID_SIGNATURE_TM1_c 0x55504361
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#define x86_CPUID_SIGNATURE_TM1_d 0x74656d73
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#define x86_CPUID_SIGNATURE_TM2_b 0x756e6547
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#define x86_CPUID_SIGNATURE_TM2_c 0x3638784d
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#define x86_CPUID_SIGNATURE_TM2_d 0x54656e69
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#define x86_CPUID_SIGNATURE_NSC_b 0x646f6547
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#define x86_CPUID_SIGNATURE_NSC_c 0x43534e20
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#define x86_CPUID_SIGNATURE_NSC_d 0x79622065
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#define x86_CPUID_SIGNATURE_NEXGEN_b 0x4778654e
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#define x86_CPUID_SIGNATURE_NEXGEN_c 0x6e657669
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#define x86_CPUID_SIGNATURE_NEXGEN_d 0x72446e65
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#define x86_CPUID_SIGNATURE_RISE_b 0x65736952
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#define x86_CPUID_SIGNATURE_RISE_c 0x65736952
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#define x86_CPUID_SIGNATURE_RISE_d 0x65736952
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#define x86_CPUID_SIGNATURE_SIS_b 0x20536953
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#define x86_CPUID_SIGNATURE_SIS_c 0x20536953
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#define x86_CPUID_SIGNATURE_SIS_d 0x20536953
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#define x86_CPUID_SIGNATURE_UMC_b 0x20434d55
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#define x86_CPUID_SIGNATURE_UMC_c 0x20434d55
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#define x86_CPUID_SIGNATURE_UMC_d 0x20434d55
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#define x86_CPUID_SIGNATURE_VIA_b 0x20414956
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#define x86_CPUID_SIGNATURE_VIA_c 0x20414956
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#define x86_CPUID_SIGNATURE_VIA_d 0x20414956
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#define x86_CPUID_SIGNATURE_VORTEX_b 0x74726f56
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#define x86_CPUID_SIGNATURE_VORTEX_c 0x436f5320
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#define x86_CPUID_SIGNATURE_VORTEX_d 0x36387865
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/**
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* @brief CPU related functions.
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*/
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@ -955,6 +1040,132 @@ namespace CPU
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uint64_t ss; // Stack Segment
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} TrapFrame;
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typedef union CR0
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{
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struct
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{
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/** @brief Protection Enable */
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uint64_t PE : 1;
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/** @brief Monitor Coprocessor */
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uint64_t MP : 1;
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/** @brief Emulation */
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uint64_t EM : 1;
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/** @brief Task Switched */
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uint64_t TS : 1;
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/** @brief Extension Type */
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uint64_t ET : 1;
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/** @brief Numeric Error */
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uint64_t NE : 1;
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/** @brief Reserved */
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uint64_t _reserved0 : 10;
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/** @brief Write Protect */
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uint64_t WP : 1;
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/** @brief Reserved */
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uint64_t _reserved1 : 1;
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/** @brief Alignment Mask */
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uint64_t AM : 1;
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/** @brief Reserved */
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uint64_t _reserved2 : 10;
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/** @brief Mot Write-through */
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uint64_t NW : 1;
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/** @brief Cache Disable */
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uint64_t CD : 1;
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/** @brief Paging */
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uint64_t PG : 1;
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};
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uint64_t raw;
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} CR0;
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typedef union CR2
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{
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struct
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{
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/** @brief Page Fault Linear Address */
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uint64_t PFLA;
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};
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uint64_t raw;
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} CR2;
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typedef union CR3
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{
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struct
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{
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/** @brief Not used if bit 17 of CR4 is 1 */
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uint64_t PWT : 1;
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/** @brief Not used if bit 17 of CR4 is 1 */
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uint64_t PCD : 1;
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/** @brief Base of PML4T/PML5T */
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uint64_t PDBR;
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};
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uint64_t raw;
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} CR3;
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typedef union CR4
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{
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struct
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{
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/** @brief Virtual-8086 Mode Extensions */
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uint64_t VME : 1;
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/** @brief Protected-Mode Virtual Interrupts */
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uint64_t PVI : 1;
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/** @brief Time Stamp Disable */
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uint64_t TSD : 1;
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/** @brief Debugging Extensions */
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uint64_t DE : 1;
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/** @brief Page Size Extensions */
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uint64_t PSE : 1;
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/** @brief Physical Address Extension */
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uint64_t PAE : 1;
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/** @brief Machine Check Enable */
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uint64_t MCE : 1;
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/** @brief Page Global Enable */
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uint64_t PGE : 1;
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/** @brief Performance Monitoring Counter */
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uint64_t PCE : 1;
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/** @brief Operating System Support */
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uint64_t OSFXSR : 1;
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/** @brief Operating System Support */
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uint64_t OSXMMEXCPT : 1;
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/** @brief User-Mode Instruction Prevention */
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uint64_t UMIP : 1;
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/** @brief Linear Address 57bit */
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uint64_t LA57 : 1;
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/** @brief VMX Enable */
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uint64_t VMXE : 1;
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/** @brief SMX Enable */
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uint64_t SMXE : 1;
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/** @brief Reserved */
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uint64_t _reserved0 : 1;
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/** @brief FSGSBASE Enable */
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uint64_t FSGSBASE : 1;
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/** @brief PCID Enable */
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uint64_t PCIDE : 1;
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/** @brief XSAVE and Processor Extended States Enable */
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uint64_t OSXSAVE : 1;
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/** @brief Reserved */
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uint64_t _reserved1 : 1;
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/** @brief SMEP Enable */
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uint64_t SMEP : 1;
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/** @brief SMAP Enable */
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uint64_t SMAP : 1;
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/** @brief Protection-Key Enable */
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uint64_t PKE : 1;
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/** @brief Reserved */
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uint64_t _reserved2 : 9;
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};
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uint64_t raw;
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} CR4;
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typedef union CR8
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{
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struct
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{
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/** @brief Task Priority Level */
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uint64_t TPL : 1;
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};
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uint64_t raw;
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} CR8;
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static inline void lgdt(void *gdt)
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{
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#if defined(__amd64__)
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@ -1023,6 +1234,107 @@ namespace CPU
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: "memory");
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#endif
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}
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static inline CR0 readcr0()
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{
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uint64_t Result;
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#if defined(__amd64__)
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asmv("mov %%cr0, %[Result]"
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: [Result] "=q"(Result));
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#endif
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return (CR0){.raw = Result};
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}
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static inline CR2 readcr2()
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{
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uint64_t Result;
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#if defined(__amd64__)
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asmv("mov %%cr2, %[Result]"
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: [Result] "=q"(Result));
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#endif
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return (CR2){.raw = Result};
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}
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static inline CR3 readcr3()
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{
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uint64_t Result;
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#if defined(__amd64__)
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asmv("mov %%cr3, %[Result]"
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: [Result] "=q"(Result));
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#endif
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return (CR3){.raw = Result};
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}
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static inline CR4 readcr4()
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{
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uint64_t Result;
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#if defined(__amd64__)
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asmv("mov %%cr4, %[Result]"
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: [Result] "=q"(Result));
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#endif
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return (CR4){.raw = Result};
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}
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static inline CR8 readcr8()
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{
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uint64_t Result;
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#if defined(__amd64__)
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asmv("mov %%cr8, %[Result]"
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: [Result] "=q"(Result));
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#endif
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return (CR8){.raw = Result};
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}
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static inline void writecr0(CR0 ControlRegister)
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{
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#if defined(__amd64__)
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asmv("mov %[ControlRegister], %%cr0"
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:
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: [ControlRegister] "q"(ControlRegister.raw)
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: "memory");
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#endif
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}
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static inline void writecr2(CR2 ControlRegister)
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{
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#if defined(__amd64__)
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asmv("mov %[ControlRegister], %%cr2"
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:
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: [ControlRegister] "q"(ControlRegister.raw)
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: "memory");
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#endif
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}
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static inline void writecr3(CR3 ControlRegister)
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{
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#if defined(__amd64__)
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asmv("mov %[ControlRegister], %%cr3"
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:
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: [ControlRegister] "q"(ControlRegister.raw)
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: "memory");
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#endif
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}
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static inline void writecr4(CR4 ControlRegister)
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{
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#if defined(__amd64__)
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asmv("mov %[ControlRegister], %%cr4"
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:
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: [ControlRegister] "q"(ControlRegister.raw)
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: "memory");
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#endif
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}
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static inline void writecr8(CR8 ControlRegister)
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{
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#if defined(__amd64__)
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asmv("mov %[ControlRegister], %%cr8"
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:
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: [ControlRegister] "q"(ControlRegister.raw)
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: "memory");
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#endif
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}
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}
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}
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