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ISR 0x1 should have RING3

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EnderIce2 2023-10-20 01:42:24 +03:00
parent da7e9d781f
commit cfee4807c4
Signed by untrusted user who does not match committer: enderice2
GPG Key ID: EACC3AD603BAB4DD
1 changed files with 1 additions and 1 deletions
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arch/amd64/cpu/idt.cpp
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@ -540,7 +540,7 @@ namespace InterruptDescriptorTable
/* ISR */
SetEntry(0x0, InterruptHandler_0x0, IST1, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
SetEntry(0x1, InterruptHandler_0x1, IST1, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
SetEntry(0x1, InterruptHandler_0x1, IST1, TRAP_GATE_64BIT, RING3, EnableISRs, GDT_KERNEL_CODE);
SetEntry(0x2, InterruptHandler_0x2, IST2, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE);
SetEntry(0x3, InterruptHandler_0x3, IST1, TRAP_GATE_64BIT, RING3, (!DebuggerIsAttached), GDT_KERNEL_CODE); /* Do not handle breakpoints if we are debugging the kernel. */
SetEntry(0x4, InterruptHandler_0x4, IST1, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE);