From cfee4807c45101f34eaecb5240c853634190295b Mon Sep 17 00:00:00 2001 From: EnderIce2 Date: Fri, 20 Oct 2023 01:42:24 +0300 Subject: [PATCH] ISR 0x1 should have RING3 --- arch/amd64/cpu/idt.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/amd64/cpu/idt.cpp b/arch/amd64/cpu/idt.cpp index b87b78a..43cf63c 100644 --- a/arch/amd64/cpu/idt.cpp +++ b/arch/amd64/cpu/idt.cpp @@ -540,7 +540,7 @@ namespace InterruptDescriptorTable /* ISR */ SetEntry(0x0, InterruptHandler_0x0, IST1, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE); - SetEntry(0x1, InterruptHandler_0x1, IST1, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE); + SetEntry(0x1, InterruptHandler_0x1, IST1, TRAP_GATE_64BIT, RING3, EnableISRs, GDT_KERNEL_CODE); SetEntry(0x2, InterruptHandler_0x2, IST2, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE); SetEntry(0x3, InterruptHandler_0x3, IST1, TRAP_GATE_64BIT, RING3, (!DebuggerIsAttached), GDT_KERNEL_CODE); /* Do not handle breakpoints if we are debugging the kernel. */ SetEntry(0x4, InterruptHandler_0x4, IST1, TRAP_GATE_64BIT, RING0, EnableISRs, GDT_KERNEL_CODE);