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Fix CPU functions for aarch64

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This commit is contained in:
EnderIce2 2024-02-04 04:04:30 +02:00
parent f0ea4e3afb
commit bb946ea568
Signed by untrusted user who does not match committer: enderice2
GPG Key ID: EACC3AD603BAB4DD
2 changed files with 24 additions and 23 deletions
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21
core/cpu.cpp
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@ -53,8 +53,7 @@ namespace CPU
memcpy(Vendor + 4, &edx, 4); memcpy(Vendor + 4, &edx, 4);
memcpy(Vendor + 8, &ecx, 4); memcpy(Vendor + 8, &ecx, 4);
#elif defined(aa64) #elif defined(aa64)
asmv("mrs %0, MIDR_EL1" #error "Not implemented"
: "=r"(Vendor[0]));
#endif #endif
return Vendor; return Vendor;
} }
@ -99,8 +98,7 @@ namespace CPU
memcpy(Name + 40, &ecx, 4); memcpy(Name + 40, &ecx, 4);
memcpy(Name + 44, &edx, 4); memcpy(Name + 44, &edx, 4);
#elif defined(aa64) #elif defined(aa64)
asmv("mrs %0, MIDR_EL1" #error "Not implemented"
: "=r"(Name[0]));
#endif #endif
return Name; return Name;
} }
@ -143,8 +141,7 @@ namespace CPU
memcpy(Hypervisor + 4, &ecx, 4); memcpy(Hypervisor + 4, &ecx, 4);
memcpy(Hypervisor + 8, &edx, 4); memcpy(Hypervisor + 8, &edx, 4);
#elif defined(aa64) #elif defined(aa64)
asmv("mrs %0, MIDR_EL1" #error "Not implemented"
: "=r"(Hypervisor[0]));
#endif #endif
return Hypervisor; return Hypervisor;
} }
@ -169,7 +166,7 @@ namespace CPU
#elif defined(aa64) #elif defined(aa64)
asmv("mrs %0, cpsr" asmv("mrs %0, cpsr"
: "=r"(Flags)); : "=r"(Flags));
return !(Flags & (1 << 7)); return Flags & (1 << 7);
#endif #endif
} }
case Enable: case Enable:
@ -191,6 +188,7 @@ namespace CPU
return true; return true;
} }
default: default:
assert(!"Unknown InterruptsType");
break; break;
} }
return false; return false;
@ -207,7 +205,8 @@ namespace CPU
{ {
asmv("movq %0, %%cr3" asmv("movq %0, %%cr3"
: :
: "r"(PT)); : "r"(PT)
: "memory");
} }
#elif defined(a32) #elif defined(a32)
asmv("movl %%cr3, %0" asmv("movl %%cr3, %0"
@ -217,7 +216,8 @@ namespace CPU
{ {
asmv("movl %0, %%cr3" asmv("movl %0, %%cr3"
: :
: "r"(PT)); : "r"(PT)
: "memory");
} }
#elif defined(aa64) #elif defined(aa64)
asmv("mrs %0, ttbr0_el1" asmv("mrs %0, ttbr0_el1"
@ -227,7 +227,8 @@ namespace CPU
{ {
asmv("msr ttbr0_el1, %0" asmv("msr ttbr0_el1, %0"
: :
: "r"(PT)); : "r"(PT)
: "memory");
} }
#endif #endif
return ret; return ret;

26
include/cpu.hpp
View File

@ -154,21 +154,21 @@ namespace CPU
/** /**
* @brief Stop the CPU (infinite loop) * @brief Stop the CPU (infinite loop)
*/ */
#if defined(a86)
SafeFunction __noreturn __naked __used inline void Stop() SafeFunction __noreturn __naked __used inline void Stop()
{ {
#if defined(a86)
asmv("CPUStopLoop:\n" asmv("CPUStopLoop:\n"
"cli\n" "cli\n"
"hlt\n" "hlt\n"
"jmp CPUStopLoop"); "jmp CPUStopLoop");
#elif defined(aa64) // annoying warning: "'noreturn' function does return" and "'naked' attribute directive ignored" #elif defined(aa64)
SafeFunction __used inline void Stop()
{
asmv("CPUStopLoop:\n" asmv("CPUStopLoop:\n"
"msr daifset, #2\n" // Disable IRQs (bit 1 of the DAIF register) "cpsid i\n"
"wfi\n" // Wait for Interrupt (puts the processor in low-power state until an interrupt occurs) "wfe\n"
"b CPUStopLoop"); // Branch to the beginning of the loop "wfi\n"
"b CPUStopLoop");
#endif #endif
__builtin_unreachable();
} }
/** /**
@ -987,12 +987,12 @@ namespace CPU
*/ */
typedef x32::TrapFrame TrapFrame; typedef x32::TrapFrame TrapFrame;
#elif defined(aa64) #elif defined(aa64)
/** /**
* CPU trap frame for the current architecture * CPU trap frame for the current architecture
* *
* @note This is for aarch64 * @note This is for aarch64
*/ */
typedef aarch64::TrapFrame TrapFrame; typedef aarch64::TrapFrame TrapFrame;
#endif #endif
} }