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Moved IOAPICVersion

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This commit is contained in:
Alex 2022-10-23 03:17:57 +03:00
parent eb65bd1896
commit 782b3fa78a
Signed by untrusted user who does not match committer: enderice2
GPG Key ID: EACC3AD603BAB4DD
2 changed files with 27 additions and 22 deletions
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25
Architecture/amd64/cpu/AdvancedProgrammableInterruptController.cpp
View File

@ -13,25 +13,6 @@ using namespace CPU::x64;
namespace APIC namespace APIC
{ {
enum IOAPICRegisters
{
GetIOAPICVersion = 0x1
};
enum IOAPICFlags
{
ActiveHighLow = 2,
EdgeLevel = 8
};
struct IOAPICVersion
{
uint8_t Version;
uint8_t Reserved;
uint8_t MaximumRedirectionEntry;
uint8_t Reserved2;
};
// headache // headache
// https://www.amd.com/system/files/TechDocs/24593.pdf // https://www.amd.com/system/files/TechDocs/24593.pdf
// https://www.naic.edu/~phil/software/intel/318148.pdf // https://www.naic.edu/~phil/software/intel/318148.pdf
@ -49,7 +30,7 @@ namespace APIC
else else
{ {
CPU::MemBar::Barrier(); CPU::MemBar::Barrier();
uint32_t ret = *((volatile uint32_t *)((uintptr_t)((ACPI::MADT *)PowerManager->GetMADT())->LAPICAddress + Register)); uint32_t ret = *((volatile uint32_t *)((uintptr_t)APICBaseAddress + Register));
CPU::MemBar::Barrier(); CPU::MemBar::Barrier();
return ret; return ret;
} }
@ -72,7 +53,7 @@ namespace APIC
else else
{ {
CPU::MemBar::Barrier(); CPU::MemBar::Barrier();
*((volatile uint32_t *)(((uintptr_t)((ACPI::MADT *)PowerManager->GetMADT())->LAPICAddress) + Register)) = Value; *((volatile uint32_t *)(((uintptr_t)APICBaseAddress) + Register)) = Value;
CPU::MemBar::Barrier(); CPU::MemBar::Barrier();
} }
} }
@ -182,7 +163,7 @@ namespace APIC
APIC::APIC(int Core) APIC::APIC(int Core)
{ {
APIC_BASE BaseStruct = {.raw = rdmsr(MSR_APIC_BASE)}; APIC_BASE BaseStruct = {.raw = rdmsr(MSR_APIC_BASE)};
void *APICBaseAddress = (void *)(uint64_t)(BaseStruct.ApicBaseLo << 12u | BaseStruct.ApicBaseHi << 32u); APICBaseAddress = BaseStruct.ApicBaseLo << 12u | BaseStruct.ApicBaseHi << 32u;
trace("APIC Address: %#lx", APICBaseAddress); trace("APIC Address: %#lx", APICBaseAddress);
uint32_t rcx; uint32_t rcx;

24
Architecture/amd64/cpu/apic.hpp
View File

@ -38,6 +38,17 @@ namespace APIC
APIC_TDCR = 0x3E0, // Divide Configuration (for Timer) APIC_TDCR = 0x3E0, // Divide Configuration (for Timer)
}; };
enum IOAPICRegisters
{
GetIOAPICVersion = 0x1
};
enum IOAPICFlags
{
ActiveHighLow = 2,
EdgeLevel = 8
};
typedef union typedef union
{ {
struct struct
@ -75,10 +86,23 @@ namespace APIC
uint64_t raw; uint64_t raw;
} __attribute__((packed)) LVTTimer; } __attribute__((packed)) LVTTimer;
typedef union
{
struct
{
uint64_t Version : 8;
uint64_t Reserved : 8;
uint64_t MaximumRedirectionEntry : 8;
uint64_t Reserved2 : 8;
};
uint64_t raw;
} __attribute__((packed)) IOAPICVersion;
class APIC class APIC
{ {
private: private:
bool x2APICSupported = false; bool x2APICSupported = false;
uint64_t APICBaseAddress = 0;
public: public:
uint32_t Read(uint32_t Register); uint32_t Read(uint32_t Register);