From 782b3fa78a5fb23d58ae4bc5a73388a94be0bdfb Mon Sep 17 00:00:00 2001
From: Alex <enderice2@users.noreply.github.com>
Date: Sun, 23 Oct 2022 03:17:57 +0300
Subject: [PATCH] Moved IOAPICVersion

---
 ...dvancedProgrammableInterruptController.cpp | 25 +++----------------
 Architecture/amd64/cpu/apic.hpp               | 24 ++++++++++++++++++
 2 files changed, 27 insertions(+), 22 deletions(-)

diff --git a/Architecture/amd64/cpu/AdvancedProgrammableInterruptController.cpp b/Architecture/amd64/cpu/AdvancedProgrammableInterruptController.cpp
index bb5a8db..b544504 100644
--- a/Architecture/amd64/cpu/AdvancedProgrammableInterruptController.cpp
+++ b/Architecture/amd64/cpu/AdvancedProgrammableInterruptController.cpp
@@ -13,25 +13,6 @@ using namespace CPU::x64;
 
 namespace APIC
 {
-    enum IOAPICRegisters
-    {
-        GetIOAPICVersion = 0x1
-    };
-
-    enum IOAPICFlags
-    {
-        ActiveHighLow = 2,
-        EdgeLevel = 8
-    };
-
-    struct IOAPICVersion
-    {
-        uint8_t Version;
-        uint8_t Reserved;
-        uint8_t MaximumRedirectionEntry;
-        uint8_t Reserved2;
-    };
-
     // headache
     // https://www.amd.com/system/files/TechDocs/24593.pdf
     // https://www.naic.edu/~phil/software/intel/318148.pdf
@@ -49,7 +30,7 @@ namespace APIC
         else
         {
             CPU::MemBar::Barrier();
-            uint32_t ret = *((volatile uint32_t *)((uintptr_t)((ACPI::MADT *)PowerManager->GetMADT())->LAPICAddress + Register));
+            uint32_t ret = *((volatile uint32_t *)((uintptr_t)APICBaseAddress + Register));
             CPU::MemBar::Barrier();
             return ret;
         }
@@ -72,7 +53,7 @@ namespace APIC
         else
         {
             CPU::MemBar::Barrier();
-            *((volatile uint32_t *)(((uintptr_t)((ACPI::MADT *)PowerManager->GetMADT())->LAPICAddress) + Register)) = Value;
+            *((volatile uint32_t *)(((uintptr_t)APICBaseAddress) + Register)) = Value;
             CPU::MemBar::Barrier();
         }
     }
@@ -182,7 +163,7 @@ namespace APIC
     APIC::APIC(int Core)
     {
         APIC_BASE BaseStruct = {.raw = rdmsr(MSR_APIC_BASE)};
-        void *APICBaseAddress = (void *)(uint64_t)(BaseStruct.ApicBaseLo << 12u | BaseStruct.ApicBaseHi << 32u);
+        APICBaseAddress = BaseStruct.ApicBaseLo << 12u | BaseStruct.ApicBaseHi << 32u;
         trace("APIC Address: %#lx", APICBaseAddress);
 
         uint32_t rcx;
diff --git a/Architecture/amd64/cpu/apic.hpp b/Architecture/amd64/cpu/apic.hpp
index ef6fa35..bf70cb3 100644
--- a/Architecture/amd64/cpu/apic.hpp
+++ b/Architecture/amd64/cpu/apic.hpp
@@ -38,6 +38,17 @@ namespace APIC
         APIC_TDCR = 0x3E0,    // Divide Configuration (for Timer)
     };
 
+    enum IOAPICRegisters
+    {
+        GetIOAPICVersion = 0x1
+    };
+
+    enum IOAPICFlags
+    {
+        ActiveHighLow = 2,
+        EdgeLevel = 8
+    };
+
     typedef union
     {
         struct
@@ -75,10 +86,23 @@ namespace APIC
         uint64_t raw;
     } __attribute__((packed)) LVTTimer;
 
+    typedef union
+    {
+        struct
+        {
+            uint64_t Version : 8;
+            uint64_t Reserved : 8;
+            uint64_t MaximumRedirectionEntry : 8;
+            uint64_t Reserved2 : 8;
+        };
+        uint64_t raw;
+    } __attribute__((packed)) IOAPICVersion;
+
     class APIC
     {
     private:
         bool x2APICSupported = false;
+        uint64_t APICBaseAddress = 0;
 
     public:
         uint32_t Read(uint32_t Register);