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x32 is now compiling

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This commit is contained in:
Alex
2023-03-04 21:17:19 +02:00
parent aa29c8a415
commit 5c91f23527
57 changed files with 1217 additions and 573 deletions
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26
include/cpu/x86/x64/cr.hpp
View File

@ -172,127 +172,105 @@ namespace CPU
uint64_t raw;
} XCR0;
#if defined(a64)
SafeFunction static inline CR0 readcr0()
{
uint64_t Result = 0;
#if defined(__amd64__)
asmv("mov %%cr0, %[Result]"
: [Result] "=q"(Result));
#endif
return (CR0){.raw = Result};
}
SafeFunction static inline CR2 readcr2()
{
uint64_t Result = 0;
#if defined(__amd64__)
asmv("mov %%cr2, %[Result]"
: [Result] "=q"(Result));
#endif
return (CR2){.raw = Result};
}
SafeFunction static inline CR3 readcr3()
{
uint64_t Result = 0;
#if defined(__amd64__)
asmv("mov %%cr3, %[Result]"
: [Result] "=q"(Result));
#endif
return (CR3){.raw = Result};
}
SafeFunction static inline CR4 readcr4()
{
uint64_t Result = 0;
#if defined(__amd64__)
asmv("mov %%cr4, %[Result]"
: [Result] "=q"(Result));
#endif
return (CR4){.raw = Result};
}
SafeFunction static inline CR8 readcr8()
{
uint64_t Result = 0;
#if defined(__amd64__)
asmv("mov %%cr8, %[Result]"
: [Result] "=q"(Result));
#endif
return (CR8){.raw = Result};
}
SafeFunction static inline XCR0 readxcr0()
{
uint64_t Result = 0;
#if defined(__amd64__)
asmv("xgetbv"
: "=a"(Result)
: "c"(0)
: "edx");
#endif
return (XCR0){.raw = Result};
}
SafeFunction static inline void writecr0(CR0 ControlRegister)
{
#if defined(__amd64__)
asmv("mov %[ControlRegister], %%cr0"
:
: [ControlRegister] "q"(ControlRegister.raw)
: "memory");
#endif
}
SafeFunction static inline void writecr2(CR2 ControlRegister)
{
#if defined(__amd64__)
asmv("mov %[ControlRegister], %%cr2"
:
: [ControlRegister] "q"(ControlRegister.raw)
: "memory");
#endif
}
SafeFunction static inline void writecr3(CR3 ControlRegister)
{
#if defined(__amd64__)
asmv("mov %[ControlRegister], %%cr3"
:
: [ControlRegister] "q"(ControlRegister.raw)
: "memory");
#endif
}
SafeFunction static inline void writecr4(CR4 ControlRegister)
{
#if defined(__amd64__)
asmv("mov %[ControlRegister], %%cr4"
:
: [ControlRegister] "q"(ControlRegister.raw)
: "memory");
#endif
}
SafeFunction static inline void writecr8(CR8 ControlRegister)
{
#if defined(__amd64__)
asmv("mov %[ControlRegister], %%cr8"
:
: [ControlRegister] "q"(ControlRegister.raw)
: "memory");
#endif
}
SafeFunction static inline void writexcr0(XCR0 ControlRegister)
{
#if defined(__amd64__)
asmv("xsetbv"
:
: "a"(ControlRegister.raw), "c"(0)
: "edx");
#endif
}
#endif
}
}

6
include/cpu/x86/x64/msr.hpp
View File

@ -384,28 +384,26 @@ namespace CPU
MSR_CR_PAT_RESET = 0x0007040600070406ULL
};
#if defined(a64)
SafeFunction static inline uint64_t rdmsr(uint32_t msr)
{
uint32_t Low, High;
#if defined(__amd64__)
asmv("rdmsr"
: "=a"(Low), "=d"(High)
: "c"(msr)
: "memory");
#endif
return ((uint64_t)Low) | (((uint64_t)High) << 32);
}
SafeFunction static inline void wrmsr(uint32_t msr, uint64_t Value)
{
uint32_t Low = Value, High = Value >> 32;
#if defined(__amd64__)
asmv("wrmsr"
:
: "c"(msr), "a"(Low), "d"(High)
: "memory");
#endif
}
#endif
}
}