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x32 is now compiling

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This commit is contained in:
Alex 2023-03-04 21:17:19 +02:00
parent aa29c8a415
commit 5c91f23527
Signed by untrusted user who does not match committer: enderice2
GPG Key ID: EACC3AD603BAB4DD
57 changed files with 1217 additions and 573 deletions
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12
Architecture/amd64/cpu/AdvancedProgrammableInterruptController.cpp
View File

@ -241,12 +241,12 @@ namespace APIC
bool x2APICSupported = false;
if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::AMD::CPUID0x1 cpuid1amd;
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::AMD::CPUID0x1 cpuid1amd;
#endif
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("cpuid"
: "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw)
: "a"(0x1));
@ -257,12 +257,12 @@ namespace APIC
}
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::Intel::CPUID0x1 cpuid1intel;
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::Intel::CPUID0x1 cpuid1intel;
#endif
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("cpuid"
: "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw)
: "a"(0x1));

44
Architecture/i686/ArithmeticOperations.c
View File

@ -158,7 +158,7 @@ int __ctzdi2(arith64_u64 a)
arith64_u64 __divmoddi4(arith64_u64 a, arith64_u64 b, arith64_u64 *c)
{
if (b > a) //
if (b > a)
{
if (c)
*c = a;
@ -283,3 +283,45 @@ int __gedf2(double a, double b) { return a >= b; }
int __fixdfsi(double a) { return (int)a; }
long __fixdfdi(double a) { return (long)a; }
int __ledf2(double a, double b) { return a <= b; }
/* FIXME: Check if these functions are implemented correctly */
typedef long long int64_t;
typedef unsigned long long uint64_t;
typedef unsigned int uint32_t;
typedef struct
{
uint64_t value;
} atomic_uint64_t;
uint64_t __atomic_load_8(const atomic_uint64_t *p)
{
uint64_t value;
__asm__ volatile("lock cmpxchg8b %1"
: "=A"(value)
: "m"(*p)
: "memory");
return value;
}
void __atomic_store_8(atomic_uint64_t *p, uint64_t value)
{
__asm__ volatile("lock cmpxchg8b %0"
: "=m"(p->value)
: "a"((uint32_t)value), "d"((uint32_t)(value >> 32)), "m"(*p)
: "memory");
}
/* FIXME: __fixsfsi is not implemented correctly(?) */
int __fixsfsi(float a) { return (int)a; }
int __ltsf2(float a, float b) { return a < b; }
int __eqsf2(float a, float b) { return a == b; }
float __divsf3(float a, float b) { return a / b; }
double __extendsfdf2(float a) { return (double)a; }
float __truncdfsf2(double a) { return (float)a; }
float __subsf3(float a, float b) { return a - b; }
float __floatsisf(int a) { return (float)a; }
int __fixunssfsi(float a) { return (int)a; }
float __mulsf3(float a, float b) { return a * b; }
float __addsf3(float a, float b) { return a + b; }

206
Architecture/i686/Multiboot2.cpp
View File

@ -1,10 +1,13 @@
#include <types.h>
#include <boot/protocols/multiboot2.h>
#include <memory.hpp>
#include <io.h>
#include "../../kernel.h"
BootInfo mb2binfo;
enum VideoType
{
VIDEO_TYPE_NONE = 0x00,
@ -47,72 +50,52 @@ void GetSMBIOS()
}
}
struct multiboot_info
void ProcessMB2(unsigned long Info)
{
multiboot_uint32_t Size;
multiboot_uint32_t Reserved;
struct multiboot_tag *Tag;
};
EXTERNC void x32Multiboot2Entry(multiboot_info *Info, unsigned int Magic)
{
if (Info == NULL || Magic == NULL)
uint8_t *VideoBuffer = (uint8_t *)0xB8F00 + 0xC0000000;
int pos = 0;
auto InfoAddress = Info;
for (auto Tag = (struct multiboot_tag *)((uint8_t *)InfoAddress + 8);
;
Tag = (struct multiboot_tag *)((multiboot_uint8_t *)Tag + ((Tag->size + 7) & ~7)))
{
if (Magic == NULL)
error("Multiboot magic is NULL");
if (Info == NULL)
error("Multiboot info is NULL");
CPU::Stop();
}
else if (Magic != MULTIBOOT2_BOOTLOADER_MAGIC)
{
error("Multiboot magic is invalid (%#x != %#x)", Magic, MULTIBOOT2_BOOTLOADER_MAGIC);
trace("Hello, World!");
CPU::Stop();
}
VideoBuffer[pos++] = '.';
VideoBuffer[pos++] = 0x2;
uint64_t div = 1193180 / 1000;
outb(0x43, 0xB6);
outb(0x42, (uint8_t)div);
outb(0x42, (uint8_t)(div >> 8));
uint8_t tmp = inb(0x61);
if (tmp != (tmp | 3))
outb(0x61, tmp | 3);
BootInfo binfo;
uint32_t Itr = 0;
for (uint32_t i = 8; i < Info->Size; i += Itr)
{
multiboot_tag *Tag = (multiboot_tag *)((uint8_t *)Info + i);
if (Tag->type == MULTIBOOT_TAG_TYPE_END)
{
debug("End of multiboot2 tags");
break;
}
switch (Tag->type)
{
case MULTIBOOT_TAG_TYPE_CMDLINE:
{
strncpy(binfo.Kernel.CommandLine,
strncpy(mb2binfo.Kernel.CommandLine,
((multiboot_tag_string *)Tag)->string,
strlen(((multiboot_tag_string *)Tag)->string));
debug("Kernel command line: %s", mb2binfo.Kernel.CommandLine);
break;
}
case MULTIBOOT_TAG_TYPE_BOOT_LOADER_NAME:
{
strncpy(binfo.Bootloader.Name,
strncpy(mb2binfo.Bootloader.Name,
((multiboot_tag_string *)Tag)->string,
strlen(((multiboot_tag_string *)Tag)->string));
debug("Bootloader name: %s", mb2binfo.Bootloader.Name);
break;
}
case MULTIBOOT_TAG_TYPE_MODULE:
{
multiboot_tag_module *module = (multiboot_tag_module *)Tag;
static int module_count = 0;
binfo.Modules[module_count++].Address = (void *)module->mod_start;
binfo.Modules[module_count++].Size = module->size;
strncpy(binfo.Modules[module_count++].Path, "(null)", 6);
strncpy(binfo.Modules[module_count++].CommandLine, module->cmdline,
mb2binfo.Modules[module_count++].Address = (void *)module->mod_start;
mb2binfo.Modules[module_count++].Size = module->size;
strncpy(mb2binfo.Modules[module_count++].Path, "(null)", 6);
strncpy(mb2binfo.Modules[module_count++].CommandLine, module->cmdline,
strlen(module->cmdline));
debug("Module: %s", mb2binfo.Modules[module_count++].Path);
break;
}
case MULTIBOOT_TAG_TYPE_BASIC_MEMINFO:
@ -133,8 +116,7 @@ EXTERNC void x32Multiboot2Entry(multiboot_info *Info, unsigned int Magic)
{
multiboot_tag_mmap *mmap = (multiboot_tag_mmap *)Tag;
uint32_t EntryCount = mmap->size / sizeof(multiboot_mmap_entry);
binfo.Memory.Entries = EntryCount;
mb2binfo.Memory.Entries = EntryCount;
for (uint32_t i = 0; i < EntryCount; i++)
{
if (EntryCount > MAX_MEMORY_ENTRIES)
@ -142,42 +124,45 @@ EXTERNC void x32Multiboot2Entry(multiboot_info *Info, unsigned int Magic)
warn("Too many memory entries, skipping the rest...");
break;
}
multiboot_mmap_entry entry = mmap->entries[i];
binfo.Memory.Size += entry.len;
mb2binfo.Memory.Size += entry.len;
switch (entry.type)
{
case MULTIBOOT_MEMORY_AVAILABLE:
binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
binfo.Memory.Entry[i].Length = entry.len;
binfo.Memory.Entry[i].Type = Usable;
mb2binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
mb2binfo.Memory.Entry[i].Length = entry.len;
mb2binfo.Memory.Entry[i].Type = Usable;
break;
case MULTIBOOT_MEMORY_RESERVED:
binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
binfo.Memory.Entry[i].Length = entry.len;
binfo.Memory.Entry[i].Type = Reserved;
mb2binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
mb2binfo.Memory.Entry[i].Length = entry.len;
mb2binfo.Memory.Entry[i].Type = Reserved;
break;
case MULTIBOOT_MEMORY_ACPI_RECLAIMABLE:
binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
binfo.Memory.Entry[i].Length = entry.len;
binfo.Memory.Entry[i].Type = ACPIReclaimable;
mb2binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
mb2binfo.Memory.Entry[i].Length = entry.len;
mb2binfo.Memory.Entry[i].Type = ACPIReclaimable;
break;
case MULTIBOOT_MEMORY_NVS:
binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
binfo.Memory.Entry[i].Length = entry.len;
binfo.Memory.Entry[i].Type = ACPINVS;
mb2binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
mb2binfo.Memory.Entry[i].Length = entry.len;
mb2binfo.Memory.Entry[i].Type = ACPINVS;
break;
case MULTIBOOT_MEMORY_BADRAM:
binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
binfo.Memory.Entry[i].Length = entry.len;
binfo.Memory.Entry[i].Type = BadMemory;
mb2binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
mb2binfo.Memory.Entry[i].Length = entry.len;
mb2binfo.Memory.Entry[i].Type = BadMemory;
break;
default:
binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
binfo.Memory.Entry[i].Length = entry.len;
binfo.Memory.Entry[i].Type = Unknown;
mb2binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
mb2binfo.Memory.Entry[i].Length = entry.len;
mb2binfo.Memory.Entry[i].Type = Unknown;
break;
}
debug("Memory entry: [BaseAddress: %#x, Length: %#x, Type: %d]",
mb2binfo.Memory.Entry[i].BaseAddress,
mb2binfo.Memory.Entry[i].Length,
mb2binfo.Memory.Entry[i].Type);
}
break;
}
@ -192,14 +177,12 @@ EXTERNC void x32Multiboot2Entry(multiboot_info *Info, unsigned int Magic)
{
multiboot_tag_framebuffer *fb = (multiboot_tag_framebuffer *)Tag;
static int fb_count = 0;
binfo.Framebuffer[fb_count].BaseAddress = (void *)fb->common.framebuffer_addr;
binfo.Framebuffer[fb_count].Width = fb->common.framebuffer_width;
binfo.Framebuffer[fb_count].Height = fb->common.framebuffer_height;
binfo.Framebuffer[fb_count].Pitch = fb->common.framebuffer_pitch;
binfo.Framebuffer[fb_count].BitsPerPixel = fb->common.framebuffer_bpp;
binfo.Framebuffer[fb_count].MemoryModel = fb->common.framebuffer_type;
mb2binfo.Framebuffer[fb_count].BaseAddress = (void *)fb->common.framebuffer_addr;
mb2binfo.Framebuffer[fb_count].Width = fb->common.framebuffer_width;
mb2binfo.Framebuffer[fb_count].Height = fb->common.framebuffer_height;
mb2binfo.Framebuffer[fb_count].Pitch = fb->common.framebuffer_pitch;
mb2binfo.Framebuffer[fb_count].BitsPerPixel = fb->common.framebuffer_bpp;
mb2binfo.Framebuffer[fb_count].MemoryModel = fb->common.framebuffer_type;
switch (fb->common.framebuffer_type)
{
case MULTIBOOT_FRAMEBUFFER_TYPE_INDEXED:
@ -209,12 +192,12 @@ EXTERNC void x32Multiboot2Entry(multiboot_info *Info, unsigned int Magic)
}
case MULTIBOOT_FRAMEBUFFER_TYPE_RGB:
{
binfo.Framebuffer[fb_count].RedMaskSize = fb->framebuffer_red_mask_size;
binfo.Framebuffer[fb_count].RedMaskShift = fb->framebuffer_red_field_position;
binfo.Framebuffer[fb_count].GreenMaskSize = fb->framebuffer_green_mask_size;
binfo.Framebuffer[fb_count].GreenMaskShift = fb->framebuffer_green_field_position;
binfo.Framebuffer[fb_count].BlueMaskSize = fb->framebuffer_blue_mask_size;
binfo.Framebuffer[fb_count].BlueMaskShift = fb->framebuffer_blue_field_position;
mb2binfo.Framebuffer[fb_count].RedMaskSize = fb->framebuffer_red_mask_size;
mb2binfo.Framebuffer[fb_count].RedMaskShift = fb->framebuffer_red_field_position;
mb2binfo.Framebuffer[fb_count].GreenMaskSize = fb->framebuffer_green_mask_size;
mb2binfo.Framebuffer[fb_count].GreenMaskShift = fb->framebuffer_green_field_position;
mb2binfo.Framebuffer[fb_count].BlueMaskSize = fb->framebuffer_blue_mask_size;
mb2binfo.Framebuffer[fb_count].BlueMaskShift = fb->framebuffer_blue_field_position;
break;
}
case MULTIBOOT_FRAMEBUFFER_TYPE_EGA_TEXT:
@ -223,12 +206,11 @@ EXTERNC void x32Multiboot2Entry(multiboot_info *Info, unsigned int Magic)
break;
}
}
debug("Framebuffer %d: %dx%d %d bpp", i, fb->common.framebuffer_width, fb->common.framebuffer_height, fb->common.framebuffer_bpp);
debug("Framebuffer %d: %dx%d %d bpp", Tag, fb->common.framebuffer_width, fb->common.framebuffer_height, fb->common.framebuffer_bpp);
debug("More info:\nAddress: %p\nPitch: %lld\nMemoryModel: %d\nRedMaskSize: %d\nRedMaskShift: %d\nGreenMaskSize: %d\nGreenMaskShift: %d\nBlueMaskSize: %d\nBlueMaskShift: %d",
fb->common.framebuffer_addr, fb->common.framebuffer_pitch, fb->common.framebuffer_type,
fb->framebuffer_red_mask_size, fb->framebuffer_red_field_position, fb->framebuffer_green_mask_size,
fb->framebuffer_green_field_position, fb->framebuffer_blue_mask_size, fb->framebuffer_blue_field_position);
fb_count++;
break;
}
@ -266,12 +248,14 @@ EXTERNC void x32Multiboot2Entry(multiboot_info *Info, unsigned int Magic)
}
case MULTIBOOT_TAG_TYPE_ACPI_OLD:
{
binfo.RSDP = (BootInfo::RSDPInfo *)((multiboot_tag_old_acpi *)Tag)->rsdp;
mb2binfo.RSDP = (BootInfo::RSDPInfo *)((multiboot_tag_old_acpi *)Tag)->rsdp;
debug("OLD ACPI RSDP: %p", mb2binfo.RSDP);
break;
}
case MULTIBOOT_TAG_TYPE_ACPI_NEW:
{
binfo.RSDP = (BootInfo::RSDPInfo *)((multiboot_tag_new_acpi *)Tag)->rsdp;
mb2binfo.RSDP = (BootInfo::RSDPInfo *)((multiboot_tag_new_acpi *)Tag)->rsdp;
debug("NEW ACPI RSDP: %p", mb2binfo.RSDP);
break;
}
case MULTIBOOT_TAG_TYPE_NETWORK:
@ -307,37 +291,49 @@ EXTERNC void x32Multiboot2Entry(multiboot_info *Info, unsigned int Magic)
case MULTIBOOT_TAG_TYPE_LOAD_BASE_ADDR:
{
multiboot_tag_load_base_addr *load_base_addr = (multiboot_tag_load_base_addr *)Tag;
binfo.Kernel.PhysicalBase = (void *)load_base_addr->load_base_addr;
binfo.Kernel.VirtualBase = (void *)(load_base_addr->load_base_addr + 0xC0000000);
mb2binfo.Kernel.PhysicalBase = (void *)load_base_addr->load_base_addr;
mb2binfo.Kernel.VirtualBase = (void *)(load_base_addr->load_base_addr + 0xC0000000);
debug("Kernel base: %p (physical) %p (virtual)", mb2binfo.Kernel.PhysicalBase, mb2binfo.Kernel.VirtualBase);
break;
}
default:
{
error("Unknown multiboot2 tag type: %d", Tag->type);
break;
}
}
Itr = Tag->size;
if ((Itr % 8) != 0)
Itr += (8 - Itr % 8);
}
}
EXTERNC void x32Multiboot2Entry(unsigned long Info, unsigned int Magic)
{
if (Info == NULL || Magic == NULL)
{
if (Magic == NULL)
error("Multiboot magic is NULL");
if (Info == NULL)
error("Multiboot info is NULL");
CPU::Stop();
}
else if (Magic != MULTIBOOT2_BOOTLOADER_MAGIC)
{
error("Multiboot magic is invalid (%#x != %#x)", Magic, MULTIBOOT2_BOOTLOADER_MAGIC);
CPU::Stop();
}
uint64_t div = 1193180 / 1000;
outb(0x43, 0xB6);
outb(0x42, (uint8_t)div);
outb(0x42, (uint8_t)(div >> 8));
uint8_t tmp = inb(0x61);
if (tmp != (tmp | 3))
outb(0x61, tmp | 3);
ProcessMB2(Info);
tmp = inb(0x61) & 0xFC;
outb(0x61, tmp);
int *vm = (int *)0xb8000;
// "Not supported yet"
vm[0] = 0x054E;
vm[1] = 0x056F;
vm[2] = 0x0574;
vm[3] = 0x0520;
vm[4] = 0x0573;
vm[5] = 0x0575;
vm[6] = 0x0570;
vm[7] = 0x0570;
vm[8] = 0x0572;
vm[9] = 0x056F;
vm[10] = 0x0574;
vm[11] = 0x0520;
vm[12] = 0x0579;
vm[13] = 0x0565;
vm[14] = 0x0574;
CPU::Stop();
// Entry(&binfo);
Entry(&mb2binfo);
}

2
Architecture/i686/cpu/apic.hpp
View File

@ -324,7 +324,7 @@ namespace APIC
private:
APIC *lapic;
uint64_t Ticks = 0;
void OnInterruptReceived(CPU::x64::TrapFrame *Frame);
void OnInterruptReceived(CPU::x32::TrapFrame *Frame);
public:
uint64_t GetTicks() { return Ticks; }

61
Architecture/i686/runtime/crt1.asm
View File

@ -1,4 +1,5 @@
; Inspired From: https://github.com/MQuy/mos/blob/master/src/kernel/boot.asm
; https://wiki.osdev.org/Higher_Half_x86_Bare_Bones
; https://wiki.osdev.org/Higher_Half_x86_Bare_Bones_(Backup)
section .multiboot2
align 4096
HEADER_START:
@ -7,6 +8,33 @@ HEADER_START:
dd (HEADER_END - HEADER_START)
dd 0x100000000 - (HEADER_END - HEADER_START) - 0 - 0xE85250D6
align 8
MB2_INFO_REQUEST_TAG_START:
dw 1
dw 0
dd MB2_INFO_REQUEST_TAG_END - MB2_INFO_REQUEST_TAG_START
dd 1 ; Command Line
dd 2 ; Boot Loader Name
dd 3 ; Module
dd 4 ; Basic Memory Information
dd 5 ; BIOS Boot Device
dd 6 ; Memory Map
dd 7 ; VBE
dd 8 ; Framebuffer
dd 9 ; ELF Sections
dd 10 ; APM Table
dd 11 ; EFI 32-bit System Table Pointer
dd 12 ; EFI 64-bit System Table Pointer
; dd 13 ; SMBIOS
dd 14 ; ACPI Old
dd 15 ; ACPI New
dd 16 ; Network
dd 17 ; EFI Memory Map
dd 18 ; EFI Boot Services Notifier
dd 19 ; EFI 32-bit Image Handle Pointer
dd 20 ; EFI 64-bit Image Handle Pointer
dd 21 ; Load Base Address
MB2_INFO_REQUEST_TAG_END:
align 8
MB2_TAG_START:
dw 0
dw 0
@ -25,34 +53,41 @@ section .data
align 0x1000
BootPageTable:
dd 0x00000083
times ((KERNEL_PAGE_NUMBER) - 1) dd 0
dd 0x00000083
times (1024 - KERNEL_PAGE_NUMBER - 1) dd 0
times (KERNEL_PAGE_NUMBER - 2) dd 0
dd 0x00000083
dd 0x00000083
times (1024 - KERNEL_PAGE_NUMBER - 2) dd 0
section .text
_start:
mov word [0xb8000], 0x074C ; L
mov word [0xb8002], 0x076F ; o
mov word [0xb8004], 0x0761 ; a
mov word [0xb8006], 0x0764 ; d
mov word [0xb8008], 0x0769 ; i
mov word [0xb800a], 0x076E ; n
mov word [0xb800c], 0x0767 ; g
mov word [0xb800e], 0x072E ; .
mov word [0xb8010], 0x072E ; .
mov word [0xb8012], 0x072E ; .
mov word [0xb8F00], 0x072E ; .
mov ecx, (BootPageTable - KERNEL_VIRTUAL_BASE)
mov cr3, ecx
mov word [0xb8F02], 0x072E ; .
mov ecx, cr4
or ecx, 0x00000010 ; Set PSE in CR4
mov cr4, ecx
mov word [0xb8F04], 0x072E ; .
mov ecx, cr0
or ecx, 0x80000000 ; Set PG in CR0
mov cr0, ecx
mov word [0xb8F06], 0x072E ; .
lea ecx, [HigherHalfStart]
jmp ecx
HigherHalfStart:
mov word [0xb8F08], 0x072E ; .
mov dword [BootPageTable], 0
invlpg [0]
mov esp, KernelStack + KERNEL_STACK_SIZE
push eax ; Multiboot2 Magic

90
Core/CPU.cpp
View File

@ -14,19 +14,19 @@ namespace CPU
char *Vendor()
{
static char Vendor[13];
#if defined(__amd64__)
#if defined(a64)
uint32_t eax, ebx, ecx, edx;
x64::cpuid(0x0, &eax, &ebx, &ecx, &edx);
memcpy_unsafe(Vendor + 0, &ebx, 4);
memcpy_unsafe(Vendor + 4, &edx, 4);
memcpy_unsafe(Vendor + 8, &ecx, 4);
#elif defined(__i386__)
#elif defined(a32)
uint32_t eax, ebx, ecx, edx;
x32::cpuid(0x0, &eax, &ebx, &ecx, &edx);
memcpy_unsafe(Vendor + 0, &ebx, 4);
memcpy_unsafe(Vendor + 4, &edx, 4);
memcpy_unsafe(Vendor + 8, &ecx, 4);
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("mrs %0, MIDR_EL1"
: "=r"(Vendor[0]));
#endif
@ -36,7 +36,7 @@ namespace CPU
char *Name()
{
static char Name[49];
#if defined(__amd64__)
#if defined(a64)
uint32_t eax, ebx, ecx, edx;
x64::cpuid(0x80000002, &eax, &ebx, &ecx, &edx);
memcpy_unsafe(Name + 0, &eax, 4);
@ -53,7 +53,7 @@ namespace CPU
memcpy_unsafe(Name + 36, &ebx, 4);
memcpy_unsafe(Name + 40, &ecx, 4);
memcpy_unsafe(Name + 44, &edx, 4);
#elif defined(__i386__)
#elif defined(a32)
uint32_t eax, ebx, ecx, edx;
x32::cpuid(0x80000002, &eax, &ebx, &ecx, &edx);
memcpy_unsafe(Name + 0, &eax, 4);
@ -70,7 +70,7 @@ namespace CPU
memcpy_unsafe(Name + 36, &ebx, 4);
memcpy_unsafe(Name + 40, &ecx, 4);
memcpy_unsafe(Name + 44, &edx, 4);
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("mrs %0, MIDR_EL1"
: "=r"(Name[0]));
#endif
@ -80,19 +80,19 @@ namespace CPU
char *Hypervisor()
{
static char Hypervisor[13];
#if defined(__amd64__)
#if defined(a64)
uint32_t eax, ebx, ecx, edx;
x64::cpuid(0x40000000, &eax, &ebx, &ecx, &edx);
memcpy_unsafe(Hypervisor + 0, &ebx, 4);
memcpy_unsafe(Hypervisor + 4, &ecx, 4);
memcpy_unsafe(Hypervisor + 8, &edx, 4);
#elif defined(__i386__)
#elif defined(a32)
uint32_t eax, ebx, ecx, edx;
x64::cpuid(0x40000000, &eax, &ebx, &ecx, &edx);
memcpy_unsafe(Hypervisor + 0, &ebx, 4);
memcpy_unsafe(Hypervisor + 4, &ecx, 4);
memcpy_unsafe(Hypervisor + 8, &edx, 4);
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("mrs %0, MIDR_EL1"
: "=r"(Hypervisor[0]));
#endif
@ -106,17 +106,17 @@ namespace CPU
case Check:
{
uintptr_t Flags;
#if defined(__amd64__)
#if defined(a64)
asmv("pushfq");
asmv("popq %0"
: "=r"(Flags));
return Flags & (1 << 9);
#elif defined(__i386__)
#elif defined(a32)
asmv("pushfl");
asmv("popl %0"
: "=r"(Flags));
return Flags & (1 << 9);
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("mrs %0, daif"
: "=r"(Flags));
return !(Flags & (1 << 2));
@ -124,18 +124,18 @@ namespace CPU
}
case Enable:
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("sti");
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("msr daifclr, #2");
#endif
return true;
}
case Disable:
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("cli");
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("msr daifset, #2");
#endif
return true;
@ -146,7 +146,7 @@ namespace CPU
void *PageTable(void *PT)
{
#if defined(__amd64__)
#if defined(a64)
if (PT)
asmv("movq %0, %%cr3"
:
@ -154,7 +154,7 @@ namespace CPU
else
asmv("movq %%cr3, %0"
: "=r"(PT));
#elif defined(__i386__)
#elif defined(a32)
if (PT)
asmv("movl %0, %%cr3"
:
@ -162,7 +162,7 @@ namespace CPU
else
asmv("movl %%cr3, %0"
: "=r"(PT));
#elif defined(__aarch64__)
#elif defined(aa64)
if (PT)
asmv("msr ttbr0_el1, %0"
:
@ -178,19 +178,19 @@ namespace CPU
{
bool PGESupport = false;
bool SSESupport = false;
#if defined(__amd64__)
#if defined(a64)
static int BSP = 0;
x64::CR0 cr0 = x64::readcr0();
x64::CR4 cr4 = x64::readcr4();
if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::AMD::CPUID0x1 cpuid1amd;
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::AMD::CPUID0x1 cpuid1amd;
#endif
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("cpuid"
: "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw)
: "a"(0x1));
@ -202,12 +202,12 @@ namespace CPU
}
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::Intel::CPUID0x1 cpuid1intel;
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::Intel::CPUID0x1 cpuid1intel;
#endif
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("cpuid"
: "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw)
: "a"(0x1));
@ -310,8 +310,8 @@ namespace CPU
trace("Features for BSP initialized.");
if (SSEEnableAfter)
SSEEnabled = true;
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
}
@ -319,13 +319,13 @@ namespace CPU
{
// TODO: Get the counter from the x2APIC or any other timer that is available. (TSC is not available on all CPUs)
uintptr_t Counter;
#if defined(__amd64__)
#if defined(a64)
asmv("rdtsc"
: "=A"(Counter));
#elif defined(__i386__)
#elif defined(a32)
asmv("rdtsc"
: "=A"(Counter));
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("mrs %0, cntvct_el0"
: "=r"(Counter));
#endif
@ -334,6 +334,10 @@ namespace CPU
x86SIMDType CheckSIMD()
{
#if defined(a32)
return SIMD_NONE; /* TODO: Support x86 SIMD on x32 */
#endif
if (unlikely(!SSEEnabled))
return SIMD_NONE;
@ -344,12 +348,12 @@ namespace CPU
if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::AMD::CPUID0x1 cpuid1amd;
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::AMD::CPUID0x1 cpuid1amd;
#endif
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("cpuid"
: "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw)
: "a"(0x1));
@ -382,12 +386,12 @@ namespace CPU
}
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::Intel::CPUID0x1 cpuid1intel;
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::Intel::CPUID0x1 cpuid1intel;
#endif
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("cpuid"
: "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw)
: "a"(0x1));
@ -429,12 +433,12 @@ namespace CPU
if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::AMD::CPUID0x1 cpuid1amd;
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::AMD::CPUID0x1 cpuid1amd;
#endif
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("cpuid"
: "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw)
: "a"(0x1));
@ -452,12 +456,12 @@ namespace CPU
}
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::Intel::CPUID0x1 cpuid1intel;
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::Intel::CPUID0x1 cpuid1intel;
#endif
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("cpuid"
: "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw)
: "a"(0x1));

34
Core/Crash/CrashDetails.cpp
View File

@ -7,10 +7,10 @@
#include <smp.hpp>
#include <cpu.hpp>
#if defined(__amd64__)
#if defined(a64)
#include "../../Architecture/amd64/cpu/gdt.hpp"
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
#include "../../kernel.h"
@ -100,11 +100,11 @@ SafeFunction void SegmentNotPresentExceptionHandler(CHArchTrapFrame *Frame)
SafeFunction void StackFaultExceptionHandler(CHArchTrapFrame *Frame)
{
CPU::x64::SelectorErrorCode SelCode = {.raw = Frame->ErrorCode};
#if defined(__amd64__)
#if defined(a64)
CrashHandler::EHPrint("Stack segment fault at address %#lx\n", Frame->rip);
#elif defined(__i386__)
#elif defined(a32)
CrashHandler::EHPrint("Stack segment fault at address %#lx\n", Frame->eip);
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
CrashHandler::EHPrint("External: %d\n", SelCode.External);
CrashHandler::EHPrint("Table: %d\n", SelCode.Table);
@ -142,11 +142,11 @@ SafeFunction void GeneralProtectionExceptionHandler(CHArchTrapFrame *Frame)
SafeFunction void PageFaultExceptionHandler(CHArchTrapFrame *Frame)
{
CPU::x64::PageFaultErrorCode params = {.raw = (uint32_t)Frame->ErrorCode};
#if defined(__amd64__)
#if defined(a64)
CrashHandler::EHPrint("\eAFAFAFAn exception occurred at %#lx by %#lx\n", CrashHandler::PageFaultAddress, Frame->rip);
#elif defined(__i386__)
#elif defined(a32)
CrashHandler::EHPrint("\eAFAFAFAn exception occurred at %#lx by %#lx\n", CrashHandler::PageFaultAddress, Frame->eip);
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
CrashHandler::EHPrint("Page: %s\n", params.P ? "Present" : "Not Present");
CrashHandler::EHPrint("Write Operation: %s\n", params.W ? "Read-Only" : "Read-Write");
@ -165,15 +165,20 @@ SafeFunction void PageFaultExceptionHandler(CHArchTrapFrame *Frame)
uintptr_t CheckPageFaultAddress = 0;
CheckPageFaultAddress = CrashHandler::PageFaultAddress;
if (CheckPageFaultAddress == 0)
#ifdef __amd64__
#ifdef a64
CheckPageFaultAddress = Frame->rip;
#elif defined(__i386__)
#elif defined(a32)
CheckPageFaultAddress = Frame->eip;
#elif defined(__aarch64__)
#elif defined(aa64)
CheckPageFaultAddress = 0;
#endif
#if defined(a64)
Memory::Virtual vma = Memory::Virtual(((Memory::PageTable4 *)CPU::x64::readcr3().raw));
#elif defined(a32)
Memory::Virtual vma = Memory::Virtual(((Memory::PageTable4 *)CPU::x32::readcr3().raw));
#elif defined(aa64)
#endif
bool PageAvailable = vma.Check((void *)CheckPageFaultAddress);
debug("Page available (Check(...)): %s. %s",
PageAvailable ? "Yes" : "No",
@ -213,7 +218,12 @@ SafeFunction void PageFaultExceptionHandler(CHArchTrapFrame *Frame)
Index.PDPTEIndex,
Index.PDEIndex,
Index.PTEIndex);
#if defined(a64)
Memory::PageMapLevel4 PML4 = ((Memory::PageTable4 *)CPU::x64::readcr3().raw)->Entries[Index.PMLIndex];
#elif defined(a32)
Memory::PageMapLevel4 PML4 = ((Memory::PageTable4 *)CPU::x32::readcr3().raw)->Entries[Index.PMLIndex];
#elif defined(aa64)
#endif
Memory::PageDirectoryPointerTableEntryPtr *PDPTE = (Memory::PageDirectoryPointerTableEntryPtr *)((uintptr_t)PML4.GetAddress() << 12);
Memory::PageDirectoryEntryPtr *PDE = (Memory::PageDirectoryEntryPtr *)((uintptr_t)PDPTE->Entries[Index.PDPTEIndex].GetAddress() << 12);

52
Core/Crash/CrashHandler.cpp
View File

@ -13,13 +13,13 @@
#include <cpu.hpp>
#include <io.h>
#if defined(__amd64__)
#if defined(a64)
#include "../../Architecture/amd64/cpu/gdt.hpp"
#include "../Architecture/amd64/cpu/apic.hpp"
#elif defined(__i386__)
#elif defined(a32)
#include "../../Architecture/i686/cpu/gdt.hpp"
#include "../Architecture/i686/cpu/apic.hpp"
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
#include "../../kernel.h"
@ -386,11 +386,11 @@ namespace CrashHandler
continue;
EHPrint("\n\e2565CC%p", EHIntFrames[i]);
EHPrint("\e7925CC-");
#if defined(__amd64__)
#if defined(a64)
if ((uintptr_t)EHIntFrames[i] >= 0xFFFFFFFF80000000 && (uintptr_t)EHIntFrames[i] <= (uintptr_t)&_kernel_end)
#elif defined(__i386__)
#elif defined(a32)
if ((uintptr_t)EHIntFrames[i] >= 0xC0000000 && (uintptr_t)EHIntFrames[i] <= (uintptr_t)&_kernel_end)
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
EHPrint("\e25CCC9%s", KernelSymbolTable->GetSymbolFromAddress((uintptr_t)EHIntFrames[i]));
else
@ -543,20 +543,50 @@ namespace CrashHandler
switch (cr[0])
{
case '0':
{
#if defined(a64)
EHPrint("\e44AA000: %#lx\n", CPU::x64::readcr0());
#elif defined(a32)
EHPrint("\e44AA000: %#lx\n", CPU::x32::readcr0());
#endif
break;
}
case '2':
{
#if defined(a64)
EHPrint("\e44AA002: %#lx\n", PageFaultAddress);
#elif defined(a32)
EHPrint("\e44AA002: %#lx\n", CPU::x32::readcr2());
#endif
break;
}
case '3':
{
#if defined(a64)
EHPrint("\e44AA003: %#lx\n", CPU::x64::readcr3());
#elif defined(a32)
EHPrint("\e44AA003: %#lx\n", CPU::x32::readcr3());
#endif
break;
}
case '4':
{
#if defined(a64)
EHPrint("\e44AA004: %#lx\n", CPU::x64::readcr4());
#elif defined(a32)
EHPrint("\e44AA004: %#lx\n", CPU::x32::readcr4());
#endif
break;
}
case '8':
{
#if defined(a64)
EHPrint("\e44AA008: %#lx\n", CPU::x64::readcr8());
#elif defined(a32)
EHPrint("\e44AA008: %#lx\n", CPU::x32::readcr8());
#endif
break;
}
default:
EHPrint("\eFF0000Invalid CR\n");
break;
@ -723,7 +753,7 @@ namespace CrashHandler
SafeFunction void StopAllCores()
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
/* FIXME: Can't send IPIs to other cores
* because it causes another exception on
* the other cores.
@ -751,7 +781,7 @@ namespace CrashHandler
__sync;
CPU::Interrupts(CPU::Disable);
// }
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
}
@ -761,7 +791,7 @@ namespace CrashHandler
CPU::Interrupts(CPU::Disable);
SBIdx = 255;
CHArchTrapFrame *Frame = (CHArchTrapFrame *)Data;
#if defined(__amd64__)
#if defined(a64)
error("An exception occurred!");
error("Exception: %#llx", Frame->InterruptNumber);
for (size_t i = 0; i < INT_FRAMES_MAX; i++)
@ -998,8 +1028,8 @@ namespace CrashHandler
}
goto CrashEnd;
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
CrashEnd:

14
Core/Crash/KBDrv.cpp
View File

@ -9,10 +9,10 @@
#include <cpu.hpp>
#include <io.h>
#if defined(__amd64__)
#if defined(a64)
#include "../../Architecture/amd64/cpu/gdt.hpp"
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
#include "../../kernel.h"
@ -102,11 +102,11 @@ namespace CrashHandler
int BackSpaceLimit = 0;
static char UserInputBuffer[1024];
#if defined(__amd64__)
#if defined(a64)
SafeFunction void CrashKeyboardDriver::OnInterruptReceived(CPU::x64::TrapFrame *Frame)
#elif defined(__i386__)
SafeFunction void CrashKeyboardDriver::OnInterruptReceived(void *Frame)
#elif defined(__aarch64__)
#elif defined(a32)
SafeFunction void CrashKeyboardDriver::OnInterruptReceived(CPU::x32::TrapFrame *Frame)
#elif defined(aa64)
SafeFunction void CrashKeyboardDriver::OnInterruptReceived(void *Frame)
#endif
{

42
Core/Crash/SFrame.cpp
View File

@ -7,10 +7,10 @@
#include <smp.hpp>
#include <cpu.hpp>
#if defined(__amd64__)
#if defined(a64)
#include "../../Architecture/amd64/cpu/gdt.hpp"
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
#include "../../kernel.h"
@ -31,20 +31,20 @@ namespace CrashHandler
return;
}
#if defined(__amd64__)
#if defined(a64)
struct StackFrame *frames = (struct StackFrame *)Frame->rbp; // (struct StackFrame *)__builtin_frame_address(0);
if (!Memory::Virtual().Check((void *)Frame->rbp))
#elif defined(__i386__)
#elif defined(a32)
struct StackFrame *frames = (struct StackFrame *)Frame->ebp; // (struct StackFrame *)__builtin_frame_address(0);
if (!Memory::Virtual().Check((void *)Frame->ebp))
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
{
#if defined(__amd64__)
#if defined(a64)
EHPrint("Invalid rbp pointer: %p\n", Frame->rbp);
#elif defined(__i386__)
#elif defined(a32)
EHPrint("Invalid ebp pointer: %p\n", Frame->ebp);
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
return;
}
@ -59,39 +59,39 @@ namespace CrashHandler
EHPrint("\e7981FC\nStack Trace:\n");
if (!frames || !frames->rip || !frames->rbp)
{
#if defined(__amd64__)
#if defined(a64)
EHPrint("\e2565CC%p", (void *)Frame->rip);
#elif defined(__i386__)
#elif defined(a32)
EHPrint("\e2565CC%p", (void *)Frame->eip);
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
EHPrint("\e7925CC-");
#if defined(__amd64__)
#if defined(a64)
EHPrint("\eAA25CC%s", SymHandle->GetSymbolFromAddress(Frame->rip));
#elif defined(__i386__)
#elif defined(a32)
EHPrint("\eAA25CC%s", SymHandle->GetSymbolFromAddress(Frame->eip));
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
EHPrint("\e7981FC <- Exception");
EHPrint("\eFF0000\n< No stack trace available. >\n");
}
else
{
#if defined(__amd64__)
#if defined(a64)
EHPrint("\e2565CC%p", (void *)Frame->rip);
EHPrint("\e7925CC-");
if ((Frame->rip >= 0xFFFFFFFF80000000 && Frame->rip <= (uintptr_t)&_kernel_end) || !Kernel)
EHPrint("\eAA25CC%s", SymHandle->GetSymbolFromAddress(Frame->rip));
else
EHPrint("Outside Kernel");
#elif defined(__i386__)
#elif defined(a32)
EHPrint("\e2565CC%p", (void *)Frame->eip);
EHPrint("\e7925CC-");
if ((Frame->eip >= 0xC0000000 && Frame->eip <= (uintptr_t)&_kernel_end) || !Kernel)
EHPrint("\eAA25CC%s", SymHandle->GetSymbolFromAddress(Frame->eip));
else
EHPrint("Outside Kernel");
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
EHPrint("\e7981FC <- Exception");
for (int frame = 0; frame < Count; ++frame)
@ -100,11 +100,11 @@ namespace CrashHandler
break;
EHPrint("\n\e2565CC%p", (void *)frames->rip);
EHPrint("\e7925CC-");
#if defined(__amd64__)
#if defined(a64)
if ((frames->rip >= 0xFFFFFFFF80000000 && frames->rip <= (uintptr_t)&_kernel_end) || !Kernel)
#elif defined(__i386__)
#elif defined(a32)
if ((frames->rip >= 0xC0000000 && frames->rip <= (uintptr_t)&_kernel_end) || !Kernel)
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
EHPrint("\e25CCC9%s", SymHandle->GetSymbolFromAddress(frames->rip));
else

6
Core/Crash/Screens/Console.cpp
View File

@ -7,10 +7,10 @@
#include <smp.hpp>
#include <cpu.hpp>
#if defined(__amd64__)
#if defined(a64)
#include "../../../Architecture/amd64/cpu/gdt.hpp"
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
#include "../../../kernel.h"

33
Core/Crash/Screens/Details.cpp
View File

@ -7,10 +7,10 @@
#include <smp.hpp>
#include <cpu.hpp>
#if defined(__amd64__)
#if defined(a64)
#include "../../../Architecture/amd64/cpu/gdt.hpp"
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
#include "../../../kernel.h"
@ -29,7 +29,7 @@ namespace CrashHandler
data.Thread->ID);
EHPrint("\e7981FCTechnical Informations on CPU %lld:\n", data.ID);
uintptr_t ds;
#if defined(__amd64__)
#if defined(a64)
CPUData *cpu = (CPUData *)data.CPUData;
if (cpu)
@ -45,26 +45,29 @@ namespace CrashHandler
asmv("mov %%ds, %0"
: "=r"(ds));
#elif defined(__i386__)
#elif defined(a32)
asmv("mov %%ds, %0"
: "=r"(ds));
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
#if defined(a64)
EHPrint("\e7981FCFS=%#llx GS=%#llx SS=%#llx CS=%#llx DS=%#llx\n",
CPU::x64::rdmsr(CPU::x64::MSR_FS_BASE), CPU::x64::rdmsr(CPU::x64::MSR_GS_BASE),
data.Frame->ss, data.Frame->cs, ds);
#if defined(__amd64__)
EHPrint("R8=%#llx R9=%#llx R10=%#llx R11=%#llx\n", data.Frame->r8, data.Frame->r9, data.Frame->r10, data.Frame->r11);
EHPrint("R12=%#llx R13=%#llx R14=%#llx R15=%#llx\n", data.Frame->r12, data.Frame->r13, data.Frame->r14, data.Frame->r15);
EHPrint("RAX=%#llx RBX=%#llx RCX=%#llx RDX=%#llx\n", data.Frame->rax, data.Frame->rbx, data.Frame->rcx, data.Frame->rdx);
EHPrint("RSI=%#llx RDI=%#llx RBP=%#llx RSP=%#llx\n", data.Frame->rsi, data.Frame->rdi, data.Frame->rbp, data.Frame->rsp);
EHPrint("RIP=%#llx RFL=%#llx INT=%#llx ERR=%#llx EFER=%#llx\n", data.Frame->rip, data.Frame->rflags.raw, data.Frame->InterruptNumber, data.Frame->ErrorCode, data.efer.raw);
#elif defined(__i386__)
#elif defined(a32)
EHPrint("\e7981FCFS=%#llx GS=%#llx SS=%#llx CS=%#llx DS=%#llx\n",
CPU::x32::rdmsr(CPU::x32::MSR_FS_BASE), CPU::x32::rdmsr(CPU::x32::MSR_GS_BASE),
data.Frame->ss, data.Frame->cs, ds);
EHPrint("EAX=%#llx EBX=%#llx ECX=%#llx EDX=%#llx\n", data.Frame->eax, data.Frame->ebx, data.Frame->ecx, data.Frame->edx);
EHPrint("ESI=%#llx EDI=%#llx EBP=%#llx ESP=%#llx\n", data.Frame->esi, data.Frame->edi, data.Frame->ebp, data.Frame->esp);
EHPrint("EIP=%#llx EFL=%#llx INT=%#llx ERR=%#llx EFER=%#llx\n", data.Frame->eip, data.Frame->eflags.raw, data.Frame->InterruptNumber, data.Frame->ErrorCode, data.efer.raw);
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
EHPrint("CR0=%#llx CR2=%#llx CR3=%#llx CR4=%#llx CR8=%#llx\n", data.cr0.raw, data.cr2.raw, data.cr3.raw, data.cr4.raw, data.cr8.raw);
EHPrint("DR0=%#llx DR1=%#llx DR2=%#llx DR3=%#llx DR6=%#llx DR7=%#llx\n", data.dr0, data.dr1, data.dr2, data.dr3, data.dr6, data.dr7.raw);
@ -87,16 +90,16 @@ namespace CrashHandler
data.cr4.PCE ? "True " : "False", data.cr4.UMIP ? "True " : "False", data.cr4.OSFXSR ? "True " : "False", data.cr4.OSXMMEXCPT ? "True " : "False",
data.cr4.LA57 ? "True " : "False", data.cr4.VMXE ? "True " : "False", data.cr4.SMXE ? "True " : "False", data.cr4.PCIDE ? "True " : "False",
data.cr4.OSXSAVE ? "True " : "False", data.cr4.SMEP ? "True " : "False", data.cr4.SMAP ? "True " : "False", data.cr4.PKE ? "True " : "False",
#if defined(__amd64__)
#if defined(a64)
data.cr4.Reserved0, data.cr4.Reserved1, data.cr4.Reserved2);
#elif defined(__i386__)
#elif defined(a32)
data.cr4.Reserved0, data.cr4.Reserved1, 0);
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
EHPrint("\e79FCF5CR8: TPL:%d\n", data.cr8.TPL);
#if defined(__amd64__)
#if defined(a64)
EHPrint("\eFCFC02RFL: CF:%s PF:%s AF:%s ZF:%s\n SF:%s TF:%s IF:%s DF:%s\n OF:%s IOPL:%s NT:%s RF:%s\n VM:%s AC:%s VIF:%s VIP:%s\n ID:%s AlwaysOne:%d\n R0:%#x R1:%#x R2:%#x R3:%#x\n",
data.Frame->rflags.CF ? "True " : "False", data.Frame->rflags.PF ? "True " : "False", data.Frame->rflags.AF ? "True " : "False", data.Frame->rflags.ZF ? "True " : "False",
data.Frame->rflags.SF ? "True " : "False", data.Frame->rflags.TF ? "True " : "False", data.Frame->rflags.IF ? "True " : "False", data.Frame->rflags.DF ? "True " : "False",
@ -104,7 +107,7 @@ namespace CrashHandler
data.Frame->rflags.VM ? "True " : "False", data.Frame->rflags.AC ? "True " : "False", data.Frame->rflags.VIF ? "True " : "False", data.Frame->rflags.VIP ? "True " : "False",
data.Frame->rflags.ID ? "True " : "False", data.Frame->rflags.AlwaysOne,
data.Frame->rflags.Reserved0, data.Frame->rflags.Reserved1, data.Frame->rflags.Reserved2, data.Frame->rflags.Reserved3);
#elif defined(__i386__)
#elif defined(a32)
EHPrint("\eFCFC02EFL: CF:%s PF:%s AF:%s ZF:%s\n SF:%s TF:%s IF:%s DF:%s\n OF:%s IOPL:%s NT:%s RF:%s\n VM:%s AC:%s VIF:%s VIP:%s\n ID:%s AlwaysOne:%d\n R0:%#x R1:%#x R2:%#x\n",
data.Frame->eflags.CF ? "True " : "False", data.Frame->eflags.PF ? "True " : "False", data.Frame->eflags.AF ? "True " : "False", data.Frame->eflags.ZF ? "True " : "False",
data.Frame->eflags.SF ? "True " : "False", data.Frame->eflags.TF ? "True " : "False", data.Frame->eflags.IF ? "True " : "False", data.Frame->eflags.DF ? "True " : "False",
@ -112,7 +115,7 @@ namespace CrashHandler
data.Frame->eflags.VM ? "True " : "False", data.Frame->eflags.AC ? "True " : "False", data.Frame->eflags.VIF ? "True " : "False", data.Frame->eflags.VIP ? "True " : "False",
data.Frame->eflags.ID ? "True " : "False", data.Frame->eflags.AlwaysOne,
data.Frame->eflags.Reserved0, data.Frame->eflags.Reserved1, data.Frame->eflags.Reserved2);
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
EHPrint("\eA0F0F0DR7: LDR0:%s GDR0:%s LDR1:%s GDR1:%s\n LDR2:%s GDR2:%s LDR3:%s GDR3:%s\n CDR0:%s SDR0:%s CDR1:%s SDR1:%s\n CDR2:%s SDR2:%s CDR3:%s SDR3:%s\n R:%#x\n",

18
Core/Crash/Screens/Main.cpp
View File

@ -7,10 +7,10 @@
#include <smp.hpp>
#include <cpu.hpp>
#if defined(__amd64__)
#if defined(a64)
#include "../../../Architecture/amd64/cpu/gdt.hpp"
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
#include "../../../kernel.h"
@ -269,11 +269,11 @@ namespace CrashHandler
EHPrint("The processor attempted to access a page that is not present.\n");
CPU::x64::PageFaultErrorCode params = {.raw = (uint32_t)Frame->ErrorCode};
#if defined(__amd64__)
#if defined(a64)
EHPrint("At \e8888FF%#lx \eFAFAFAby \e8888FF%#lx\eFAFAFA\n", PageFaultAddress, Frame->rip);
#elif defined(__i386__)
#elif defined(a32)
EHPrint("At \e8888FF%#lx \eFAFAFAby \e8888FF%#lx\eFAFAFA\n", PageFaultAddress, Frame->eip);
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
EHPrint("Page: %s\eFAFAFA\n", params.P ? "\e058C19Present" : "\eE85230Not Present");
EHPrint("Write Operation: \e8888FF%s\eFAFAFA\n", params.W ? "Read-Only" : "Read-Write");
@ -335,11 +335,11 @@ namespace CrashHandler
}
}
#if defined(__amd64__)
#if defined(a64)
EHPrint("The exception happened at \e8888FF%#lx\eFAFAFA\n", Frame->rip);
#elif defined(__i386__)
#elif defined(a32)
EHPrint("The exception happened at \e8888FF%#lx\eFAFAFA\n", Frame->eip);
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
}
}

12
Core/Crash/Screens/StackFrame.cpp
View File

@ -8,10 +8,10 @@
#include <smp.hpp>
#include <cpu.hpp>
#if defined(__amd64__)
#if defined(a64)
#include "../../../Architecture/amd64/cpu/gdt.hpp"
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
#include "../../../kernel.h"
@ -40,11 +40,11 @@ namespace CrashHandler
continue;
EHPrint("\n\e2565CC%p", EHIntFrames[i]);
EHPrint("\e7925CC-");
#if defined(__amd64__)
#if defined(a64)
if ((uintptr_t)EHIntFrames[i] >= 0xFFFFFFFF80000000 && (uintptr_t)EHIntFrames[i] <= (uintptr_t)&_kernel_end)
#elif defined(__i386__)
#elif defined(a32)
if ((uintptr_t)EHIntFrames[i] >= 0xC0000000 && (uintptr_t)EHIntFrames[i] <= (uintptr_t)&_kernel_end)
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
EHPrint("\e25CCC9%s", KernelSymbolTable->GetSymbolFromAddress((uintptr_t)EHIntFrames[i]));
else

12
Core/Crash/Screens/Tasks.cpp
View File

@ -7,10 +7,10 @@
#include <smp.hpp>
#include <cpu.hpp>
#if defined(__amd64__)
#if defined(a64)
#include "../../../Architecture/amd64/cpu/gdt.hpp"
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
#include "../../../kernel.h"
@ -44,11 +44,11 @@ namespace CrashHandler
if (TaskManager)
{
if (data.Thread)
#if defined(__amd64__)
#if defined(a64)
EHPrint("\eFAFAFACrash occurred in thread \eAA0F0F%s\eFAFAFA(%ld) at \e00AAAA%#lx\n", data.Thread->Name, data.Thread->ID, data.Frame->rip);
#elif defined(__i386__)
#elif defined(a32)
EHPrint("\eFAFAFACrash occurred in thread \eAA0F0F%s\eFAFAFA(%ld) at \e00AAAA%#lx\n", data.Thread->Name, data.Thread->ID, data.Frame->eip);
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
EHPrint("\eFAFAFAProcess list (%ld):\n", Plist.size());

54
Core/Crash/UserHandler.cpp
View File

@ -7,10 +7,10 @@
#include <smp.hpp>
#include <cpu.hpp>
#if defined(__amd64__)
#if defined(a64)
#include "../../Architecture/amd64/cpu/gdt.hpp"
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
#include "../../kernel.h"
@ -34,6 +34,7 @@ SafeFunction void UserModeExceptionHandler(CHArchTrapFrame *Frame)
CPUData *CurCPU = GetCurrentCPU();
{
#if defined(a64)
CPU::x64::CR0 cr0 = CPU::x64::readcr0();
CPU::x64::CR2 cr2 = CPU::x64::CR2{.PFLA = CrashHandler::PageFaultAddress};
CPU::x64::CR3 cr3 = CPU::x64::readcr3();
@ -44,28 +45,41 @@ SafeFunction void UserModeExceptionHandler(CHArchTrapFrame *Frame)
error("Technical Informations on CPU %lld:", CurCPU->ID);
uintptr_t ds;
#if defined(__amd64__)
asmv("mov %%ds, %0"
: "=r"(ds));
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::CR0 cr0 = CPU::x32::readcr0();
CPU::x32::CR2 cr2 = CPU::x32::CR2{.PFLA = CrashHandler::PageFaultAddress};
CPU::x32::CR3 cr3 = CPU::x32::readcr3();
CPU::x32::CR4 cr4 = CPU::x32::readcr4();
CPU::x32::CR8 cr8 = CPU::x32::readcr8();
CPU::x32::EFER efer;
efer.raw = CPU::x32::rdmsr(CPU::x32::MSR_EFER);
error("Technical Informations on CPU %lld:", CurCPU->ID);
uintptr_t ds;
asmv("mov %%ds, %0"
: "=r"(ds));
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
#if defined(a64)
error("FS=%#llx GS=%#llx SS=%#llx CS=%#llx DS=%#llx",
CPU::x64::rdmsr(CPU::x64::MSR_FS_BASE), CPU::x64::rdmsr(CPU::x64::MSR_GS_BASE),
Frame->ss, Frame->cs, ds);
#if defined(__amd64__)
error("R8=%#llx R9=%#llx R10=%#llx R11=%#llx", Frame->r8, Frame->r9, Frame->r10, Frame->r11);
error("R12=%#llx R13=%#llx R14=%#llx R15=%#llx", Frame->r12, Frame->r13, Frame->r14, Frame->r15);
error("RAX=%#llx RBX=%#llx RCX=%#llx RDX=%#llx", Frame->rax, Frame->rbx, Frame->rcx, Frame->rdx);
error("RSI=%#llx RDI=%#llx RBP=%#llx RSP=%#llx", Frame->rsi, Frame->rdi, Frame->rbp, Frame->rsp);
error("RIP=%#llx RFL=%#llx INT=%#llx ERR=%#llx EFER=%#llx", Frame->rip, Frame->rflags.raw, Frame->InterruptNumber, Frame->ErrorCode, efer.raw);
#elif defined(__i386__)
#elif defined(a32)
error("FS=%#llx GS=%#llx SS=%#llx CS=%#llx DS=%#llx",
CPU::x32::rdmsr(CPU::x32::MSR_FS_BASE), CPU::x32::rdmsr(CPU::x32::MSR_GS_BASE),
Frame->ss, Frame->cs, ds);
error("EAX=%#llx EBX=%#llx ECX=%#llx EDX=%#llx", Frame->eax, Frame->ebx, Frame->ecx, Frame->edx);
error("ESI=%#llx EDI=%#llx EBP=%#llx ESP=%#llx", Frame->esi, Frame->edi, Frame->ebp, Frame->esp);
error("EIP=%#llx EFL=%#llx INT=%#llx ERR=%#llx EFER=%#llx", Frame->eip, Frame->eflags.raw, Frame->InterruptNumber, Frame->ErrorCode, efer.raw);
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
error("CR0=%#llx CR2=%#llx CR3=%#llx CR4=%#llx CR8=%#llx", cr0.raw, cr2.raw, cr3.raw, cr4.raw, cr8.raw);
@ -81,6 +95,7 @@ SafeFunction void UserModeExceptionHandler(CHArchTrapFrame *Frame)
error("CR3: PWT:%s PCD:%s PDBR:%#llx",
cr3.PWT ? "True " : "False", cr3.PCD ? "True " : "False", cr3.PDBR);
#if defined(a64)
error("CR4: VME:%s PVI:%s TSD:%s DE:%s PSE:%s PAE:%s MCE:%s PGE:%s PCE:%s UMIP:%s OSFXSR:%s OSXMMEXCPT:%s LA57:%s VMXE:%s SMXE:%s PCIDE:%s OSXSAVE:%s SMEP:%s SMAP:%s PKE:%s R0:%#x R1:%#x R2:%#x",
cr4.VME ? "True " : "False", cr4.PVI ? "True " : "False", cr4.TSD ? "True " : "False", cr4.DE ? "True " : "False",
cr4.PSE ? "True " : "False", cr4.PAE ? "True " : "False", cr4.MCE ? "True " : "False", cr4.PGE ? "True " : "False",
@ -88,10 +103,19 @@ SafeFunction void UserModeExceptionHandler(CHArchTrapFrame *Frame)
cr4.LA57 ? "True " : "False", cr4.VMXE ? "True " : "False", cr4.SMXE ? "True " : "False", cr4.PCIDE ? "True " : "False",
cr4.OSXSAVE ? "True " : "False", cr4.SMEP ? "True " : "False", cr4.SMAP ? "True " : "False", cr4.PKE ? "True " : "False",
cr4.Reserved0, cr4.Reserved1, cr4.Reserved2);
#elif defined(a32)
error("CR4: VME:%s PVI:%s TSD:%s DE:%s PSE:%s PAE:%s MCE:%s PGE:%s PCE:%s UMIP:%s OSFXSR:%s OSXMMEXCPT:%s LA57:%s VMXE:%s SMXE:%s PCIDE:%s OSXSAVE:%s SMEP:%s SMAP:%s PKE:%s R0:%#x R1:%#x",
cr4.VME ? "True " : "False", cr4.PVI ? "True " : "False", cr4.TSD ? "True " : "False", cr4.DE ? "True " : "False",
cr4.PSE ? "True " : "False", cr4.PAE ? "True " : "False", cr4.MCE ? "True " : "False", cr4.PGE ? "True " : "False",
cr4.PCE ? "True " : "False", cr4.UMIP ? "True " : "False", cr4.OSFXSR ? "True " : "False", cr4.OSXMMEXCPT ? "True " : "False",
cr4.LA57 ? "True " : "False", cr4.VMXE ? "True " : "False", cr4.SMXE ? "True " : "False", cr4.PCIDE ? "True " : "False",
cr4.OSXSAVE ? "True " : "False", cr4.SMEP ? "True " : "False", cr4.SMAP ? "True " : "False", cr4.PKE ? "True " : "False",
cr4.Reserved0, cr4.Reserved1);
#endif
error("CR8: TPL:%d", cr8.TPL);
#if defined(__amd64__)
#if defined(a64)
error("RFL: CF:%s PF:%s AF:%s ZF:%s SF:%s TF:%s IF:%s DF:%s OF:%s IOPL:%s NT:%s RF:%s VM:%s AC:%s VIF:%s VIP:%s ID:%s AlwaysOne:%d R0:%#x R1:%#x R2:%#x R3:%#x",
Frame->rflags.CF ? "True " : "False", Frame->rflags.PF ? "True " : "False", Frame->rflags.AF ? "True " : "False", Frame->rflags.ZF ? "True " : "False",
Frame->rflags.SF ? "True " : "False", Frame->rflags.TF ? "True " : "False", Frame->rflags.IF ? "True " : "False", Frame->rflags.DF ? "True " : "False",
@ -99,7 +123,7 @@ SafeFunction void UserModeExceptionHandler(CHArchTrapFrame *Frame)
Frame->rflags.VM ? "True " : "False", Frame->rflags.AC ? "True " : "False", Frame->rflags.VIF ? "True " : "False", Frame->rflags.VIP ? "True " : "False",
Frame->rflags.ID ? "True " : "False", Frame->rflags.AlwaysOne,
Frame->rflags.Reserved0, Frame->rflags.Reserved1, Frame->rflags.Reserved2, Frame->rflags.Reserved3);
#elif defined(__i386__)
#elif defined(a32)
error("EFL: CF:%s PF:%s AF:%s ZF:%s SF:%s TF:%s IF:%s DF:%s OF:%s IOPL:%s NT:%s RF:%s VM:%s AC:%s VIF:%s VIP:%s ID:%s AlwaysOne:%d R0:%#x R1:%#x R2:%#x",
Frame->eflags.CF ? "True " : "False", Frame->eflags.PF ? "True " : "False", Frame->eflags.AF ? "True " : "False", Frame->eflags.ZF ? "True " : "False",
Frame->eflags.SF ? "True " : "False", Frame->eflags.TF ? "True " : "False", Frame->eflags.IF ? "True " : "False", Frame->eflags.DF ? "True " : "False",
@ -107,7 +131,7 @@ SafeFunction void UserModeExceptionHandler(CHArchTrapFrame *Frame)
Frame->eflags.VM ? "True " : "False", Frame->eflags.AC ? "True " : "False", Frame->eflags.VIF ? "True " : "False", Frame->eflags.VIP ? "True " : "False",
Frame->eflags.ID ? "True " : "False", Frame->eflags.AlwaysOne,
Frame->eflags.Reserved0, Frame->eflags.Reserved1, Frame->eflags.Reserved2);
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
error("EFER: SCE:%s LME:%s LMA:%s NXE:%s SVME:%s LMSLE:%s FFXSR:%s TCE:%s R0:%#x R1:%#x R2:%#x",
@ -178,15 +202,15 @@ SafeFunction void UserModeExceptionHandler(CHArchTrapFrame *Frame)
{
uintptr_t CheckPageFaultAddress = 0;
CPU::x64::PageFaultErrorCode params = {.raw = (uint32_t)Frame->ErrorCode};
#if defined(__amd64__)
#if defined(a64)
CheckPageFaultAddress = CrashHandler::PageFaultAddress;
if (CheckPageFaultAddress == 0)
CheckPageFaultAddress = Frame->rip;
error("An exception occurred at %#lx by %#lx", CrashHandler::PageFaultAddress, Frame->rip);
#elif defined(__i386__)
#elif defined(a32)
error("An exception occurred at %#lx by %#lx", CrashHandler::PageFaultAddress, Frame->eip);
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
error("Page: %s", params.P ? "Present" : "Not Present");
error("Write Operation: %s", params.W ? "Read-Only" : "Read-Write");

14
Core/Crash/chfcts.hpp
View File

@ -7,7 +7,7 @@
#include <task.hpp>
#include <cpu.hpp>
#if defined(__amd64__)
#if defined(a64)
typedef struct CPU::x64::TrapFrame CHArchTrapFrame;
struct CRData
@ -29,7 +29,7 @@ struct CRData
Tasking::TCB *Thread;
};
#elif defined(__i386__)
#elif defined(a32)
typedef struct CPU::x32::TrapFrame CHArchTrapFrame;
struct CRData
@ -49,7 +49,7 @@ struct CRData
Tasking::PCB *Process;
Tasking::TCB *Thread;
};
#elif defined(__aarch64__)
#elif defined(aa64)
typedef struct CPU::aarch64::TrapFrame CHArchTrapFrame;
#endif
@ -244,11 +244,11 @@ namespace CrashHandler
class CrashKeyboardDriver : public Interrupts::Handler
{
private:
#if defined(__amd64__)
#if defined(a64)
void OnInterruptReceived(CPU::x64::TrapFrame *Frame);
#elif defined(__i386__)
void OnInterruptReceived(void *Frame);
#elif defined(__aarch64__)
#elif defined(a32)
void OnInterruptReceived(CPU::x32::TrapFrame *Frame);
#elif defined(aa64)
void OnInterruptReceived(void *Frame);
#endif
public:

8
Core/Driver/Driver.cpp
View File

@ -209,11 +209,11 @@ namespace Driver
this->UnloadAllDrivers();
}
#if defined(__amd64__)
#if defined(a64)
SafeFunction void DriverInterruptHook::OnInterruptReceived(CPU::x64::TrapFrame *Frame)
#elif defined(__i386__)
SafeFunction void DriverInterruptHook::OnInterruptReceived(void *Frame)
#elif defined(__aarch64__)
#elif defined(a32)
SafeFunction void DriverInterruptHook::OnInterruptReceived(CPU::x32::TrapFrame *Frame)
#elif defined(aa64)
SafeFunction void DriverInterruptHook::OnInterruptReceived(void *Frame)
#endif
{

44
Core/Interrupts/IntManager.cpp
View File

@ -5,15 +5,15 @@
#include <smp.hpp>
#include <io.h>
#if defined(__amd64__)
#if defined(a64)
#include "../Architecture/amd64/cpu/gdt.hpp"
#include "../Architecture/amd64/cpu/idt.hpp"
#include "../Architecture/amd64/acpi.hpp"
#include "../Architecture/amd64/cpu/apic.hpp"
#elif defined(__i386__)
#elif defined(a32)
#include "../Architecture/i686/cpu/gdt.hpp"
#include "../Architecture/i686/cpu/idt.hpp"
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
#include "../crashhandler.hpp"
@ -30,18 +30,18 @@ namespace Interrupts
};
Vector<Event> RegisteredEvents;
#if defined(__amd64__)
#if defined(a64)
/* APIC::APIC */ void *apic[MAX_CPU];
/* APIC::Timer */ void *apicTimer[MAX_CPU];
#elif defined(__i386__)
#elif defined(a32)
/* APIC::APIC */ void *apic[MAX_CPU];
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
void *InterruptFrames[INT_FRAMES_MAX];
void Initialize(int Core)
{
#if defined(__amd64__)
#if defined(a64)
GlobalDescriptorTable::Init(Core);
InterruptDescriptorTable::Init(Core);
CPUData *CoreData = GetCPU(Core);
@ -60,16 +60,16 @@ namespace Interrupts
debug("Stack for core %d is %#lx (Address: %#lx)", Core, CoreData->Stack, CoreData->Stack - STACK_SIZE);
asmv("movq %0, %%rsp" ::"r"(CoreData->Stack));
InitializeSystemCalls();
#elif defined(__i386__)
#elif defined(a32)
warn("i386 is not supported yet");
#elif defined(__aarch64__)
#elif defined(aa64)
warn("aarch64 is not supported yet");
#endif
}
void Enable(int Core)
{
#if defined(__amd64__)
#if defined(a64)
if (((ACPI::MADT *)PowerManager->GetMADT())->LAPICAddress != nullptr)
{
// TODO: This function is called by SMP too. Do not initialize timers that doesn't support multiple cores.
@ -82,9 +82,9 @@ namespace Interrupts
error("LAPIC not found");
// TODO: PIC
}
#elif defined(__i386__)
#elif defined(a32)
warn("i386 is not supported yet");
#elif defined(__aarch64__)
#elif defined(aa64)
warn("aarch64 is not supported yet");
#endif
}
@ -92,16 +92,16 @@ namespace Interrupts
void InitializeTimer(int Core)
{
// TODO: This function is called by SMP too. Do not initialize timers that doesn't support multiple cores.
#if defined(__amd64__)
#if defined(a64)
if (apic[Core] != nullptr)
apicTimer[Core] = new APIC::Timer((APIC::APIC *)apic[Core]);
else
{
fixme("apic not found");
}
#elif defined(__i386__)
#elif defined(a32)
warn("i386 is not supported yet");
#elif defined(__aarch64__)
#elif defined(aa64)
warn("aarch64 is not supported yet");
#endif
}
@ -113,7 +113,7 @@ namespace Interrupts
extern "C" SafeFunction void MainInterruptHandler(void *Data)
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::TrapFrame *Frame = (CPU::x64::TrapFrame *)Data;
memmove(InterruptFrames + 1, InterruptFrames, sizeof(InterruptFrames) - sizeof(InterruptFrames[0]));
@ -159,9 +159,9 @@ namespace Interrupts
}
// TODO: PIC
}
#elif defined(__i386__)
#elif defined(a32)
void *Frame = Data;
#elif defined(__aarch64__)
#elif defined(aa64)
void *Frame = Data;
#endif
error("HALT HALT HALT HALT HALT HALT HALT HALT HALT");
@ -197,15 +197,15 @@ namespace Interrupts
warn("Event %d not found.", InterruptNumber);
}
#if defined(__amd64__)
#if defined(a64)
void Handler::OnInterruptReceived(CPU::x64::TrapFrame *Frame)
{
trace("Unhandled interrupt IRQ%d", Frame->InterruptNumber - 32);
#elif defined(__i386__)
void Handler::OnInterruptReceived(void *Frame)
#elif defined(a32)
void Handler::OnInterruptReceived(CPU::x32::TrapFrame *Frame)
{
trace("Unhandled interrupt received");
#elif defined(__aarch64__)
#elif defined(aa64)
void Handler::OnInterruptReceived(void *Frame)
{
trace("Unhandled interrupt received");

4
Core/Memory/HeapAllocators/Xalloc/XallocV1.cpp
View File

@ -103,7 +103,7 @@ namespace Xalloc
{
if (this->SMAPUsed)
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asm volatile("stac" ::
: "cc");
#endif
@ -114,7 +114,7 @@ namespace Xalloc
{
if (this->SMAPUsed)
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asm volatile("clac" ::
: "cc");
#endif

10
Core/Memory/Memory.cpp
View File

@ -39,7 +39,7 @@ NIF void tracepagetable(PageTable4 *pt)
{
for (int i = 0; i < 512; i++)
{
#if defined(__amd64__)
#if defined(a64)
if (pt->Entries[i].Present)
debug("Entry %03d: %x %x %x %x %x %x %x %p-%#llx", i,
pt->Entries[i].Present, pt->Entries[i].ReadWrite,
@ -47,8 +47,8 @@ NIF void tracepagetable(PageTable4 *pt)
pt->Entries[i].CacheDisable, pt->Entries[i].Accessed,
pt->Entries[i].ExecuteDisable, pt->Entries[i].Address << 12,
pt->Entries[i]);
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
}
}
@ -232,9 +232,9 @@ NIF void InitializeMemoryManagement(BootInfo *Info)
tracepagetable(UserspaceKernelOnlyPageTable);
#endif
KPT = KernelPageTable;
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("mov %0, %%cr3" ::"r"(KPT));
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("msr ttbr0_el1, %0" ::"r"(KPT));
#endif
debug("Page table updated.");

4
Core/Memory/MemoryManager.cpp
View File

@ -192,7 +192,11 @@ namespace Memory
if (PageTable)
this->PageTable = PageTable;
else
#if defined(a64)
this->PageTable = (PageTable4 *)CPU::x64::readcr3().raw;
#elif defined(a32)
this->PageTable = (PageTable4 *)CPU::x32::readcr3().raw;
#endif
this->Directory = Directory;
debug("+ %#lx", this);

6
Core/Memory/PageMapIndexer.cpp
View File

@ -4,7 +4,7 @@ namespace Memory
{
Virtual::PageMapIndexer::PageMapIndexer(uintptr_t VirtualAddress)
{
#if defined(__amd64__)
#if defined(a64)
uintptr_t Address = VirtualAddress;
Address >>= 12;
this->PTEIndex = Address & 0x1FF;
@ -14,7 +14,7 @@ namespace Memory
this->PDPTEIndex = Address & 0x1FF;
Address >>= 9;
this->PMLIndex = Address & 0x1FF;
#elif defined(__i386__)
#elif defined(a32)
uintptr_t Address = VirtualAddress;
Address >>= 12;
this->PTEIndex = Address & 0x3FF;
@ -22,7 +22,7 @@ namespace Memory
this->PDEIndex = Address & 0x3FF;
Address >>= 10;
this->PDPTEIndex = Address & 0x3FF;
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
}
}

12
Core/Memory/VirtualMemoryManager.cpp
View File

@ -101,11 +101,11 @@ namespace Memory
PTE.SetAddress((uintptr_t)PhysicalAddress >> 12);
PTEPtr->Entries[Index.PTEIndex] = PTE;
#if defined(__amd64__)
#if defined(a64)
CPU::x64::invlpg(VirtualAddress);
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::invlpg(VirtualAddress);
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("dsb sy");
asmv("tlbi vae1is, %0"
:
@ -180,11 +180,11 @@ namespace Memory
PTE.Present = false;
PTEPtr->Entries[Index.PTEIndex] = PTE;
#if defined(__amd64__)
#if defined(a64)
CPU::x64::invlpg(VirtualAddress);
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::invlpg(VirtualAddress);
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("dsb sy");
asmv("tlbi vae1is, %0"
:

12
Core/PeripheralComponentInterconnect.cpp
View File

@ -2,10 +2,10 @@
#include <memory.hpp>
#include <power.hpp>
#if defined(__amd64__)
#if defined(a64)
#include "../Architecture/amd64/acpi.hpp"
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
#include "../kernel.h"
@ -837,7 +837,7 @@ namespace PCI
PCI::PCI()
{
#if defined(__amd64__)
#if defined(a64)
int Entries = ((((ACPI::ACPI *)PowerManager->GetACPI())->MCFG->Header.Length) - sizeof(ACPI::ACPI::MCFGHeader)) / sizeof(DeviceConfig);
for (int t = 0; t < Entries; t++)
{
@ -848,9 +848,9 @@ namespace PCI
for (uintptr_t Bus = NewDeviceConfig->StartBus; Bus < NewDeviceConfig->EndBus; Bus++)
EnumerateBus(NewDeviceConfig->BaseAddress, Bus);
}
#elif defined(__i386__)
#elif defined(a32)
error("PCI not implemented on i386");
#elif defined(__aarch64__)
#elif defined(aa64)
error("PCI not implemented on aarch64");
#endif
}

6
Core/Power.cpp
View File

@ -5,7 +5,7 @@
#include "../kernel.h"
#if defined(__amd64__)
#if defined(a64)
#include <io.h>
#include "../Architecture/amd64/acpi.hpp"
@ -75,7 +75,7 @@ namespace Power
}
}
#elif defined(__i386__)
#elif defined(a32)
namespace Power
{
@ -99,7 +99,7 @@ namespace Power
}
}
#elif defined(__aarch64__)
#elif defined(aa64)
namespace Power
{

42
Core/Random.cpp
View File

@ -10,12 +10,12 @@ namespace Random
int RDRANDFlag = 0;
if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::AMD::CPUID0x1 cpuid1amd;
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::AMD::CPUID0x1 cpuid1amd;
#endif
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("cpuid"
: "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw)
: "a"(0x1));
@ -24,12 +24,12 @@ namespace Random
}
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::Intel::CPUID0x1 cpuid1intel;
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::Intel::CPUID0x1 cpuid1intel;
#endif
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("cpuid"
: "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw)
: "a"(0x1));
@ -40,7 +40,7 @@ namespace Random
if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_TCG) == 0)
RDRANDFlag = 0;
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
if (RDRANDFlag)
{
uint16_t RDRANDValue = 0;
@ -59,12 +59,12 @@ namespace Random
int RDRANDFlag = 0;
if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::AMD::CPUID0x1 cpuid1amd;
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::AMD::CPUID0x1 cpuid1amd;
#endif
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("cpuid"
: "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw)
: "a"(0x1));
@ -73,12 +73,12 @@ namespace Random
}
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::Intel::CPUID0x1 cpuid1intel;
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::Intel::CPUID0x1 cpuid1intel;
#endif
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("cpuid"
: "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw)
: "a"(0x1));
@ -89,7 +89,7 @@ namespace Random
if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_TCG) == 0)
RDRANDFlag = 0;
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
if (RDRANDFlag)
{
uint32_t RDRANDValue = 0;
@ -108,12 +108,12 @@ namespace Random
int RDRANDFlag = 0;
if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::AMD::CPUID0x1 cpuid1amd;
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::AMD::CPUID0x1 cpuid1amd;
#endif
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("cpuid"
: "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw)
: "a"(0x1));
@ -122,12 +122,12 @@ namespace Random
}
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::Intel::CPUID0x1 cpuid1intel;
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::Intel::CPUID0x1 cpuid1intel;
#endif
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("cpuid"
: "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw)
: "a"(0x1));
@ -138,7 +138,7 @@ namespace Random
if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_TCG) == 0)
RDRANDFlag = 0;
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
if (RDRANDFlag)
{
uint64_t RDRANDValue = 0;

13
Core/StackGuard.cpp
View File

@ -43,15 +43,20 @@ EXTERNC __attribute__((weak, noreturn, no_stack_protector)) void __stack_chk_fai
debug("Current stack check guard value: %#lx", __stack_chk_guard);
KPrint("\eFF0000Stack smashing detected!");
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
void *Stack = nullptr;
#if defined(a64)
asmv("movq %%rsp, %0"
: "=r"(Stack));
#elif defined(a32)
asmv("movl %%esp, %0"
: "=r"(Stack));
#endif
error("Stack address: %#lx", Stack);
while (1)
asmv("cli; hlt");
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("wfe");
#endif
CPU::Stop();
@ -65,10 +70,10 @@ EXTERNC __attribute__((weak, noreturn, no_stack_protector)) void __chk_fail(void
error("Buffer overflow detected!");
KPrint("\eFF0000Buffer overflow detected!");
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
while (1)
asmv("cli; hlt");
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("wfe");
#endif
}

4
Core/Time.cpp
View File

@ -7,7 +7,7 @@ namespace Time
Clock ReadClock()
{
Clock tm;
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
uint32_t t = 0;
outb(0x70, 0x00);
t = inb(0x71);
@ -28,7 +28,7 @@ namespace Time
t = inb(0x71);
tm.Year = ((t & 0x0F) + ((t >> 4) * 10));
tm.Counter = 0;
#elif defined(__aarch64__)
#elif defined(aa64)
tm.Year = 0;
tm.Month = 0;
tm.Day = 0;

24
Core/Timer.cpp
View File

@ -4,10 +4,10 @@
#include <debug.h>
#include <io.h>
#if defined(__amd64__)
#if defined(a64)
#include "../Architecture/amd64/acpi.hpp"
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
#include "../kernel.h"
@ -16,7 +16,7 @@ namespace Time
{
void time::Sleep(uint64_t Milliseconds)
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
uint64_t Target = mminq(&((HPET *)hpet)->MainCounterValue) + (Milliseconds * 1000000000000) / clk;
#ifdef DEBUG
uint64_t Counter = mminq(&((HPET *)hpet)->MainCounterValue);
@ -29,23 +29,23 @@ namespace Time
while (mminq(&((HPET *)hpet)->MainCounterValue) < Target)
CPU::Pause();
#endif
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
}
uint64_t time::GetCounter()
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
return mminq(&((HPET *)hpet)->MainCounterValue);
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
}
uint64_t time::CalculateTarget(uint64_t Milliseconds)
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
return mminq(&((HPET *)hpet)->MainCounterValue) + (Milliseconds * 1000000000000) / clk;
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
}
@ -53,7 +53,7 @@ namespace Time
{
if (_acpi)
{
#if defined(__amd64__)
#if defined(a64)
this->acpi = _acpi;
ACPI::ACPI *acpi = (ACPI::ACPI *)this->acpi;
if (acpi->HPET)
@ -76,8 +76,8 @@ namespace Time
KPrint("\eFF2200HPET not found");
CPU::Stop();
}
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
}
}

10
Core/UniversalAsynchronousReceiverTransmitter.cpp
View File

@ -6,7 +6,7 @@
volatile bool serialports[8] = {false, false, false, false, false, false, false, false};
Vector<UniversalAsynchronousReceiverTransmitter::Events *> RegisteredEvents;
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
NIF uint8_t NoProfiler_inportb(uint16_t Port)
{
uint8_t Result;
@ -39,7 +39,7 @@ namespace UniversalAsynchronousReceiverTransmitter
SafeFunction NIF UART::UART(SerialPorts Port)
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
if (Port == COMNULL)
return;
@ -108,7 +108,7 @@ namespace UniversalAsynchronousReceiverTransmitter
SafeFunction NIF void UART::Write(uint8_t Char)
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
while ((NoProfiler_inportb(Port + 5) & SERIAL_BUFFER_EMPTY) == 0)
;
NoProfiler_outportb(Port, Char);
@ -120,7 +120,7 @@ namespace UniversalAsynchronousReceiverTransmitter
SafeFunction NIF uint8_t UART::Read()
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
while ((NoProfiler_inportb(Port + 5) & 1) == 0)
;
return NoProfiler_inportb(Port);
@ -129,7 +129,7 @@ namespace UniversalAsynchronousReceiverTransmitter
{
if (e->GetRegisteredPort() == Port || e->GetRegisteredPort() == COMNULL)
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
e->OnReceived(NoProfiler_inportb(Port));
#endif
}

24
Kernel.cpp
View File

@ -93,23 +93,23 @@
*
*/
#ifdef __amd64__
#ifdef a64
#if UINTPTR_MAX != UINT64_MAX
#error "uintptr_t is not 64-bit!"
#endif // UINTPTR_MAX != UINT64_MAX
#endif // __amd64__
#endif // a64
#ifdef __i386__
#ifdef a32
#if UINTPTR_MAX != UINT32_MAX
#error "uintptr_t is not 32-bit!"
#endif // UINTPTR_MAX != UINT32_MAX
#endif // __i386__
#endif // a32
#ifdef __aarch64__
#ifdef aa64
#if UINTPTR_MAX != UINT64_MAX
#error "uintptr_t is not 64-bit!"
#endif // UINTPTR_MAX != UINT64_MAX
#endif // __aarch64__
#endif // aa64
NewLock(KernelLock);
@ -184,18 +184,18 @@ EXTERNC NIF void Main(BootInfo *Info)
}
KPrint("Enabling Interrupts on Bootstrap Processor");
Interrupts::Enable(0);
#if defined(__amd64__)
#if defined(a64)
PowerManager->InitDSDT();
#elif defined(__i386__)
#elif defined(a32)
// FIXME: Add ACPI support for i386
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
KPrint("Initializing Timers");
#if defined(__amd64__)
#if defined(a64)
TimeManager = new Time::time(PowerManager->GetACPI());
#elif defined(__i386__)
#elif defined(a32)
TimeManager = new Time::time(PowerManager->GetACPI());
#elif defined(__aarch64__)
#elif defined(aa64)
TimeManager = new Time::time(nullptr);
#endif
KPrint("Initializing Bootstrap Processor Timer");

2
Library/Convert.cpp
View File

@ -594,7 +594,7 @@ EXTERNC void __chk_fail(void) __attribute__((__noreturn__));
__noreturn static inline void __convert_chk_fail(void)
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("int3");
#else
#error "Not implemented!"

12
Library/MemoryCopySIMD.cpp
View File

@ -12,6 +12,7 @@ TODO: Replace these functions with even more optimized versions.
EXTERNC void *memcpy_sse(void *dest, const void *src, size_t n)
{
#if defined(a64)
char *d = (char *)dest;
const char *s = (const char *)src;
@ -32,11 +33,13 @@ EXTERNC void *memcpy_sse(void *dest, const void *src, size_t n)
}
memcpy_unsafe(d, s, n);
#endif // defined(a64)
return dest;
}
EXTERNC void *memcpy_sse2(void *dest, const void *src, size_t n)
{
#if defined(a64)
char *d = (char *)dest;
const char *s = (const char *)src;
@ -57,11 +60,13 @@ EXTERNC void *memcpy_sse2(void *dest, const void *src, size_t n)
}
memcpy_unsafe(d, s, n);
#endif // defined(a64)
return dest;
}
EXTERNC void *memcpy_sse3(void *dest, const void *src, size_t n)
{
#if defined(a64)
char *d = (char *)dest;
const char *s = (const char *)src;
@ -83,11 +88,13 @@ EXTERNC void *memcpy_sse3(void *dest, const void *src, size_t n)
}
memcpy_unsafe(d, s, n);
#endif // defined(a64)
return dest;
}
EXTERNC void *memcpy_ssse3(void *dest, const void *src, size_t n)
{
#if defined(a64)
char *d = (char *)dest;
const char *s = (const char *)src;
@ -110,11 +117,13 @@ EXTERNC void *memcpy_ssse3(void *dest, const void *src, size_t n)
}
memcpy_unsafe(d, s, n);
#endif // defined(a64)
return dest;
}
EXTERNC void *memcpy_sse4_1(void *dest, const void *src, size_t n)
{
#if defined(a64)
char *d = (char *)dest;
const char *s = (const char *)src;
@ -136,11 +145,13 @@ EXTERNC void *memcpy_sse4_1(void *dest, const void *src, size_t n)
}
memcpy_unsafe(d, s, n);
#endif // defined(a64)
return dest;
}
EXTERNC void *memcpy_sse4_2(void *dest, const void *src, size_t n)
{
#if defined(a64)
char *d = (char *)dest;
const char *s = (const char *)src;
@ -162,5 +173,6 @@ EXTERNC void *memcpy_sse4_2(void *dest, const void *src, size_t n)
}
memcpy_unsafe(d, s, n);
#endif // defined(a64)
return dest;
}

2
Library/MemorySetSIMD.cpp
View File

@ -39,6 +39,7 @@ EXTERNC void *memset_sse4_1(void *dest, int c, size_t n)
EXTERNC void *memset_sse4_2(void *dest, int c, size_t n)
{
#if defined(a64)
char *d = (char *)dest;
if (((uintptr_t)d & 0xF) == 0)
@ -58,5 +59,6 @@ EXTERNC void *memset_sse4_2(void *dest, int c, size_t n)
}
memset_unsafe(d, c, n);
#endif
return dest;
}

6
Library/md5.c
View File

@ -120,7 +120,7 @@ void md5Finalize(MD5Context *ctx)
unsigned int offset = ctx->size % 64;
unsigned int padding_length = offset < 56 ? 56 - offset : (56 + 64) - offset;
// Fill in the padding andndo the changes to size that resulted from the update
// Fill in the padding and do the changes to size that resulted from the update
md5Update(ctx, PADDING, padding_length);
ctx->size -= (uint64_t)padding_length;
@ -134,7 +134,11 @@ void md5Finalize(MD5Context *ctx)
(uint32_t)(ctx->input[(j * 4)]);
}
input[14] = (uint32_t)(ctx->size * 8);
#ifdef a32
input[15] = (uint32_t)((ctx->size >> 32) | (ctx->size << 32)) >> 32;
#else
input[15] = (uint32_t)((ctx->size * 8) >> 32);
#endif
md5Step(ctx->buffer, input);

30
SystemCalls/Linux.cpp
View File

@ -972,15 +972,39 @@ static uint64_t sys_arch_prctl(int code, unsigned long arg2, unsigned long arg3,
switch (code)
{
case 0x1001: // ARCH_SET_GS
{
#if defined(a64)
CPU::x64::wrmsr(CPU::x64::MSRID::MSR_GS_BASE, arg2);
#elif defined(a32)
CPU::x32::wrmsr(CPU::x32::MSRID::MSR_GS_BASE, arg2);
#endif
return arg2;
}
case 0x1002: // ARCH_SET_FS
{
#if defined(a64)
CPU::x64::wrmsr(CPU::x64::MSRID::MSR_FS_BASE, arg2);
#elif defined(a32)
CPU::x32::wrmsr(CPU::x32::MSRID::MSR_FS_BASE, arg2);
#endif
return arg2;
}
case 0x1003: // ARCH_GET_FS
{
#if defined(a64)
return CPU::x64::rdmsr(CPU::x64::MSRID::MSR_FS_BASE);
#elif defined(a32)
return CPU::x32::rdmsr(CPU::x32::MSRID::MSR_FS_BASE);
#endif
}
case 0x1004: // ARCH_GET_GS
{
#if defined(a64)
return CPU::x64::rdmsr(CPU::x64::MSRID::MSR_GS_BASE);
#elif defined(a32)
return CPU::x32::rdmsr(CPU::x32::MSRID::MSR_GS_BASE);
#endif
}
default:
warn("Unimplemented prctl code %#lx (arg2=%lx, arg3=%lx, arg4=%lx, arg5=%lx)", code, arg2, arg3, arg4, arg5);
return -1; /* EINVAL */
@ -2393,7 +2417,7 @@ static void *LinuxSyscallsTable[] = {
uintptr_t HandleLinuxSyscalls(SyscallsFrame *Frame)
{
#if defined(__amd64__)
#if defined(a64)
if (Frame->rax > sizeof(LinuxSyscallsTable))
{
fixme("Syscall %lld not implemented", Frame->rax);
@ -2409,7 +2433,7 @@ uintptr_t HandleLinuxSyscalls(SyscallsFrame *Frame)
uint64_t ret = call(Frame->rdi, Frame->rsi, Frame->rdx, Frame->r10, Frame->r8, Frame->r9);
Frame->rax = ret;
return ret;
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
}

6
SystemCalls/Native.cpp
View File

@ -276,7 +276,7 @@ static void *NativeSyscallsTable[] = {
uintptr_t HandleNativeSyscalls(SyscallsFrame *Frame)
{
#if defined(__amd64__)
#if defined(a64)
// debug("rax: %#llx, rbx: %#llx, rcx: %#llx, rdx: %#llx, rsi: %#llx, rdi: %#llx, rbp: %#llx, r8: %#llx, r9: %#llx, r10: %#llx, r11: %#llx, r12: %#llx, r13: %#llx, r14: %#llx, r15: %#llx", Frame->rax, Frame->rbx, Frame->rcx, Frame->rdx, Frame->rsi, Frame->rdi, Frame->rbp, Frame->r8, Frame->r9, Frame->r10, Frame->r11, Frame->r12, Frame->r13, Frame->r14, Frame->r15);
if (Frame->rax > sizeof(NativeSyscallsTable))
{
@ -294,7 +294,7 @@ uintptr_t HandleNativeSyscalls(SyscallsFrame *Frame)
uintptr_t ret = call((uintptr_t)Frame, Frame->rdi, Frame->rsi, Frame->rdx, Frame->r10, Frame->r8, Frame->r9);
Frame->rax = ret;
return ret;
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
}

6
SystemCalls/Syscalls.cpp
View File

@ -11,7 +11,7 @@ extern "C" uintptr_t SystemCallsHandler(SyscallsFrame *Frame)
CPU::Interrupts(CPU::Enable);
SmartLock(SyscallsLock); /* TODO: This should be replaced or moved somewhere else. */
#if defined(__amd64__)
#if defined(a64)
switch (TaskManager->GetCurrentThread()->Info.Compatibility)
{
case Tasking::TaskCompatibility::Native:
@ -30,9 +30,9 @@ extern "C" uintptr_t SystemCallsHandler(SyscallsFrame *Frame)
break;
}
}
#elif defined(__i386__)
#elif defined(a32)
fixme("System call %lld", Frame->eax);
#elif defined(__aarch64__)
#elif defined(aa64)
fixme("System call");
#endif
return -1;

20
Tasking/Scheduler.cpp
View File

@ -9,12 +9,12 @@
#include "../kernel.h"
#if defined(__amd64__)
#if defined(a64)
#include "../Architecture/amd64/cpu/apic.hpp"
#include "../Architecture/amd64/cpu/gdt.hpp"
#elif defined(__i386__)
#elif defined(a32)
#include "../Architecture/i686/cpu/apic.hpp"
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
NewLock(SchedulerLock);
@ -94,16 +94,16 @@ extern "C" SafeFunction NIF void TaskingScheduler_OneShot(int TimeSlice)
{
if (TimeSlice == 0)
TimeSlice = Tasking::TaskPriority::Normal;
#if defined(__amd64__)
#if defined(a64)
((APIC::Timer *)Interrupts::apicTimer[GetCurrentCPU()->ID])->OneShot(CPU::x86::IRQ16, TimeSlice);
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
}
namespace Tasking
{
#if defined(__amd64__)
#if defined(a64)
SafeFunction NIF bool Task::FindNewProcess(void *CPUDataPointer)
{
CPUData *CurrentCPU = (CPUData *)CPUDataPointer;
@ -671,7 +671,7 @@ namespace Tasking
}
SafeFunction NIF void Task::OnInterruptReceived(CPU::x64::TrapFrame *Frame) { this->Schedule(Frame); }
#elif defined(__i386__)
#elif defined(a32)
SafeFunction bool Task::FindNewProcess(void *CPUDataPointer)
{
fixme("unimplemented");
@ -702,8 +702,8 @@ namespace Tasking
fixme("unimplemented");
}
SafeFunction void Task::OnInterruptReceived(void *Frame) { this->Schedule(Frame); }
#elif defined(__aarch64__)
SafeFunction void Task::OnInterruptReceived(CPU::x32::TrapFrame *Frame) { this->Schedule(Frame); }
#elif defined(aa64)
SafeFunction bool Task::FindNewProcess(void *CPUDataPointer)
{
fixme("unimplemented");

76
Tasking/Task.cpp
View File

@ -9,12 +9,12 @@
#include "../kernel.h"
#if defined(__amd64__)
#if defined(a64)
#include "../Architecture/amd64/cpu/apic.hpp"
#include "../Architecture/amd64/cpu/gdt.hpp"
#elif defined(__i386__)
#elif defined(a32)
#include "../Architecture/i686/cpu/apic.hpp"
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
// #define DEBUG_TASKING 1
@ -43,11 +43,11 @@ namespace Tasking
__naked __used __no_stack_protector NIF void IdleProcessLoop()
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("IdleLoop:\n"
"hlt\n"
"jmp IdleLoop\n");
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("IdleLoop:\n"
"wfe\n"
"b IdleLoop\n");
@ -394,11 +394,11 @@ namespace Tasking
// : "memory");
// CPU::x64::fxsave(Thread->FPU);
#if defined(__amd64__)
#if defined(a64)
memset(&Thread->Registers, 0, sizeof(CPU::x64::TrapFrame)); // Just in case
Thread->Registers.rip = (EntryPoint + Offset);
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
switch (Parent->Security.TrustLevel)
{
@ -408,7 +408,7 @@ namespace Tasking
case TaskTrustLevel::Kernel:
{
Thread->Stack = new Memory::StackGuard(false, Parent->PageTable);
#if defined(__amd64__)
#if defined(a64)
SecurityManager.TrustToken(Thread->Security.UniqueToken, TTL::TrustedByKernel);
Thread->GSBase = CPU::x64::rdmsr(CPU::x64::MSRID::MSR_GS_BASE);
Thread->FSBase = CPU::x64::rdmsr(CPU::x64::MSRID::MSR_FS_BASE);
@ -419,15 +419,15 @@ namespace Tasking
Thread->Registers.rflags.ID = 1;
Thread->Registers.rsp = ((uintptr_t)Thread->Stack->GetStackTop());
POKE(uintptr_t, Thread->Registers.rsp) = (uintptr_t)ThreadDoExit;
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
break;
}
case TaskTrustLevel::User:
{
Thread->Stack = new Memory::StackGuard(true, Parent->PageTable);
#if defined(__amd64__)
#if defined(a64)
SecurityManager.TrustToken(Thread->Security.UniqueToken, TTL::Untrusted);
Thread->GSBase = 0;
Thread->FSBase = 0;
@ -577,8 +577,8 @@ namespace Tasking
error("Offset is not user accessible");
uva.Map((void *)Offset, (void *)Offset, Memory::PTFlag::RW | Memory::PTFlag::US); // We try one more time.
}
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
#ifdef DEBUG_TASKING
DumpData(Thread->Name, Thread->Stack, STACK_SIZE);
@ -613,19 +613,19 @@ namespace Tasking
Thread->Info.Compatibility = Compatibility;
#ifdef DEBUG
#ifdef __amd64__
#ifdef a64
debug("Thread offset is %#lx (EntryPoint: %#lx) => RIP: %#lx", Thread->Offset, Thread->EntryPoint, Thread->Registers.rip);
if (Parent->Security.TrustLevel == TaskTrustLevel::User)
debug("Thread stack region is %#lx-%#lx (U) and rsp is %#lx", Thread->Stack->GetStackBottom(), Thread->Stack->GetStackTop(), Thread->Registers.rsp);
else
debug("Thread stack region is %#lx-%#lx (K) and rsp is %#lx", Thread->Stack->GetStackBottom(), Thread->Stack->GetStackTop(), Thread->Registers.rsp);
#elif defined(__i386__)
#elif defined(a32)
debug("Thread offset is %#lx (EntryPoint: %#lx) => RIP: %#lx", Thread->Offset, Thread->EntryPoint, Thread->Registers.eip);
if (Parent->Security.TrustLevel == TaskTrustLevel::User)
debug("Thread stack region is %#lx-%#lx (U) and rsp is %#lx", Thread->Stack->GetStackBottom(), Thread->Stack->GetStackTop(), Thread->Registers.esp);
else
debug("Thread stack region is %#lx-%#lx (K) and rsp is %#lx", Thread->Stack->GetStackBottom(), Thread->Stack->GetStackTop(), Thread->Registers.esp);
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
debug("Created thread \"%s\"(%d) in process \"%s\"(%d)",
Thread->Name, Thread->ID,
@ -669,18 +669,18 @@ namespace Tasking
case TaskTrustLevel::Kernel:
{
SecurityManager.TrustToken(Process->Security.UniqueToken, TTL::TrustedByKernel);
#if defined(__amd64__)
#if defined(a64)
if (!DoNotCreatePageTable)
Process->PageTable = (Memory::PageTable4 *)CPU::x64::readcr3().raw;
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
break;
}
case TaskTrustLevel::User:
{
SecurityManager.TrustToken(Process->Security.UniqueToken, TTL::Untrusted);
#if defined(__amd64__)
#if defined(a64)
if (!DoNotCreatePageTable)
{
Process->PageTable = (Memory::PageTable4 *)KernelAllocator.RequestPages(TO_PAGES(PAGE_SIZE));
@ -688,8 +688,8 @@ namespace Tasking
for (size_t i = 0; i < TO_PAGES(PAGE_SIZE); i++)
Memory::Virtual(Process->PageTable).Map((void *)Process->PageTable, (void *)Process->PageTable, Memory::PTFlag::RW); // Make sure the page table is mapped.
}
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
break;
}
@ -740,20 +740,20 @@ namespace Tasking
Task::Task(const IP EntryPoint) : Interrupts::Handler(CPU::x86::IRQ16)
{
SmartCriticalSection(TaskingLock);
#if defined(__amd64__)
#if defined(a64)
// Map the IRQ16 to the first CPU.
((APIC::APIC *)Interrupts::apic[0])->RedirectIRQ(0, CPU::x86::IRQ16 - CPU::x86::IRQ0, 1);
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
KPrint("Starting Tasking With Instruction Pointer: %p (\e666666%s\eCCCCCC)", EntryPoint, KernelSymbolTable->GetSymbolFromAddress(EntryPoint));
TaskingLock.Unlock();
#if defined(__amd64__)
#if defined(a64)
TaskArchitecture Arch = TaskArchitecture::x64;
#elif defined(__i386__)
#elif defined(a32)
TaskArchitecture Arch = TaskArchitecture::x32;
#elif defined(__aarch64__)
#elif defined(aa64)
TaskArchitecture Arch = TaskArchitecture::ARM64;
#endif
PCB *kproc = CreateProcess(nullptr, "Kernel", TaskTrustLevel::Kernel);
@ -765,12 +765,12 @@ namespace Tasking
bool MONITORSupported = false;
if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::AMD::CPUID0x1 cpuid1amd;
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::AMD::CPUID0x1 cpuid1amd;
#endif
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("cpuid"
: "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw)
: "a"(0x1));
@ -779,12 +779,12 @@ namespace Tasking
}
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::Intel::CPUID0x1 cpuid1intel;
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::Intel::CPUID0x1 cpuid1intel;
#endif
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("cpuid"
: "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw)
: "a"(0x1));
@ -817,7 +817,7 @@ namespace Tasking
IdleThread->Info.Affinity[i] = true;
}
debug("Tasking Started");
#if defined(__amd64__)
#if defined(a64)
((APIC::Timer *)Interrupts::apicTimer[0])->OneShot(CPU::x86::IRQ16, 100);
/* FIXME: The kernel is not ready for multi-core tasking. */
@ -829,8 +829,8 @@ namespace Tasking
// icr.Level = APIC::APICLevel::Assert;
// ((APIC::APIC *)Interrupts::apic[0])->IPI(i, icr);
// }
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
}

14
Tests/RandomNumberGenerator.cpp
View File

@ -9,12 +9,12 @@ __constructor void TestRandom()
int RDRANDFlag = 0;
if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::AMD::CPUID0x1 cpuid1amd;
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::AMD::CPUID0x1 cpuid1amd;
#endif
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("cpuid"
: "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw)
: "a"(0x1));
@ -23,12 +23,12 @@ __constructor void TestRandom()
}
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::Intel::CPUID0x1 cpuid1intel;
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::Intel::CPUID0x1 cpuid1intel;
#endif
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("cpuid"
: "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw)
: "a"(0x1));
@ -39,7 +39,7 @@ __constructor void TestRandom()
if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_TCG) == 0)
RDRANDFlag = 0;
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
if (RDRANDFlag)
{
uint64_t RDSEEDValue = 0;

6
include/abi.h
View File

@ -62,11 +62,11 @@ typedef struct
typedef struct
{
#if defined(__amd64__)
#if defined(a64)
Elf64_auxv_t archaux;
#elif defined(__i386__)
#elif defined(a32)
Elf32_auxv_t archaux;
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
} AuxiliaryVector;

30
include/cpu.hpp
View File

@ -119,9 +119,9 @@ namespace CPU
{
do
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("pause");
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("yield");
#endif
} while (Loop);
@ -132,12 +132,12 @@ namespace CPU
*/
SafeFunction __noreturn __naked __used inline void Stop()
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("CPUStopLoop:\n"
"cli\n"
"hlt\n"
"jmp CPUStopLoop");
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("msr daifset, #2");
asmv("wfe");
#endif
@ -150,9 +150,9 @@ namespace CPU
{
do
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("hlt");
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("wfe");
#endif
} while (Loop);
@ -362,7 +362,7 @@ namespace CPU
*/
static inline void cpuid(uint32_t Function, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
{
#if defined(__i386__)
#if defined(a32)
asmv("cpuid"
: "=a"(*eax), "=b"(*ebx), "=c"(*ecx), "=d"(*edx)
: "a"(Function));
@ -377,7 +377,7 @@ namespace CPU
SafeFunction static inline void invlpg(void *Address)
{
#if defined(__i386__)
#if defined(a32)
asmv("invlpg (%0)"
:
: "r"(Address)
@ -650,7 +650,7 @@ namespace CPU
SafeFunction static inline void lgdt(void *gdt)
{
#if defined(__amd64__)
#if defined(a64)
asmv("lgdt (%0)"
:
: "r"(gdt));
@ -659,7 +659,7 @@ namespace CPU
SafeFunction static inline void lidt(void *idt)
{
#if defined(__amd64__)
#if defined(a64)
asmv("lidt (%0)"
:
: "r"(idt));
@ -668,7 +668,7 @@ namespace CPU
SafeFunction static inline void ltr(uint16_t Segment)
{
#if defined(__amd64__)
#if defined(a64)
asmv("ltr %0"
:
: "r"(Segment));
@ -677,7 +677,7 @@ namespace CPU
SafeFunction static inline void invlpg(void *Address)
{
#if defined(__amd64__)
#if defined(a64)
asmv("invlpg (%0)"
:
: "r"(Address)
@ -696,7 +696,7 @@ namespace CPU
*/
SafeFunction static inline void cpuid(uint32_t Function, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
{
#if defined(__amd64__)
#if defined(a64)
asmv("cpuid"
: "=a"(*eax), "=b"(*ebx), "=c"(*ecx), "=d"(*edx)
: "a"(Function));
@ -719,7 +719,7 @@ namespace CPU
SafeFunction static inline void fxsave(void *FXSaveArea)
{
#if defined(__amd64__)
#if defined(a64)
if (!FXSaveArea || FXSaveArea >= (char *)0xfffffffffffff000)
return;
@ -732,7 +732,7 @@ namespace CPU
SafeFunction static inline void fxrstor(void *FXRstorArea)
{
#if defined(__amd64__)
#if defined(a64)
if (!FXRstorArea || FXRstorArea >= (char *)0xfffffffffffff000)
return;

16
include/cpu/membar.hpp
View File

@ -9,10 +9,10 @@ namespace CPU
{
SafeFunction static inline void Barrier()
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("" ::
: "memory");
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("dmb ish" ::
: "memory");
#endif
@ -20,10 +20,10 @@ namespace CPU
SafeFunction static inline void Fence()
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("mfence" ::
: "memory");
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("dmb ish" ::
: "memory");
#endif
@ -31,10 +31,10 @@ namespace CPU
SafeFunction static inline void StoreFence()
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("sfence" ::
: "memory");
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("dmb ishst" ::
: "memory");
#endif
@ -42,10 +42,10 @@ namespace CPU
SafeFunction static inline void LoadFence()
{
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
asmv("lfence" ::
: "memory");
#elif defined(__aarch64__)
#elif defined(aa64)
asmv("dmb ishld" ::
: "memory");
#endif

81
include/cpu/x86/x32/cr.hpp
View File

@ -134,6 +134,87 @@ namespace CPU
};
uint32_t raw;
} CR8;
#if defined(a32)
SafeFunction static inline CR0 readcr0()
{
uint32_t Result = 0;
asmv("mov %%cr0, %[Result]"
: [Result] "=q"(Result));
return (CR0){.raw = Result};
}
SafeFunction static inline CR2 readcr2()
{
uint32_t Result = 0;
asmv("mov %%cr2, %[Result]"
: [Result] "=q"(Result));
return (CR2){.raw = Result};
}
SafeFunction static inline CR3 readcr3()
{
uint32_t Result = 0;
asmv("mov %%cr3, %[Result]"
: [Result] "=q"(Result));
return (CR3){.raw = Result};
}
SafeFunction static inline CR4 readcr4()
{
uint32_t Result = 0;
asmv("mov %%cr4, %[Result]"
: [Result] "=q"(Result));
return (CR4){.raw = Result};
}
SafeFunction static inline CR8 readcr8()
{
uint32_t Result = 0;
asmv("mov %%cr8, %[Result]"
: [Result] "=q"(Result));
return (CR8){.raw = Result};
}
SafeFunction static inline void writecr0(CR0 ControlRegister)
{
asmv("mov %[ControlRegister], %%cr0"
:
: [ControlRegister] "q"(ControlRegister.raw)
: "memory");
}
SafeFunction static inline void writecr2(CR2 ControlRegister)
{
asmv("mov %[ControlRegister], %%cr2"
:
: [ControlRegister] "q"(ControlRegister.raw)
: "memory");
}
SafeFunction static inline void writecr3(CR3 ControlRegister)
{
asmv("mov %[ControlRegister], %%cr3"
:
: [ControlRegister] "q"(ControlRegister.raw)
: "memory");
}
SafeFunction static inline void writecr4(CR4 ControlRegister)
{
asmv("mov %[ControlRegister], %%cr4"
:
: [ControlRegister] "q"(ControlRegister.raw)
: "memory");
}
SafeFunction static inline void writecr8(CR8 ControlRegister)
{
asmv("mov %[ControlRegister], %%cr8"
:
: [ControlRegister] "q"(ControlRegister.raw)
: "memory");
}
#endif
}
}

397
include/cpu/x86/x32/msr.hpp
View File

@ -7,7 +7,402 @@ namespace CPU
{
namespace x32
{
enum MSRID
{
MSR_MONITOR_FILTER_SIZE = 0x6,
MSR_TIME_STAMP_COUNTER = 0x10,
MSR_PLATFORM_ID = 0x17,
MSR_APIC_BASE = 0x1B,
MSR_FEATURE_CONTROL = 0x3A,
MSR_TSC_ADJUST = 0x3B,
MSR_SPEC_CTRL = 0x48,
MSR_PRED_CMD = 0x49,
MSR_BIOS_UPDT_TRIG = 0x79,
MSR_BIOS_SIGN_ID = 0x8B,
MSR_SGXLEPUBKEYHASH0 = 0x8C,
MSR_SGXLEPUBKEYHASH1 = 0x8D,
MSR_SGXLEPUBKEYHASH2 = 0x8E,
MSR_SGXLEPUBKEYHASH3 = 0x8F,
MSR_SMM_MONITOR_CTL = 0x9B,
MSR_SMBASE = 0x9E,
MSR_PMC0 = 0xC1,
MSR_PMC1 = 0xC2,
MSR_PMC2 = 0xC3,
MSR_PMC3 = 0xC4,
MSR_PMC4 = 0xC5,
MSR_PMC5 = 0xC6,
MSR_PMC6 = 0xC7,
MSR_PMC7 = 0xC8,
MSR_UMWAIT_CONTROL = 0xE1,
MSR_MPERF = 0xE7,
MSR_APERF = 0xE8,
MSR_MTRRCAP = 0xFE,
MSR_ARCH_CAPABILITIES = 0x10A,
MSR_FLUSH_CMD = 0x10B,
MSR_SYSENTER_CS = 0x17A,
MSR_SYSENTER_ESP = 0x175,
MSR_SYSENTER_EIP = 0x176,
MSR_MCG_CAP = 0x179,
MSR_MCG_STATUS = 0x17A,
MSR_MCG_CTL = 0x17B,
MSR_PERFEVTSEL0 = 0x186,
MSR_PERFEVTSEL1 = 0x187,
MSR_PERFEVTSEL2 = 0x188,
MSR_PERFEVTSEL3 = 0x189,
MSR_PERF_STATUS = 0x198,
MSR_PERF_CTL = 0x199,
MSR_CLOCK_MODULATION = 0x19A,
MSR_THERM_INTERRUPT = 0x19B,
MSR_THERM_STATUS = 0x19C,
MSR_MISC_ENABLE = 0x1A0,
MSR_ENERGY_PERF_BIAS = 0x1B0,
MSR_PACKAGE_THERM_STATUS = 0x1B1,
MSR_PACKAGE_THERM_INTERRUPT = 0x1B2,
MSR_DEBUGCTL = 0x1D9,
MSR_SMRR_PHYSBASE = 0x1F2,
MSR_SMRR_PHYSMASK = 0x1F3,
MSR_PLATFORM_DCA_CAP = 0x1F8,
MSR_CPU_DCA_CAP = 0x1F9,
MSR_DCA_0_CAP = 0x1FA,
MSR_MTRR_PHYSBASE0 = 0x200,
MSR_MTRR_PHYSMASK0 = 0x201,
MSR_MTRR_PHYSBASE1 = 0x202,
MSR_MTRR_PHYSMASK1 = 0x203,
MSR_MTRR_PHYSBASE2 = 0x204,
MSR_MTRR_PHYSMASK2 = 0x205,
MSR_MTRR_PHYSBASE3 = 0x206,
MSR_MTRR_PHYSMASK3 = 0x207,
MSR_MTRR_PHYSBASE4 = 0x208,
MSR_MTRR_PHYSMASK4 = 0x209,
MSR_MTRR_PHYSBASE5 = 0x20A,
MSR_MTRR_PHYSMASK5 = 0x20B,
MSR_MTRR_PHYSBASE6 = 0x20C,
MSR_MTRR_PHYSMASK6 = 0x20D,
MSR_MTRR_PHYSBASE7 = 0x20E,
MSR_MTRR_PHYSMASK7 = 0x20F,
MSR_MTRR_PHYSBASE8 = 0x210,
MSR_MTRR_PHYSMASK8 = 0x211,
MSR_MTRR_PHYSBASE9 = 0x212,
MSR_MTRR_PHYSMASK9 = 0x213,
MSR_MTRR_FIX64K_00000 = 0x250,
MSR_MTRR_FIX16K_80000 = 0x258,
MSR_MTRR_FIX16K_A0000 = 0x259,
MSR_MTRR_FIX4K_C0000 = 0x268,
MSR_MTRR_FIX4K_C8000 = 0x269,
MSR_MTRR_FIX4K_D0000 = 0x26A,
MSR_MTRR_FIX4K_D8000 = 0x26B,
MSR_MTRR_FIX4K_E0000 = 0x26C,
MSR_MTRR_FIX4K_E8000 = 0x26D,
MSR_MTRR_FIX4K_F0000 = 0x26E,
MSR_MTRR_FIX4K_F8000 = 0x26F,
MSR_PAT = 0x277,
MSR_MC0_CTL2 = 0x280,
MSR_MC1_CTL2 = 0x281,
MSR_MC2_CTL2 = 0x282,
MSR_MC3_CTL2 = 0x283,
MSR_MC4_CTL2 = 0x284,
MSR_MC5_CTL2 = 0x285,
MSR_MC6_CTL2 = 0x286,
MSR_MC7_CTL2 = 0x287,
MSR_MC8_CTL2 = 0x288,
MSR_MC9_CTL2 = 0x289,
MSR_MC10_CTL2 = 0x28A,
MSR_MC11_CTL2 = 0x28B,
MSR_MC12_CTL2 = 0x28C,
MSR_MC13_CTL2 = 0x28D,
MSR_MC14_CTL2 = 0x28E,
MSR_MC15_CTL2 = 0x28F,
MSR_MC16_CTL2 = 0x290,
MSR_MC17_CTL2 = 0x291,
MSR_MC18_CTL2 = 0x292,
MSR_MC19_CTL2 = 0x293,
MSR_MC20_CTL2 = 0x294,
MSR_MC21_CTL2 = 0x295,
MSR_MC22_CTL2 = 0x296,
MSR_MC23_CTL2 = 0x297,
MSR_MC24_CTL2 = 0x298,
MSR_MC25_CTL2 = 0x299,
MSR_MC26_CTL2 = 0x29A,
MSR_MC27_CTL2 = 0x29B,
MSR_MC28_CTL2 = 0x29C,
MSR_MC29_CTL2 = 0x29D,
MSR_MC30_CTL2 = 0x29E,
MSR_MC31_CTL2 = 0x29F,
MSR_MTRR_DEF_TYPE = 0x2FF,
MSR_FIXED_CTR0 = 0x309,
MSR_FIXED_CTR1 = 0x30A,
MSR_FIXED_CTR2 = 0x30B,
MSR_PERF_CAPABILITIES = 0x345,
MSR_FIXED_CTR_CTRL = 0x38D,
MSR_PERF_GLOBAL_STATUS = 0x38E,
MSR_PERF_GLOBAL_CTRL = 0x38F,
MSR_PERF_GLOBAL_STATUS_RESET = 0x390,
MSR_PERF_GLOBAL_STATUS_SET = 0x391,
MSR_PERF_GLOBAL_INUSE = 0x392,
MSR_PEBS_ENABLE = 0x3F1,
MSR_MC0_CTL = 0x400,
MSR_MC0_STATUS = 0x401,
MSR_MC0_ADDR = 0x402,
MSR_MC0_MISC = 0x403,
MSR_MC1_CTL = 0x404,
MSR_MC1_STATUS = 0x405,
MSR_MC1_ADDR = 0x406,
MSR_MC1_MISC = 0x407,
MSR_MC2_CTL = 0x408,
MSR_MC2_STATUS = 0x409,
MSR_MC2_ADDR = 0x40A,
MSR_MC2_MISC = 0x40B,
MSR_MC3_CTL = 0x40C,
MSR_MC3_STATUS = 0x40D,
MSR_MC3_ADDR = 0x40E,
MSR_MC3_MISC = 0x40F,
MSR_MC4_CTL = 0x410,
MSR_MC4_STATUS = 0x411,
MSR_MC4_ADDR = 0x412,
MSR_MC4_MISC = 0x413,
MSR_MC5_CTL = 0x414,
MSR_MC5_STATUS = 0x415,
MSR_MC5_ADDR = 0x416,
MSR_MC5_MISC = 0x417,
MSR_MC6_CTL = 0x418,
MSR_MC6_STATUS = 0x419,
MSR_MC6_ADDR = 0x41A,
MSR_MC6_MISC = 0x41B,
MSR_MC7_CTL = 0x41C,
MSR_MC7_STATUS = 0x41D,
MSR_MC7_ADDR = 0x41E,
MSR_MC7_MISC = 0x41F,
MSR_MC8_CTL = 0x420,
MSR_MC8_STATUS = 0x421,
MSR_MC8_ADDR = 0x422,
MSR_MC8_MISC = 0x423,
MSR_MC9_CTL = 0x424,
MSR_MC9_STATUS = 0x425,
MSR_MC9_ADDR = 0x426,
MSR_MC9_MISC = 0x427,
MSR_MC10_CTL = 0x428,
MSR_MC10_STATUS = 0x429,
MSR_MC10_ADDR = 0x42A,
MSR_MC10_MISC = 0x42B,
MSR_MC11_CTL = 0x42C,
MSR_MC11_STATUS = 0x42D,
MSR_MC11_ADDR = 0x42E,
MSR_MC11_MISC = 0x42F,
MSR_MC12_CTL = 0x430,
MSR_MC12_STATUS = 0x431,
MSR_MC12_ADDR = 0x432,
MSR_MC12_MISC = 0x433,
MSR_MC13_CTL = 0x434,
MSR_MC13_STATUS = 0x435,
MSR_MC13_ADDR = 0x436,
MSR_MC13_MISC = 0x437,
MSR_MC14_CTL = 0x438,
MSR_MC14_STATUS = 0x439,
MSR_MC14_ADDR = 0x43A,
MSR_MC14_MISC = 0x43B,
MSR_MC15_CTL = 0x43C,
MSR_MC15_STATUS = 0x43D,
MSR_MC15_ADDR = 0x43E,
MSR_MC15_MISC = 0x43F,
MSR_MC16_CTL = 0x440,
MSR_MC16_STATUS = 0x441,
MSR_MC16_ADDR = 0x442,
MSR_MC16_MISC = 0x443,
MSR_MC17_CTL = 0x444,
MSR_MC17_STATUS = 0x445,
MSR_MC17_ADDR = 0x446,
MSR_MC17_MISC = 0x447,
MSR_MC18_CTL = 0x448,
MSR_MC18_STATUS = 0x449,
MSR_MC18_ADDR = 0x44A,
MSR_MC18_MISC = 0x44B,
MSR_MC19_CTL = 0x44C,
MSR_MC19_STATUS = 0x44D,
MSR_MC19_ADDR = 0x44E,
MSR_MC19_MISC = 0x44F,
MSR_MC20_CTL = 0x450,
MSR_MC20_STATUS = 0x451,
MSR_MC20_ADDR = 0x452,
MSR_MC20_MISC = 0x453,
MSR_MC21_CTL = 0x454,
MSR_MC21_STATUS = 0x455,
MSR_MC21_ADDR = 0x456,
MSR_MC21_MISC = 0x457,
MSR_MC22_CTL = 0x458,
MSR_MC22_STATUS = 0x459,
MSR_MC22_ADDR = 0x45A,
MSR_MC22_MISC = 0x45B,
MSR_MC23_CTL = 0x45C,
MSR_MC23_STATUS = 0x45D,
MSR_MC23_ADDR = 0x45E,
MSR_MC23_MISC = 0x45F,
MSR_MC24_CTL = 0x460,
MSR_MC24_STATUS = 0x461,
MSR_MC24_ADDR = 0x462,
MSR_MC24_MISC = 0x463,
MSR_MC25_CTL = 0x464,
MSR_MC25_STATUS = 0x465,
MSR_MC25_ADDR = 0x466,
MSR_MC25_MISC = 0x467,
MSR_MC26_CTL = 0x468,
MSR_MC26_STATUS = 0x469,
MSR_MC26_ADDR = 0x46A,
MSR_MC26_MISC = 0x46B,
MSR_MC27_CTL = 0x46C,
MSR_MC27_STATUS = 0x46D,
MSR_MC27_ADDR = 0x46E,
MSR_MC27_MISC = 0x46F,
MSR_MC28_CTL = 0x470,
MSR_MC28_STATUS = 0x471,
MSR_MC28_ADDR = 0x472,
MSR_MC28_MISC = 0x473,
MSR_VMX_BASIC = 0x480,
MSR_VMX_PINBASED_CTLS = 0x481,
MSR_VMX_PROCBASED_CTLS = 0x482,
MSR_VMX_EXIT_CTLS = 0x483,
MSR_VMX_ENTRY_CTLS = 0x484,
MSR_VMX_MISC = 0x485,
MSR_VMX_CR0_FIXED0 = 0x486,
MSR_VMX_CR0_FIXED1 = 0x487,
MSR_VMX_CR4_FIXED0 = 0x488,
MSR_VMX_CR4_FIXED1 = 0x489,
MSR_VMX_VMCS_ENUM = 0x48A,
MSR_VMX_PROCBASED_CTLS2 = 0x48B,
MSR_VMX_EPT_VPID_CAP = 0x48C,
MSR_VMX_TRUE_PINBASED_CTLS = 0x48D,
MSR_VMX_TRUE_PROCBASED_CTLS = 0x48E,
MSR_VMX_TRUE_EXIT_CTLS = 0x48F,
MSR_VMX_TRUE_ENTRY_CTLS = 0x490,
MSR_VMX_VMFUNC = 0x491,
MSR_A_PMC0 = 0x4C1,
MSR_A_PMC1 = 0x4C2,
MSR_A_PMC2 = 0x4C3,
MSR_A_PMC3 = 0x4C4,
MSR_A_PMC4 = 0x4C5,
MSR_A_PMC5 = 0x4C6,
MSR_A_PMC6 = 0x4C7,
MSR_A_PMC7 = 0x4C8,
MSR_MCG_EXT_CTL = 0x4D0,
MSR_SGX_SVN_STATUS = 0x500,
MSR_RTIT_OUTPUT_BASE = 0x560,
MSR_RTIT_OUTPUT_MASK_PTRS = 0x561,
MSR_RTIT_CTL = 0x570,
MSR_RTIT_STATUS = 0x571,
MSR_RTIT_CR3_MATCH = 0x572,
MSR_RTIT_ADDR0_A = 0x580,
MSR_RTIT_ADDR0_B = 0x581,
MSR_RTIT_ADDR1_A = 0x582,
MSR_RTIT_ADDR1_B = 0x583,
MSR_RTIT_ADDR2_A = 0x584,
MSR_RTIT_ADDR2_B = 0x585,
MSR_RTIT_ADDR3_A = 0x586,
MSR_RTIT_ADDR3_B = 0x587,
MSR_DS_AREA = 0x600,
MSR_TSC_DEADLINE = 0x6E0,
MSR_PM_ENABLE = 0x770,
MSR_HWP_CAPABILITIES = 0x771,
MSR_HWP_REQUEST_PKG = 0x772,
MSR_HWP_INTERRUPT = 0x773,
MSR_HWP_REQUEST = 0x774,
MSR_HWP_STATUS = 0x777,
MSR_X2APIC_APICID = 0x802,
MSR_X2APIC_VERSION = 0x803,
MSR_X2APIC_TPR = 0x808,
MSR_X2APIC_PPR = 0x80A,
MSR_X2APIC_EOI = 0x80B,
MSR_X2APIC_LDR = 0x80D,
MSR_X2APIC_SIVR = 0x80F,
MSR_X2APIC_ISR0 = 0x810,
MSR_X2APIC_ISR1 = 0x811,
MSR_X2APIC_ISR2 = 0x812,
MSR_X2APIC_ISR3 = 0x813,
MSR_X2APIC_ISR4 = 0x814,
MSR_X2APIC_ISR5 = 0x815,
MSR_X2APIC_ISR6 = 0x816,
MSR_X2APIC_ISR7 = 0x817,
MSR_X2APIC_TMR0 = 0x818,
MSR_X2APIC_TMR1 = 0x819,
MSR_X2APIC_TMR2 = 0x81A,
MSR_X2APIC_TMR3 = 0x81B,
MSR_X2APIC_TMR4 = 0x81C,
MSR_X2APIC_TMR5 = 0x81D,
MSR_X2APIC_TMR6 = 0x81E,
MSR_X2APIC_TMR7 = 0x81F,
MSR_X2APIC_IRR0 = 0x820,
MSR_X2APIC_IRR1 = 0x821,
MSR_X2APIC_IRR2 = 0x822,
MSR_X2APIC_IRR3 = 0x823,
MSR_X2APIC_IRR4 = 0x824,
MSR_X2APIC_IRR5 = 0x825,
MSR_X2APIC_IRR6 = 0x826,
MSR_X2APIC_IRR7 = 0x827,
MSR_X2APIC_ESR = 0x828,
MSR_X2APIC_LVT_CMCI = 0x82F,
MSR_X2APIC_ICR = 0x830,
MSR_X2APIC_LVT_TIMER = 0x832,
MSR_X2APIC_LVT_THERMAL = 0x833,
MSR_X2APIC_LVT_PMI = 0x834,
MSR_X2APIC_LVT_LINT0 = 0x835,
MSR_X2APIC_LVT_LINT1 = 0x836,
MSR_X2APIC_LVT_ERROR = 0x837,
MSR_X2APIC_INIT_COUNT = 0x838,
MSR_X2APIC_CUR_COUNT = 0x839,
MSR_X2APIC_DIV_CONF = 0x83E,
MSR_X2APIC_SELF_IPI = 0x83F,
MSR_DEBUG_INTERFACE = 0xC80,
MSR_L3_QOS_CFG = 0xC81,
MSR_L2_QOS_CFG = 0xC82,
MSR_QM_EVTSEL = 0xC8D,
MSR_QM_CTR = 0xC8E,
MSR_PQR_ASSOC = 0xC8F,
MSR_L3_MASK_0 = 0xC90,
MSR_L2_MASK_0 = 0xD10,
MSR_BNDCFGS = 0xD90,
MSR_XSS = 0xDA0,
MSR_PKG_HDC_CTL = 0xDB0,
MSR_PM_CTL1 = 0xDB1,
MSR_THREAD_STALL = 0xDB2,
/** @brief Extended Feature Enable Register (0xc0000080) */
MSR_EFER = 0xC0000080,
/** @brief legacy SYSCALL (0xC0000081) */
MSR_STAR = 0xC0000081,
/** @brief 64bit SYSCALL (0xC0000082) */
MSR_LSTAR = 0xC0000082,
/** @brief compatibility mode SYSCALL (0xC0000083) */
MSR_CSTAR = 0xC0000083,
/** @brief EFLAGS mask for syscall (0xC0000084) */
MSR_SYSCALL_MASK = 0xC0000084,
/** @brief 64bit FS base (0xC0000100) */
MSR_FS_BASE = 0xC0000100,
/** @brief 64bit GS base (0xC0000101) */
MSR_GS_BASE = 0xC0000101,
/** @brief SwapGS GS shadow (0xC0000102) */
MSR_SHADOW_GS_BASE = 0xC0000102,
/** @brief Auxiliary TSC (0xC0000103) */
MSR_TSC_AUX = 0xC0000103,
MSR_CR_PAT = 0x00000277,
};
#if defined(a32)
SafeFunction static inline uint64_t rdmsr(uint32_t msr)
{
uint32_t Low, High;
asmv("rdmsr"
: "=a"(Low), "=d"(High)
: "c"(msr)
: "memory");
return ((uint64_t)Low) | (((uint64_t)High) << 32);
}
SafeFunction static inline void wrmsr(uint32_t msr, uint64_t Value)
{
uint32_t Low = Value, High = Value >> 32;
asmv("wrmsr"
:
: "c"(msr), "a"(Low), "d"(High)
: "memory");
}
#endif
}
}

26
include/cpu/x86/x64/cr.hpp
View File

@ -172,127 +172,105 @@ namespace CPU
uint64_t raw;
} XCR0;
#if defined(a64)
SafeFunction static inline CR0 readcr0()
{
uint64_t Result = 0;
#if defined(__amd64__)
asmv("mov %%cr0, %[Result]"
: [Result] "=q"(Result));
#endif
return (CR0){.raw = Result};
}
SafeFunction static inline CR2 readcr2()
{
uint64_t Result = 0;
#if defined(__amd64__)
asmv("mov %%cr2, %[Result]"
: [Result] "=q"(Result));
#endif
return (CR2){.raw = Result};
}
SafeFunction static inline CR3 readcr3()
{
uint64_t Result = 0;
#if defined(__amd64__)
asmv("mov %%cr3, %[Result]"
: [Result] "=q"(Result));
#endif
return (CR3){.raw = Result};
}
SafeFunction static inline CR4 readcr4()
{
uint64_t Result = 0;
#if defined(__amd64__)
asmv("mov %%cr4, %[Result]"
: [Result] "=q"(Result));
#endif
return (CR4){.raw = Result};
}
SafeFunction static inline CR8 readcr8()
{
uint64_t Result = 0;
#if defined(__amd64__)
asmv("mov %%cr8, %[Result]"
: [Result] "=q"(Result));
#endif
return (CR8){.raw = Result};
}
SafeFunction static inline XCR0 readxcr0()
{
uint64_t Result = 0;
#if defined(__amd64__)
asmv("xgetbv"
: "=a"(Result)
: "c"(0)
: "edx");
#endif
return (XCR0){.raw = Result};
}
SafeFunction static inline void writecr0(CR0 ControlRegister)
{
#if defined(__amd64__)
asmv("mov %[ControlRegister], %%cr0"
:
: [ControlRegister] "q"(ControlRegister.raw)
: "memory");
#endif
}
SafeFunction static inline void writecr2(CR2 ControlRegister)
{
#if defined(__amd64__)
asmv("mov %[ControlRegister], %%cr2"
:
: [ControlRegister] "q"(ControlRegister.raw)
: "memory");
#endif
}
SafeFunction static inline void writecr3(CR3 ControlRegister)
{
#if defined(__amd64__)
asmv("mov %[ControlRegister], %%cr3"
:
: [ControlRegister] "q"(ControlRegister.raw)
: "memory");
#endif
}
SafeFunction static inline void writecr4(CR4 ControlRegister)
{
#if defined(__amd64__)
asmv("mov %[ControlRegister], %%cr4"
:
: [ControlRegister] "q"(ControlRegister.raw)
: "memory");
#endif
}
SafeFunction static inline void writecr8(CR8 ControlRegister)
{
#if defined(__amd64__)
asmv("mov %[ControlRegister], %%cr8"
:
: [ControlRegister] "q"(ControlRegister.raw)
: "memory");
#endif
}
SafeFunction static inline void writexcr0(XCR0 ControlRegister)
{
#if defined(__amd64__)
asmv("xsetbv"
:
: "a"(ControlRegister.raw), "c"(0)
: "edx");
#endif
}
#endif
}
}

6
include/cpu/x86/x64/msr.hpp
View File

@ -384,28 +384,26 @@ namespace CPU
MSR_CR_PAT_RESET = 0x0007040600070406ULL
};
#if defined(a64)
SafeFunction static inline uint64_t rdmsr(uint32_t msr)
{
uint32_t Low, High;
#if defined(__amd64__)
asmv("rdmsr"
: "=a"(Low), "=d"(High)
: "c"(msr)
: "memory");
#endif
return ((uint64_t)Low) | (((uint64_t)High) << 32);
}
SafeFunction static inline void wrmsr(uint32_t msr, uint64_t Value)
{
uint32_t Low = Value, High = Value >> 32;
#if defined(__amd64__)
asmv("wrmsr"
:
: "c"(msr), "a"(Low), "d"(High)
: "memory");
#endif
}
#endif
}
}

8
include/driver.hpp
View File

@ -33,11 +33,11 @@ namespace Driver
void *Handle;
void *Data;
#if defined(__amd64__)
#if defined(a64)
void OnInterruptReceived(CPU::x64::TrapFrame *Frame);
#elif defined(__i386__)
void OnInterruptReceived(void *Frame);
#elif defined(__aarch64__)
#elif defined(a32)
void OnInterruptReceived(CPU::x32::TrapFrame *Frame);
#elif defined(aa64)
void OnInterruptReceived(void *Frame);
#endif

14
include/ints.hpp
View File

@ -12,13 +12,13 @@ namespace Interrupts
#define INT_FRAMES_MAX 8
#endif
#if defined(__amd64__)
#if defined(a64)
/* APIC::APIC */ extern void *apic[256]; // MAX_CPU
/* APIC::Timer */ extern void *apicTimer[256]; // MAX_CPU
#elif defined(__i386__)
#elif defined(a32)
/* APIC::APIC */ extern void *apic[256]; // MAX_CPU
/* APIC::Timer */ extern void *apicTimer[256]; // MAX_CPU
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
extern void *InterruptFrames[INT_FRAMES_MAX];
@ -39,11 +39,11 @@ namespace Interrupts
~Handler();
public:
#if defined(__amd64__)
#if defined(a64)
virtual void OnInterruptReceived(CPU::x64::TrapFrame *Frame);
#elif defined(__i386__)
virtual void OnInterruptReceived(void *Frame);
#elif defined(__aarch64__)
#elif defined(a32)
virtual void OnInterruptReceived(CPU::x32::TrapFrame *Frame);
#elif defined(aa64)
virtual void OnInterruptReceived(void *Frame);
#endif
};

4
include/io.h
View File

@ -3,7 +3,7 @@
#include <types.h>
#if defined(__amd64__) || defined(__i386__)
#if defined(a64) || defined(a32)
#ifdef __cplusplus
extern "C"
@ -215,6 +215,6 @@ extern "C"
#define outw(Port, Data) outportw(Port, Data)
#define outl(Port, Data) outportl(Port, Data)
#endif // defined(__amd64__) || defined(__i386__)
#endif // defined(a64) || defined(a32)
#endif // !__FENNIX_KERNEL_IO_H__

67
include/memory.hpp
View File

@ -46,22 +46,19 @@ extern uintptr_t _kernel_text_end, _kernel_data_end, _kernel_rodata_end;
// From pages
#define FROM_PAGES(d) ((d)*PAGE_SIZE - 1)
#if defined(a64) || defined(aa64)
#define NORMAL_VMA_OFFSET 0xFFFF800000000000
#define KERNEL_VMA_OFFSET 0xFFFFFFFF80000000
/**
* @brief KERNEL_HEAP_BASE is the base address of the kernel heap
*/
#define KERNEL_HEAP_BASE 0xFFFFA00000000000
/**
* @brief USER_HEAP_BASE is the base address of the user heap allocated by the kernel
*/
#define USER_HEAP_BASE 0xFFFFB00000000000
/**
* @brief USER_STACK_BASE is the base address of the user stack
*/
#define USER_STACK_BASE 0xFFFFEFFFFFFF0000
#elif defined(a32)
#define NORMAL_VMA_OFFSET 0x80000000
#define KERNEL_VMA_OFFSET 0xC0000000
#define KERNEL_HEAP_BASE 0xA0000000
#define USER_HEAP_BASE 0xB0000000
#define USER_STACK_BASE 0xEFFFFFFF
#endif
namespace Memory
{
@ -181,15 +178,15 @@ namespace Memory
/** @brief Set Address */
void SetAddress(uintptr_t _Address)
{
#if defined(__amd64__)
#if defined(a64)
_Address &= 0x000000FFFFFFFFFF;
this->raw &= 0xFFF0000000000FFF;
this->raw |= (_Address << 12);
#elif defined(__i386__)
#elif defined(a32)
_Address &= 0x000FFFFF;
this->raw &= 0xFFC00003;
this->raw |= (_Address << 12);
#elif defined(__aarch64__)
#elif defined(aa64)
_Address &= 0x000000FFFFFFFFFF;
this->raw &= 0xFFF0000000000FFF;
this->raw |= (_Address << 12);
@ -199,11 +196,11 @@ namespace Memory
/** @brief Get Address */
uintptr_t GetAddress()
{
#if defined(__amd64__)
#if defined(a64)
return (this->raw & 0x000FFFFFFFFFF000) >> 12;
#elif defined(__i386__)
#elif defined(a32)
return (this->raw & 0x003FFFFF000) >> 12;
#elif defined(__aarch64__)
#elif defined(aa64)
return (this->raw & 0x000FFFFFFFFFF000) >> 12;
#endif
}
@ -236,15 +233,15 @@ namespace Memory
/** @brief Set PageTableEntryPtr address */
void SetAddress(uintptr_t _Address)
{
#if defined(__amd64__)
#if defined(a64)
_Address &= 0x000000FFFFFFFFFF;
this->raw &= 0xFFF0000000000FFF;
this->raw |= (_Address << 12);
#elif defined(__i386__)
#elif defined(a32)
_Address &= 0x000FFFFF;
this->raw &= 0xFFC00003;
this->raw |= (_Address << 12);
#elif defined(__aarch64__)
#elif defined(aa64)
_Address &= 0x000000FFFFFFFFFF;
this->raw &= 0xFFF0000000000FFF;
this->raw |= (_Address << 12);
@ -254,11 +251,11 @@ namespace Memory
/** @brief Get PageTableEntryPtr address */
uintptr_t GetAddress()
{
#if defined(__amd64__)
#if defined(a64)
return (this->raw & 0x000FFFFFFFFFF000) >> 12;
#elif defined(__i386__)
#elif defined(a32)
return (this->raw & 0x003FFFFF000) >> 12;
#elif defined(__aarch64__)
#elif defined(aa64)
return (this->raw & 0x000FFFFFFFFFF000) >> 12;
#endif
}
@ -291,15 +288,15 @@ namespace Memory
/** @brief Set PageDirectoryEntryPtr address */
void SetAddress(uintptr_t _Address)
{
#if defined(__amd64__)
#if defined(a64)
_Address &= 0x000000FFFFFFFFFF;
this->raw &= 0xFFF0000000000FFF;
this->raw |= (_Address << 12);
#elif defined(__i386__)
#elif defined(a32)
_Address &= 0x000FFFFF;
this->raw &= 0xFFC00003;
this->raw |= (_Address << 12);
#elif defined(__aarch64__)
#elif defined(aa64)
_Address &= 0x000000FFFFFFFFFF;
this->raw &= 0xFFF0000000000FFF;
this->raw |= (_Address << 12);
@ -309,11 +306,11 @@ namespace Memory
/** @brief Get PageDirectoryEntryPtr address */
uintptr_t GetAddress()
{
#if defined(__amd64__)
#if defined(a64)
return (this->raw & 0x000FFFFFFFFFF000) >> 12;
#elif defined(__i386__)
#elif defined(a32)
return (this->raw & 0x003FFFFF000) >> 12;
#elif defined(__aarch64__)
#elif defined(aa64)
return (this->raw & 0x000FFFFFFFFFF000) >> 12;
#endif
}
@ -346,15 +343,15 @@ namespace Memory
/** @brief Set PageDirectoryPointerTableEntryPtr address */
void SetAddress(uintptr_t _Address)
{
#if defined(__amd64__)
#if defined(a64)
_Address &= 0x000000FFFFFFFFFF;
this->raw &= 0xFFF0000000000FFF;
this->raw |= (_Address << 12);
#elif defined(__i386__)
#elif defined(a32)
_Address &= 0x000FFFFF;
this->raw &= 0xFFC00003;
this->raw |= (_Address << 12);
#elif defined(__aarch64__)
#elif defined(aa64)
_Address &= 0x000000FFFFFFFFFF;
this->raw &= 0xFFF0000000000FFF;
this->raw |= (_Address << 12);
@ -364,11 +361,11 @@ namespace Memory
/** @brief Get PageDirectoryPointerTableEntryPtr address */
uintptr_t GetAddress()
{
#if defined(__amd64__)
#if defined(a64)
return (this->raw & 0x000FFFFFFFFFF000) >> 12;
#elif defined(__i386__)
#elif defined(a32)
return (this->raw & 0x003FFFFF000) >> 12;
#elif defined(__aarch64__)
#elif defined(aa64)
return (this->raw & 0x000FFFFFFFFFF000) >> 12;
#endif
}

6
include/smp.hpp
View File

@ -11,11 +11,11 @@
struct CPUArchData
{
#if defined(__amd64__)
#if defined(a64)
CPU::x64::FXState *FPU;
/* TODO */
#elif defined(__i386__)
#elif defined(__aarch64__)
#elif defined(a32)
#elif defined(aa64)
#endif
};

6
include/syscalls.hpp
View File

@ -5,14 +5,14 @@
typedef struct SyscallsFrame
{
#if defined(__amd64__)
#if defined(a64)
uint64_t r15, r14, r13, r12, r11, r10, r9, r8;
uint64_t rbp, rdi, rsi, rdx, rcx, rbx, rax;
uint64_t InterruptNumber, ErrorCode, rip, cs, rflags, rsp, ss;
#elif defined(__i386__)
#elif defined(a32)
uint32_t ebp, edi, esi, edx, ecx, ebx, eax;
uint32_t InterruptNumber, ErrorCode, eip, cs, eflags, esp, ss;
#elif defined(__aarch64__)
#elif defined(aa64)
#endif
} SyscallsFrame;

14
include/task.hpp
View File

@ -102,13 +102,13 @@ namespace Tasking
Memory::StackGuard *Stack;
Memory::MemMgr *Memory;
TaskStatus Status;
#if defined(__amd64__)
#if defined(a64)
CPU::x64::TrapFrame Registers;
uint64_t GSBase, FSBase;
#elif defined(__i386__)
#elif defined(a32)
CPU::x32::TrapFrame Registers; // TODO
uint64_t GSBase, FSBase;
#elif defined(__aarch64__)
#elif defined(aa64)
uint64_t Registers; // TODO
#endif
uintptr_t IPHistory[128];
@ -250,13 +250,13 @@ namespace Tasking
void UpdateProcessStatus();
void WakeUpThreads(void *CPUDataPointer);
#if defined(__amd64__)
#if defined(a64)
void Schedule(CPU::x64::TrapFrame *Frame);
void OnInterruptReceived(CPU::x64::TrapFrame *Frame);
#elif defined(__i386__)
#elif defined(a32)
void Schedule(void *Frame);
void OnInterruptReceived(void *Frame);
#elif defined(__aarch64__)
void OnInterruptReceived(CPU::x32::TrapFrame *Frame);
#elif defined(aa64)
void Schedule(void *Frame);
void OnInterruptReceived(void *Frame);
#endif

6
include/types.h
View File

@ -208,17 +208,17 @@ typedef intptr_t ssize_t;
#define WINT_MAX __WINT_MAX__
#define WINT_MIN __WINT_MIN__
#if defined(__amd64__)
#if defined(a64)
#define BREAK __asm__ __volatile__("int $0x3" \
: \
: \
: "memory");
#elif defined(__i386__)
#elif defined(a32)
#define BREAK __asm__ __volatile__("int $0x3" \
: \
: \
: "memory");
#elif defined(__aarch64__)
#elif defined(aa64)
#define BREAK __asm__ __volatile__("brk #0" \
: \
: \