mirror of
https://github.com/EnderIce2/Fennix.git
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385 lines
12 KiB
C++
385 lines
12 KiB
C++
#include "apic.hpp"
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#include <memory.hpp>
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#include <uart.hpp>
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#include <lock.hpp>
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#include <cpu.hpp>
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#include <smp.hpp>
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#include <io.h>
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#include "../../../kernel.h"
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#include "../acpi.hpp"
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NewLock(APICLock);
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using namespace CPU::x64;
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using namespace CPU::x86;
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/*
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In constructor ‘APIC::APIC::APIC(int)’:
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warning: left shift count >= width of type
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| APICBaseAddress = BaseStruct.ApicBaseLo << 12u | BaseStruct.ApicBaseHi << 32u;
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| ~~~~~~~~~~~~~~~~~~~~~~^~~~~~
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*/
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#pragma GCC diagnostic ignored "-Wshift-count-overflow"
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namespace APIC
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{
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// headache
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// https://www.amd.com/system/files/TechDocs/24593.pdf
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// https://www.naic.edu/~phil/software/intel/318148.pdf
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uint32_t APIC::Read(uint32_t Register)
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{
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if (Register != APIC_ICRLO &&
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Register != APIC_ICRHI &&
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Register != APIC_ID)
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debug("APIC::Read(%#lx) [x2=%d]", Register, x2APICSupported ? 1 : 0);
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if (x2APICSupported)
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{
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if (Register != APIC_ICRHI)
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return rdmsr((Register >> 4) + 0x800);
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else
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return rdmsr(0x30 + 0x800);
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}
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else
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{
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CPU::MemBar::Barrier();
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uint32_t ret = *((volatile uint32_t *)((uintptr_t)APICBaseAddress + Register));
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CPU::MemBar::Barrier();
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return ret;
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}
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}
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void APIC::Write(uint32_t Register, uint32_t Value)
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{
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if (Register != APIC_EOI &&
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Register != APIC_TDCR &&
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Register != APIC_TIMER &&
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Register != APIC_TICR &&
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Register != APIC_ICRLO &&
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Register != APIC_ICRHI)
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debug("APIC::Write(%#lx, %#lx) [x2=%d]", Register, Value, x2APICSupported ? 1 : 0);
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if (x2APICSupported)
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{
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if (Register != APIC_ICRHI)
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wrmsr((Register >> 4) + 0x800, Value);
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else
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wrmsr(MSR_X2APIC_ICR, Value);
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}
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else
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{
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CPU::MemBar::Barrier();
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*((volatile uint32_t *)(((uintptr_t)APICBaseAddress) + Register)) = Value;
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CPU::MemBar::Barrier();
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}
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}
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void APIC::IOWrite(uint64_t Base, uint32_t Register, uint32_t Value)
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{
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debug("APIC::IOWrite(%#lx, %#lx, %#lx)", Base, Register, Value);
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CPU::MemBar::Barrier();
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*((volatile uint32_t *)(((uintptr_t)Base))) = Register;
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CPU::MemBar::Barrier();
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*((volatile uint32_t *)(((uintptr_t)Base + 16))) = Value;
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CPU::MemBar::Barrier();
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}
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uint32_t APIC::IORead(uint64_t Base, uint32_t Register)
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{
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debug("APIC::IORead(%#lx, %#lx)", Base, Register);
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CPU::MemBar::Barrier();
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*((volatile uint32_t *)(((uintptr_t)Base))) = Register;
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CPU::MemBar::Barrier();
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uint32_t ret = *((volatile uint32_t *)(((uintptr_t)Base + 16)));
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CPU::MemBar::Barrier();
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return ret;
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}
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void APIC::EOI() { this->Write(APIC_EOI, 0); }
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void APIC::WaitForIPI()
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{
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InterruptCommandRegisterLow icr = {.raw = 0};
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do
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{
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icr.raw = this->Read(APIC_ICRLO);
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} while (icr.DeliveryStatus != Idle);
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}
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void APIC::IPI(uint8_t CPU, InterruptCommandRegisterLow icr)
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{
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SmartCriticalSection(APICLock);
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if (x2APICSupported)
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{
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fixme("Not implemented for x2APIC");
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// wrmsr(MSR_X2APIC_ICR, ((uint64_t)CPU) << 32);
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}
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else
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{
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this->Write(APIC_ICRHI, (CPU << 24));
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this->Write(APIC_ICRLO, icr.raw);
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this->WaitForIPI();
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}
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}
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void APIC::SendInitIPI(uint8_t CPU)
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{
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SmartCriticalSection(APICLock);
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if (x2APICSupported)
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{
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fixme("Not implemented for x2APIC");
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// wrmsr(MSR_X2APIC_ICR, ((uint64_t)CPU) << 32);
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}
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else
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{
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InterruptCommandRegisterLow icr = {.raw = 0};
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icr.DeliveryMode = INIT;
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icr.Level = Assert;
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this->Write(APIC_ICRHI, (CPU << 24));
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this->Write(APIC_ICRLO, icr.raw);
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this->WaitForIPI();
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}
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}
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void APIC::SendStartupIPI(uint8_t CPU, uint64_t StartupAddress)
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{
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SmartCriticalSection(APICLock);
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if (x2APICSupported)
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{
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warn("Not tested for x2APIC");
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wrmsr(MSR_X2APIC_ICR, ((uint64_t)CPU) << 32 | StartupAddress);
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}
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else
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{
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InterruptCommandRegisterLow icr = {.raw = 0};
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icr.Vector = StartupAddress >> 12;
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icr.DeliveryMode = Startup;
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icr.Level = Assert;
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this->Write(APIC_ICRHI, (CPU << 24));
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this->Write(APIC_ICRLO, icr.raw);
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this->WaitForIPI();
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}
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}
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uint32_t APIC::IOGetMaxRedirect(uint32_t APICID)
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{
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uint32_t TableAddress = (this->IORead((((ACPI::MADT *)PowerManager->GetMADT())->ioapic[APICID]->Address), GetIOAPICVersion));
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return ((IOAPICVersion *)&TableAddress)->MaximumRedirectionEntry;
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}
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void APIC::RawRedirectIRQ(uint8_t Vector, uint32_t GSI, uint16_t Flags, int CPU, int Status)
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{
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uint64_t Value = Vector;
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int64_t IOAPICTarget = -1;
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for (uint64_t i = 0; ((ACPI::MADT *)PowerManager->GetMADT())->ioapic[i] != 0; i++)
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if (((ACPI::MADT *)PowerManager->GetMADT())->ioapic[i]->GSIBase <= GSI)
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if (((ACPI::MADT *)PowerManager->GetMADT())->ioapic[i]->GSIBase + IOGetMaxRedirect(i) > GSI)
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{
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IOAPICTarget = i;
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break;
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}
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if (IOAPICTarget == -1)
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{
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error("No ISO table found for I/O APIC");
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return;
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}
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// TODO: IOAPICRedirectEntry Entry = {.raw = 0};
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if (Flags & ActiveHighLow)
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Value |= (1 << 13);
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if (Flags & EdgeLevel)
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Value |= (1 << 15);
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if (!Status)
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Value |= (1 << 16);
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Value |= (((uintptr_t)CPU) << 56);
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uint32_t IORegister = (GSI - ((ACPI::MADT *)PowerManager->GetMADT())->ioapic[IOAPICTarget]->GSIBase) * 2 + 16;
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this->IOWrite(((ACPI::MADT *)PowerManager->GetMADT())->ioapic[IOAPICTarget]->Address, IORegister, (uint32_t)Value);
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this->IOWrite(((ACPI::MADT *)PowerManager->GetMADT())->ioapic[IOAPICTarget]->Address, IORegister + 1, (uint32_t)(Value >> 32));
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}
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void APIC::RedirectIRQ(int CPU, uint8_t IRQ, int Status)
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{
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for (uint64_t i = 0; i < ((ACPI::MADT *)PowerManager->GetMADT())->iso.size(); i++)
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if (((ACPI::MADT *)PowerManager->GetMADT())->iso[i]->IRQSource == IRQ)
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{
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debug("[ISO %d] Mapping to source IRQ%#d GSI:%#lx on CPU %d",
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i, ((ACPI::MADT *)PowerManager->GetMADT())->iso[i]->IRQSource, ((ACPI::MADT *)PowerManager->GetMADT())->iso[i]->GSI, CPU);
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this->RawRedirectIRQ(((ACPI::MADT *)PowerManager->GetMADT())->iso[i]->IRQSource + 0x20, ((ACPI::MADT *)PowerManager->GetMADT())->iso[i]->GSI, ((ACPI::MADT *)PowerManager->GetMADT())->iso[i]->Flags, CPU, Status);
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return;
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}
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debug("Mapping IRQ%d on CPU %d", IRQ, CPU);
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this->RawRedirectIRQ(IRQ + 0x20, IRQ, 0, CPU, Status);
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}
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void APIC::RedirectIRQs(int CPU)
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{
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SmartCriticalSection(APICLock);
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debug("Redirecting IRQs...");
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for (int i = 0; i < 16; i++)
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this->RedirectIRQ(CPU, i, 1);
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debug("Redirecting IRQs completed.");
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}
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APIC::APIC(int Core)
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{
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SmartCriticalSection(APICLock);
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APIC_BASE BaseStruct = {.raw = rdmsr(MSR_APIC_BASE)};
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uint64_t BaseLow = BaseStruct.ApicBaseLo;
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uint64_t BaseHigh = BaseStruct.ApicBaseHi;
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this->APICBaseAddress = BaseLow << 12u | BaseHigh << 32u;
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trace("APIC Address: %#lx", this->APICBaseAddress);
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bool x2APICSupported = false;
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if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
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{
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#if defined(a64)
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CPU::x64::AMD::CPUID0x1 cpuid1amd;
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#elif defined(a32)
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CPU::x32::AMD::CPUID0x1 cpuid1amd;
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#endif
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#if defined(a64) || defined(a32)
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asmv("cpuid"
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: "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw)
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: "a"(0x1));
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#endif
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// FIXME: Not sure if I configured this correctly or something else is wrong
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// x2APICSupported = cpuid1amd.ECX.x2APIC;
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fixme("AMD does even support x2APIC? ECX->Reserved10: %#lx", cpuid1amd.ECX.Reserved10);
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}
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else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
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{
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#if defined(a64)
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CPU::x64::Intel::CPUID0x1 cpuid1intel;
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#elif defined(a32)
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CPU::x32::Intel::CPUID0x1 cpuid1intel;
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#endif
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#if defined(a64) || defined(a32)
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asmv("cpuid"
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: "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw)
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: "a"(0x1));
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#endif
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x2APICSupported = cpuid1intel.ECX.x2APIC;
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}
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if (x2APICSupported)
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{
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this->x2APICSupported = true;
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wrmsr(MSR_APIC_BASE, (rdmsr(MSR_APIC_BASE) | (1 << 11)) & ~(1 << 10));
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BaseStruct.EN = 1;
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wrmsr(MSR_APIC_BASE, BaseStruct.raw);
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}
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else
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{
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BaseStruct.EN = 1;
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wrmsr(MSR_APIC_BASE, BaseStruct.raw);
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}
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this->Write(APIC_TPR, 0x0);
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// this->Write(APIC_SVR, this->Read(APIC_SVR) | 0x100); // 0x1FF or 0x100 ? on https://wiki.osdev.org/APIC is 0x100
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if (!this->x2APICSupported)
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{
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this->Write(APIC_DFR, 0xF0000000);
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this->Write(APIC_LDR, this->Read(APIC_ID));
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}
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ACPI::MADT *madt = (ACPI::MADT *)PowerManager->GetMADT();
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for (size_t i = 0; i < madt->nmi.size(); i++)
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{
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if (madt->nmi[i]->processor != 0xFF && Core != madt->nmi[i]->processor)
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return;
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uint32_t nmi = 0x402;
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if (madt->nmi[i]->flags & 2)
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nmi |= 1 << 13;
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if (madt->nmi[i]->flags & 8)
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nmi |= 1 << 15;
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if (madt->nmi[i]->lint == 0)
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this->Write(APIC_LINT0, nmi);
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else if (madt->nmi[i]->lint == 1)
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this->Write(APIC_LINT1, nmi);
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}
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// Setup the spurrious interrupt vector
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Spurious Spurious = {.raw = this->Read(APIC_SVR)};
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Spurious.Vector = IRQ223; // TODO: Should I map the IRQ to something?
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Spurious.Software = 1;
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this->Write(APIC_SVR, Spurious.raw);
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static int once = 0;
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if (!once++)
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{
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// Disable PIT
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outb(0x43, 0x28);
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outb(0x40, 0x0);
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// Disable PIC
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outb(0x21, 0xFF);
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outb(0xA1, 0xFF);
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}
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}
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APIC::~APIC() {}
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void Timer::OnInterruptReceived(TrapFrame *Frame) { UNUSED(Frame); }
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void Timer::OneShot(uint32_t Vector, uint64_t Miliseconds)
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{
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SmartCriticalSection(APICLock);
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LVTTimer timer = {.raw = 0};
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timer.Vector = Vector;
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timer.TimerMode = 0;
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if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_TCG) != 0)
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this->lapic->Write(APIC_TDCR, DivideBy128);
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else
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this->lapic->Write(APIC_TDCR, DivideBy16);
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this->lapic->Write(APIC_TICR, Ticks * Miliseconds);
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this->lapic->Write(APIC_TIMER, timer.raw);
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}
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Timer::Timer(APIC *apic) : Interrupts::Handler(IRQ0)
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{
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SmartCriticalSection(APICLock);
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this->lapic = apic;
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LVTTimerDivide Divider = DivideBy16;
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trace("Initializing APIC timer on CPU %d", GetCurrentCPU()->ID);
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this->lapic->Write(APIC_TDCR, Divider);
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this->lapic->Write(APIC_TICR, 0xFFFFFFFF);
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TimeManager->Sleep(1);
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// Mask the timer
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this->lapic->Write(APIC_TIMER, 0x10000 /* LVTTimer.Mask flag */);
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Ticks = 0xFFFFFFFF - this->lapic->Read(APIC_TCCR);
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// Config for IRQ0 timer
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LVTTimer timer = {.raw = 0};
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timer.Vector = IRQ0;
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timer.Mask = Unmasked;
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timer.TimerMode = LVTTimerMode::OneShot;
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// Initialize APIC timer
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this->lapic->Write(APIC_TDCR, Divider);
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this->lapic->Write(APIC_TICR, Ticks);
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this->lapic->Write(APIC_TIMER, timer.raw);
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trace("%d APIC Timer %d ticks in.", GetCurrentCPU()->ID, Ticks);
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KPrint("APIC Timer: \e8888FF%ld\eCCCCCC ticks.", Ticks);
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}
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Timer::~Timer()
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{
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}
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}
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