mirror of
https://github.com/EnderIce2/Fennix.git
synced 2025-05-28 15:34:31 +00:00
486 lines
11 KiB
C++
486 lines
11 KiB
C++
/*
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This file is part of Fennix Kernel.
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Fennix Kernel is free software: you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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Fennix Kernel is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <driver.hpp>
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#include <cpu.hpp>
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#include <pci.hpp>
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#include <net/net.hpp>
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#include "e1000.hpp"
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extern Driver::Manager *DriverManager;
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extern PCI::Manager *PCIManager;
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namespace Driver::E1000
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{
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dev_t DriverID;
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class E1000Device
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{
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private:
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PCI::PCIHeader0 *Header;
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uint16_t DeviceID;
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bool Initialized = false;
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bool EEPROMAvailable = false;
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struct BARData
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{
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uint8_t Type;
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uint16_t IOBase;
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uint64_t MemoryBase;
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} BAR;
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#define E1000_NUM_RX_DESC 32
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#define E1000_NUM_TX_DESC 8
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RXDescriptor *RX[E1000_NUM_RX_DESC];
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TXDescriptor *TX[E1000_NUM_TX_DESC];
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uint16_t RXCurrent;
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uint16_t TXCurrent;
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const int BaseBufferSize = 8192;
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const int AdditionalBytes = 16;
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uint32_t CurrentPacket;
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void WriteCMD(uint16_t Address, uint32_t Value)
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{
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if (BAR.Type == 0)
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mmoutl((void *)(BAR.MemoryBase + Address), Value);
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else
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{
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outl(BAR.IOBase, Address);
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outl(BAR.IOBase + 4, Value);
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}
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}
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uint32_t ReadCMD(uint16_t Address)
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{
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if (BAR.Type == 0)
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return mminl((void *)(BAR.MemoryBase + Address));
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else
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{
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outl(BAR.IOBase, Address);
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return inl(BAR.IOBase + 0x4);
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}
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}
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uint32_t ReadEEPROM(uint8_t Address)
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{
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uint16_t Data = 0;
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uint32_t temp = 0;
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if (EEPROMAvailable)
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{
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WriteCMD(REG::EEPROM, (1) | ((uint32_t)(Address) << 8));
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while (!((temp = ReadCMD(REG::EEPROM)) & (1 << 4)))
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;
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}
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else
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{
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WriteCMD(REG::EEPROM, (1) | ((uint32_t)(Address) << 2));
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while (!((temp = ReadCMD(REG::EEPROM)) & (1 << 1)))
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;
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}
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Data = (uint16_t)((temp >> 16) & 0xFFFF);
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return Data;
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}
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void InitializeRX()
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{
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debug("Initializing RX...");
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uintptr_t Ptr = (uintptr_t)v0::AllocateMemory(DriverID,
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TO_PAGES(sizeof(RXDescriptor) *
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E1000_NUM_RX_DESC +
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AdditionalBytes));
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for (int i = 0; i < E1000_NUM_RX_DESC; i++)
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{
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RX[i] = (RXDescriptor *)(Ptr + i * 16);
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RX[i]->Address = (uint64_t)v0::AllocateMemory(DriverID,
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TO_PAGES(BaseBufferSize + AdditionalBytes));
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RX[i]->Status = 0;
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}
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#pragma GCC diagnostic ignored "-Wshift-count-overflow"
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WriteCMD(REG::TXDESCLO, (uint32_t)(Ptr >> 32));
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WriteCMD(REG::TXDESCHI, (uint32_t)(Ptr & 0xFFFFFFFF));
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WriteCMD(REG::RXDESCLO, (uint32_t)Ptr);
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WriteCMD(REG::RXDESCHI, 0);
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WriteCMD(REG::RXDESCLEN, E1000_NUM_RX_DESC * 16);
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WriteCMD(REG::RXDESCHEAD, 0);
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WriteCMD(REG::RXDESCTAIL, E1000_NUM_RX_DESC - 1);
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RXCurrent = 0;
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WriteCMD(REG::RCTRL, RCTL::EN | RCTL::SBP | RCTL::UPE |
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RCTL::MPE | RCTL::LBM_NONE |
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RTCL::RDMTS_HALF | RCTL::BAM |
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RCTL::SECRC | RCTL::BSIZE_8192);
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}
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void InitializeTX()
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{
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debug("Initializing TX...");
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uintptr_t Ptr = (uintptr_t)v0::AllocateMemory(DriverID,
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TO_PAGES(sizeof(TXDescriptor) *
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E1000_NUM_RX_DESC +
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AdditionalBytes));
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for (short i = 0; i < E1000_NUM_TX_DESC; i++)
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{
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TX[i] = (TXDescriptor *)((uintptr_t)Ptr + i * 16);
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TX[i]->Address = 0;
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TX[i]->Command = 0;
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TX[i]->Status = TSTA::DD;
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}
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WriteCMD(REG::TXDESCHI, (uint32_t)((uint64_t)Ptr >> 32));
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WriteCMD(REG::TXDESCLO, (uint32_t)((uint64_t)Ptr & 0xFFFFFFFF));
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WriteCMD(REG::TXDESCLEN, E1000_NUM_TX_DESC * 16);
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WriteCMD(REG::TXDESCHEAD, 0);
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WriteCMD(REG::TXDESCTAIL, 0);
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TXCurrent = 0;
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WriteCMD(REG::TCTRL, TCTL::EN_ | TCTL::PSP |
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(15 << TCTL::CT_SHIFT) |
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(64 << TCTL::COLD_SHIFT) |
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TCTL::RTLC);
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WriteCMD(REG::TCTRL, 0b0110000000000111111000011111010);
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WriteCMD(REG::TIPG, 0x0060200A);
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}
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public:
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dev_t ID;
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bool IsInitialized() { return Initialized; }
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size_t write(uint8_t *Buffer, size_t Size)
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{
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TX[TXCurrent]->Address = (uint64_t)Buffer;
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TX[TXCurrent]->Length = (uint16_t)Size;
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TX[TXCurrent]->Command = CMD::EOP | CMD::IFCS | CMD::RS;
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TX[TXCurrent]->Status = 0;
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uint16_t OldTXCurrent = TXCurrent;
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TXCurrent = (uint16_t)((TXCurrent + 1) % E1000_NUM_TX_DESC);
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WriteCMD(REG::TXDESCTAIL, TXCurrent);
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while (!(TX[OldTXCurrent]->Status & 0xFF))
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v0::Yield(DriverID);
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return Size;
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}
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MediaAccessControl GetMAC()
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{
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MediaAccessControl mac;
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if (EEPROMAvailable)
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{
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uint32_t temp;
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temp = ReadEEPROM(0);
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mac.Address[0] = temp & 0xff;
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mac.Address[1] = (uint8_t)(temp >> 8);
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temp = ReadEEPROM(1);
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mac.Address[2] = temp & 0xff;
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mac.Address[3] = (uint8_t)(temp >> 8);
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temp = ReadEEPROM(2);
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mac.Address[4] = temp & 0xff;
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mac.Address[5] = (uint8_t)(temp >> 8);
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}
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else
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{
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uint8_t *BaseMac8 = (uint8_t *)(BAR.MemoryBase + 0x5400);
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uint32_t *BaseMac32 = (uint32_t *)(BAR.MemoryBase + 0x5400);
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if (BaseMac32[0] != 0)
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for (int i = 0; i < 6; i++)
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mac.Address[i] = BaseMac8[i];
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else
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{
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trace("No MAC address found.");
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return MediaAccessControl();
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}
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}
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return mac;
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}
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int ioctl(NetIoctl req, void *arg)
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{
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switch (req)
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{
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case IOCTL_NET_GET_MAC:
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{
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MediaAccessControl mac = GetMAC();
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*((uint48_t *)arg) = mac.ToHex(); /* UNTESTED */
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return 0;
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}
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default:
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return -EINVAL;
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}
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return 0;
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}
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void OnInterruptReceived(CPU::TrapFrame *)
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{
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WriteCMD(REG::IMASK, 0x1);
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uint32_t status = ReadCMD(0xC0);
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UNUSED(status);
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while ((RX[RXCurrent]->Status & 0x1))
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{
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uint8_t *data = (uint8_t *)RX[RXCurrent]->Address;
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uint16_t dataSz = RX[RXCurrent]->Length;
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// ReportNetworkPacket(ID, data, dataSz);
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/* FIXME: Implement */
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trace("FIXME: Received packet");
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(void)data;
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(void)dataSz;
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RX[RXCurrent]->Status = 0;
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uint16_t OldRXCurrent = RXCurrent;
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RXCurrent = (uint16_t)((RXCurrent + 1) % E1000_NUM_RX_DESC);
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WriteCMD(REG::RXDESCTAIL, OldRXCurrent);
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}
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}
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void Panic()
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{
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WriteCMD(REG::IMASK, 0x00000000);
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WriteCMD(REG::ITR, 0x00000000);
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WriteCMD(REG::IAM, 0x00000000);
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}
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E1000Device(PCI::PCIHeader0 *_Header, uint16_t _DeviceID)
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: Header(_Header),
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DeviceID(_DeviceID)
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{
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uint32_t PCIBAR0 = Header->BAR0;
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uint32_t PCIBAR1 = Header->BAR1;
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BAR.Type = PCIBAR0 & 1;
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BAR.IOBase = (uint16_t)(PCIBAR0 & (~3));
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BAR.MemoryBase = PCIBAR1 & (~15);
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switch (DeviceID)
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{
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case 0x100E:
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{
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trace("Found Intel 82540EM Gigabit Ethernet Controller.");
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/* Detect EEPROM */
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WriteCMD(REG::EEPROM, 0x1);
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for (int i = 0; i < 1000 && !EEPROMAvailable; i++)
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if (ReadCMD(REG::EEPROM) & 0x10)
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EEPROMAvailable = true;
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else
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EEPROMAvailable = false;
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if (!GetMAC().Valid())
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{
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trace("Failed to get MAC");
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return;
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}
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/* Start link */
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uint32_t cmdret = ReadCMD(REG::CTRL);
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WriteCMD(REG::CTRL, cmdret | ECTRL::SLU);
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for (int i = 0; i < 0x80; i++)
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WriteCMD((uint16_t)(0x5200 + i * 4), 0);
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WriteCMD(REG::IMASK, 0x1F6DC);
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WriteCMD(REG::IMASK, 0xFF & ~4);
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ReadCMD(0xC0);
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InitializeRX();
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InitializeTX();
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break;
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}
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default:
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{
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trace("Unimplemented E1000 device.");
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return;
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}
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}
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Initialized = true;
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}
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~E1000Device()
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{
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if (!Initialized)
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return;
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switch (DeviceID)
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{
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case 0x100E:
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{
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// Clearing Enable bit in Receive Control Register
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uint32_t cmdret = ReadCMD(REG::RCTRL);
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WriteCMD(REG::RCTRL, cmdret & ~RCTL::EN);
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// Masking Interrupt Mask, Interrupt Throttling Rate & Interrupt Auto-Mask
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WriteCMD(REG::IMASK, 0x00000000);
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WriteCMD(REG::ITR, 0x00000000);
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WriteCMD(REG::IAM, 0x00000000);
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// Clearing SLU bit in Device Control Register
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cmdret = ReadCMD(REG::CTRL);
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WriteCMD(REG::CTRL, cmdret & ~ECTRL::SLU);
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// Clear the Interrupt Cause Read register by reading it
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ReadCMD(REG::ICR);
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// Powering down the device (?)
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WriteCMD(REG::CTRL, PCTRL::POWER_DOWN);
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/* TODO: Stop link; further testing required */
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break;
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}
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default:
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{
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trace("Unimplemented E1000 device.");
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return;
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}
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}
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((PCI::PCIDeviceHeader *)Header)->Command |= PCI::PCI_COMMAND_INTX_DISABLE;
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}
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};
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std::unordered_map<dev_t, E1000Device *> Drivers;
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int Open(struct Inode *, int, mode_t)
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{
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return 0;
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}
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int Close(struct Inode *)
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{
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return 0;
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}
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ssize_t Read(struct Inode *, void *, size_t, off_t)
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{
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return 0;
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}
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ssize_t Write(struct Inode *Node, const void *Buffer, size_t Size, off_t)
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{
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return Drivers[Node->GetMinor()]->write((uint8_t *)Buffer, Size);
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}
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int Ioctl(struct Inode *Node, unsigned long Request, void *Argp)
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{
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return Drivers[Node->GetMinor()]->ioctl((NetIoctl)Request, Argp);
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}
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const struct InodeOperations ops = {
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.Lookup = nullptr,
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.Create = nullptr,
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.Remove = nullptr,
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.Rename = nullptr,
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.Read = Read,
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.Write = Write,
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.Truncate = nullptr,
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.Open = Open,
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.Close = Close,
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.Ioctl = Ioctl,
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.ReadDir = nullptr,
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.MkDir = nullptr,
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.RmDir = nullptr,
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.SymLink = nullptr,
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.ReadLink = nullptr,
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.Seek = nullptr,
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.Stat = nullptr,
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};
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std::list<PCI::PCIDevice> Devices;
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int Entry()
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{
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for (auto &&dev : Devices)
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{
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PCIManager->InitializeDevice(dev, KernelPageTable);
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E1000Device *e1000 = new E1000Device((PCI::PCIHeader0 *)dev.Header,
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dev.Header->DeviceID);
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if (e1000->IsInitialized())
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{
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dev_t ret = v0::RegisterDevice(DriverID, NETWORK_TYPE_ETHERNET, &ops);
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Drivers[ret] = e1000;
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}
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}
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if (Drivers.empty())
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{
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trace("No valid E1000 device found.");
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return -EINVAL;
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}
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return 0;
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}
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int Final()
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{
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for (auto &&dev : Drivers)
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{
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dev_t ret = dev.first;
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v0::UnregisterDevice(DriverID, ret);
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delete dev.second;
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}
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return 0;
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}
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int Panic()
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{
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for (auto &&i : Drivers)
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i.second->Panic();
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return 0;
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}
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int Probe()
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{
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Devices = PCIManager->FindPCIDevice(
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{
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0x8086, /* Intel */
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},
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{
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0x100E, /* 82540EM */
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0x100F, /* 82545EM */
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0x10D3, /* 82574L */
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0x10EA, /* I217-LM */
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0x153A, /* 82577LM */
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});
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if (Devices.empty())
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{
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trace("No E1000 device found.");
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return -ENODEV;
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}
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return 0;
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}
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REGISTER_BUILTIN_DRIVER(e1000,
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"Intel(R) PRO/1000 Network Driver",
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"enderice2",
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1, 0, 0,
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Entry,
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Final,
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Panic,
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Probe);
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}
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