mirror of
https://github.com/EnderIce2/Fennix.git
synced 2025-05-25 22:14:34 +00:00
439 lines
9.4 KiB
C++
439 lines
9.4 KiB
C++
/*
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This file is part of Fennix Kernel.
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Fennix Kernel is free software: you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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Fennix Kernel is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef __FENNIX_KERNEL_ACPI_H__
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#define __FENNIX_KERNEL_ACPI_H__
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#include <types.h>
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#include <unordered_map>
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#include <boot/binfo.h>
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#include <ints.hpp>
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#include <cpu.hpp>
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#include <vector>
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namespace ACPI
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{
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class ACPI
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{
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public:
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struct ACPIHeader
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{
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unsigned char Signature[4];
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uint32_t Length;
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uint8_t Revision;
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uint8_t Checksum;
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uint8_t OEMID[6];
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uint8_t OEMTableID[8];
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uint32_t OEMRevision;
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uint32_t CreatorID;
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uint32_t CreatorRevision;
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} __packed;
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struct GenericAddressStructure
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{
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uint8_t AddressSpace;
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uint8_t BitWidth;
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uint8_t BitOffset;
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uint8_t AccessSize;
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uint64_t Address;
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} __packed;
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enum DBG2PortType
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{
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TYPE_SERIAL = 0x8000,
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TYPE_1394 = 0x8001,
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TYPE_USB = 0x8002,
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TYPE_NET = 0x8003
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};
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enum DBG2PortSubtype
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{
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SUBTYPE_SERIAL_16550_COMPATIBLE = 0x0000,
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SUBTYPE_SERIAL_16550_SUBSET = 0x0001,
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SUBTYPE_SERIAL_MAX311xE_SPI_UART = 0x0002,
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SUBTYPE_SERIAL_Arm_PL011_UART = 0x0003,
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SUBTYPE_SERIAL_MSM8x60 = 0x0004,
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SUBTYPE_SERIAL_Nvidia_16550 = 0x0005,
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SUBTYPE_SERIAL_TI_OMAP = 0x0006,
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SUBTYPE_SERIAL_APM88xxxx = 0x0008,
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SUBTYPE_SERIAL_MSM8974 = 0x0009,
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SUBTYPE_SERIAL_SAM5250 = 0x000A,
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SUBTYPE_SERIAL_Intel_USIF = 0x000B,
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SUBTYPE_SERIAL_iMX6 = 0x000C,
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SUBTYPE_SERIAL_Arm_SBSA_UART = 0x000D,
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SUBTYPE_SERIAL_Arm_SBSA_Generic_UART = 0x000E,
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SUBTYPE_SERIAL_Arm_DCC = 0x000F,
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SUBTYPE_SERIAL_BCM2835 = 0x0010,
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SUBTYPE_SERIAL_SDM845_At_1_8432MHz = 0x0011,
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SUBTYPE_SERIAL_16550_With_Generic_Address_Structure = 0x0012,
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SUBTYPE_SERIAL_SDM845_At_7_372MHz = 0x0013,
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SUBTYPE_SERIAL_Intel_LPSS = 0x0014,
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SUBTYPE_SERIAL_RISC_V_SBI_Console = 0x0015,
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SUBTYPE_1394_IEEE1394_HCI = 0x0000,
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SUBTYPE_USB_XHCI = 0x0000,
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SUBTYPE_USB_EHCI = 0x0001,
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SUBTYPE_NET_NNNN = 0x0000,
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};
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struct DBG2Device
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{
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uint8_t Revision;
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uint16_t Length;
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uint8_t NumberofGenericAddressRegisters;
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uint16_t NamespaceStringLength;
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uint16_t NamespaceStringOffset;
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uint16_t OemDataLength;
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uint16_t OemDataOffset;
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uint16_t PortType;
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uint16_t PortSubtype;
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uint16_t Reserved;
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uint16_t BaseAddressRegisterOffset;
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uint16_t AddressSizeOffset;
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/* BaseAddressRegister[NumberofGenericAddressRegisters * 12] at offset BaseAddressRegisterOffset */
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/* AddressSize[NumberofGenericAddressRegisters * 4] at offset AddressSizeOffset */
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/* NamespaceString[NamespaceStringLength] at offset NamespaceStringOffset */
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/* OemData[OemDataLength] at offset OemDataOffset */
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} __packed;
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struct MCFGHeader
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{
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struct ACPIHeader Header;
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uint64_t Reserved;
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} __packed;
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struct HPETHeader
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{
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ACPIHeader Header;
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uint8_t HardwareRevID;
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uint8_t ComparatorCount : 5;
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uint8_t CounterSize : 1;
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uint8_t Reserved : 1;
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uint8_t LegacyReplacement : 1;
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uint16_t PCIVendorID;
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struct GenericAddressStructure Address;
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uint8_t HPETNumber;
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uint16_t MinimumTick;
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uint8_t PageProtection;
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} __packed;
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struct FADTHeader
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{
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ACPIHeader Header;
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uint32_t FirmwareCtrl;
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uint32_t Dsdt;
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uint8_t Reserved;
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uint8_t PreferredPowerManagementProfile;
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uint16_t SCI_Interrupt;
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uint32_t SMI_CommandPort;
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uint8_t AcpiEnable;
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uint8_t AcpiDisable;
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uint8_t S4BIOS_REQ;
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uint8_t PSTATE_Control;
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uint32_t PM1aEventBlock;
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uint32_t PM1bEventBlock;
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uint32_t PM1aControlBlock;
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uint32_t PM1bControlBlock;
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uint32_t PM2ControlBlock;
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uint32_t PMTimerBlock;
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uint32_t GPE0Block;
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uint32_t GPE1Block;
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uint8_t PM1EventLength;
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uint8_t PM1ControlLength;
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uint8_t PM2ControlLength;
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uint8_t PMTimerLength;
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uint8_t GPE0Length;
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uint8_t GPE1Length;
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uint8_t GPE1Base;
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uint8_t CStateControl;
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uint16_t WorstC2Latency;
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uint16_t WorstC3Latency;
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uint16_t FlushSize;
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uint16_t FlushStride;
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uint8_t DutyOffset;
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uint8_t DutyWidth;
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uint8_t DayAlarm;
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uint8_t MonthAlarm;
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uint8_t Century;
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uint16_t BootArchitectureFlags;
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uint8_t Reserved2;
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uint32_t Flags;
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struct GenericAddressStructure ResetReg;
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uint8_t ResetValue;
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uint8_t Reserved3[3];
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uint64_t X_FirmwareControl;
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uint64_t X_Dsdt;
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struct GenericAddressStructure X_PM1aEventBlock;
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struct GenericAddressStructure X_PM1bEventBlock;
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struct GenericAddressStructure X_PM1aControlBlock;
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struct GenericAddressStructure X_PM1bControlBlock;
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struct GenericAddressStructure X_PM2ControlBlock;
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struct GenericAddressStructure X_PMTimerBlock;
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struct GenericAddressStructure X_GPE0Block;
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struct GenericAddressStructure X_GPE1Block;
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} __packed;
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struct BGRTHeader
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{
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ACPIHeader Header;
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/**
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* Version. This value must be 1.
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*/
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uint16_t Version;
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/**
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* Status of the image
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*/
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union
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{
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struct
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{
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/**
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* Indicates that the image graphic is displayed.
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*/
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uint8_t Displayed : 1;
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/**
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* Orientation
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*
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* 0b00 - 0˚
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* 0b01 - 90˚
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* 0b10 - 180˚
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* 0b11 - 270˚
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*/
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uint8_t OrientationOffset : 2;
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/**
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* This field is reserved and must be zero.
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*/
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uint8_t Reserved : 5;
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};
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uint8_t raw;
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} Status;
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/**
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* Image type
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*
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* 0 - Bitmap
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* 1-255 - Reserved
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*/
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uint8_t ImageType;
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/**
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* Physical address of the image pointing to firmware's in-memory copy of the image bitmap.
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*/
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uint64_t ImageAddress;
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/**
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* X-offset of the boot image.
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*/
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uint32_t ImageOffsetX;
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/**
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* Y-offset of the boot image.
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*/
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uint32_t ImageOffsetY;
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} __packed;
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struct SRATHeader
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{
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ACPIHeader Header;
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uint32_t TableRevision; // Must be value 1
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uint64_t Reserved; // Reserved, must be zero
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} __packed;
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struct TPM2Header
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{
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ACPIHeader Header;
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uint32_t Flags;
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uint64_t ControlAddress;
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uint32_t StartMethod;
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} __packed;
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struct TCPAHeader
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{
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ACPIHeader Header;
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uint16_t Reserved;
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uint32_t MaxLogLength;
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uint64_t LogAddress;
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} __packed;
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struct WAETHeader
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{
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ACPIHeader Header;
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uint32_t Flags;
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} __packed;
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struct HESTHeader
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{
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ACPIHeader Header;
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uint32_t ErrorSourceCount;
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} __packed;
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struct MADTHeader
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{
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ACPIHeader Header;
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uint32_t LocalControllerAddress;
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uint32_t Flags;
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char Entries[];
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} __packed;
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struct SSDTHeader
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{
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ACPIHeader Header;
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char DefinitionBlock[];
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} __packed;
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struct DBGPHeader
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{
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ACPIHeader Header;
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/**
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* 0 - 16550 compatible
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* 1 - Subset of 16550
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*/
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uint8_t InterfaceType;
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uint8_t Reserved[3];
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GenericAddressStructure BaseAddress;
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} __packed;
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struct DBG2Header
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{
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ACPIHeader Header;
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uint32_t OffsetDbgDeviceInfo;
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uint32_t NumberDbgDeviceInfo;
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/* DBG2Device[NumberDbgDeviceInfo] at offset OffsetDbgDeviceInfo */
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} __packed;
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ACPIHeader *XSDT = nullptr;
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MCFGHeader *MCFG = nullptr;
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HPETHeader *HPET = nullptr;
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FADTHeader *FADT = nullptr;
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BGRTHeader *BGRT = nullptr;
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SRATHeader *SRAT = nullptr;
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TPM2Header *TPM2 = nullptr;
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TCPAHeader *TCPA = nullptr;
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WAETHeader *WAET = nullptr;
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MADTHeader *MADT = nullptr;
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HESTHeader *HEST = nullptr;
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SSDTHeader *SSDT = nullptr;
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DBGPHeader *DBGP = nullptr;
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DBG2Header *DBG2 = nullptr;
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bool XSDTSupported = false;
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std::unordered_map<const char *, ACPIHeader *> Tables;
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void *FindTable(ACPIHeader *ACPIHeader, char *Signature);
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void SearchTables(ACPIHeader *Header);
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ACPI();
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~ACPI();
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};
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class MADT
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{
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public:
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struct APICHeader
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{
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uint8_t Type;
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uint8_t Length;
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} __packed;
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struct MADTIOApic
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{
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struct APICHeader Header;
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uint8_t APICID;
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uint8_t reserved;
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uint32_t Address;
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uint32_t GSIBase;
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} __packed;
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struct MADTIso
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{
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struct APICHeader Header;
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uint8_t BuSSource;
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uint8_t IRQSource;
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uint32_t GSI;
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uint16_t Flags;
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} __packed;
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struct MADTNmi
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{
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struct APICHeader Header;
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uint8_t processor;
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uint16_t flags;
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uint8_t lint;
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} __packed;
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struct LocalAPIC
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{
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struct APICHeader Header;
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uint8_t ACPIProcessorId;
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uint8_t APICId;
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uint32_t Flags;
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} __packed;
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struct LAPIC
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{
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uint8_t id;
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uintptr_t PhysicalAddress;
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void *VirtualAddress;
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};
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std::vector<MADTIOApic *> ioapic;
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std::vector<MADTIso *> iso;
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std::vector<MADTNmi *> nmi;
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std::vector<LocalAPIC *> lapic;
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struct LAPIC *LAPICAddress;
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uint16_t CPUCores;
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MADT(ACPI::MADTHeader *madt);
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~MADT();
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};
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class DSDT : public Interrupts::Handler
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{
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private:
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uint32_t SMI_CMD = 0;
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uint8_t ACPI_ENABLE = 0;
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uint8_t ACPI_DISABLE = 0;
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uint32_t PM1a_CNT = 0;
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uint32_t PM1b_CNT = 0;
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uint16_t SLP_TYPa = 0;
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uint16_t SLP_TYPb = 0;
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uint16_t SLP_EN = 0;
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uint16_t SCI_EN = 0;
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uint8_t PM1_CNT_LEN = 0;
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ACPI *acpi;
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void OnInterruptReceived(CPU::TrapFrame *Frame);
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public:
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bool ACPIShutdownSupported = false;
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void Reboot();
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void Shutdown();
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DSDT(ACPI *acpi);
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~DSDT();
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};
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}
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#endif // !__FENNIX_KERNEL_ACPI_H__
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