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APIC implementation (not working as expected)

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This commit is contained in:
Alex
2022-10-17 04:05:44 +03:00
parent c5b4666b50
commit c944f57a3b
15 changed files with 272 additions and 153 deletions
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94
Architecture/amd64/cpu/AdvancedProgrammableInterruptController.cpp
View File

@ -1,7 +1,9 @@
#include "apic.hpp"
#include <memory.hpp>
#include <cpu.hpp>
#include <smp.hpp>
#include <io.h>
#include "../../../kernel.h"
#include "../acpi.hpp"
@ -33,14 +35,7 @@ namespace APIC
uint32_t APIC::Read(uint32_t Register)
{
// Too repetitive
if (Register != APIC_EOI &&
Register != APIC_ID &&
Register != APIC_TIMER &&
Register != APIC_TDCR &&
Register != APIC_TICR &&
Register != APIC_TCCR)
debug("APIC::Read(%#lx)", Register);
debug("APIC::Read(%#lx)", Register);
if (x2APICSupported)
{
if (Register != APIC_ICRHI)
@ -54,13 +49,7 @@ namespace APIC
void APIC::Write(uint32_t Register, uint32_t Value)
{
// Too repetitive
if (Register != APIC_EOI &&
Register != APIC_TIMER &&
Register != APIC_TDCR &&
Register != APIC_TICR &&
Register != APIC_TCCR)
debug("APIC::Write(%#lx, %#lx)", Register, Value);
debug("APIC::Write(%#lx, %#lx)", Register, Value);
if (x2APICSupported)
{
if (Register != APIC_ICRHI)
@ -176,7 +165,7 @@ namespace APIC
this->RawRedirectIRQ(IRQ + 0x20, IRQ, 0, CPU, Status);
}
APIC::APIC()
APIC::APIC(int Core)
{
uint32_t rcx;
CPU::x64::cpuid(1, 0, 0, &rcx, 0);
@ -195,9 +184,82 @@ namespace APIC
this->Write(APIC_TPR, 0x0);
this->Write(APIC_SVR, this->Read(APIC_SVR) | 0x100); // 0x1FF or 0x100 ? on https://wiki.osdev.org/APIC is 0x100
if (!this->x2APICSupported)
{
this->Write(APIC_DFR, 0xF0000000);
this->Write(APIC_LDR, this->Read(APIC_ID));
}
ACPI::MADT *madt = (ACPI::MADT *)PowerManager->GetMADT();
for (size_t i = 0; i < madt->nmi.size(); i++)
{
if (madt->nmi[i]->processor != 0xFF && Core != madt->nmi[i]->processor)
return;
uint32_t nmi = 0x402;
if (madt->nmi[i]->flags & 2)
nmi |= 1 << 13;
if (madt->nmi[i]->flags & 8)
nmi |= 1 << 15;
if (madt->nmi[i]->lint == 0)
this->Write(0x350, nmi);
else if (madt->nmi[i]->lint == 1)
this->Write(0x360, nmi);
}
}
APIC::~APIC()
{
}
void Timer::OnInterruptReceived(CPU::x64::TrapFrame *Frame)
{
fixme("APIC IRQ0 INTERRUPT RECEIVED ON CPU %d", CPU::x64::rdmsr(CPU::x64::MSR_FS_BASE));
}
Timer::Timer(APIC *apic) : Interrupts::Handler(CPU::x64::IRQ0)
{
trace("Initializing APIC timer on CPU %d", CPU::x64::rdmsr(CPU::x64::MSR_FS_BASE));
apic->Write(APIC::APIC::APIC_TDCR, 0x3);
int IOIn = inb(0x61);
IOIn = (IOIn & 0xFD) | 1;
outb(0x61, IOIn);
outb(0x43, 0b10110010);
outb(0x42, 155);
inb(0x60);
outb(0x42, 46);
apic->Write(APIC::APIC::APIC_TICR, 0xFFFFFFFF);
IOIn = inb(0x61);
IOIn = (IOIn & 0xFC);
outb(0x61, IOIn);
IOIn |= 1;
outb(0x61, IOIn);
uint32_t Loop = 0;
while ((inb(0x61) & 0x20) != 0)
++Loop;
apic->Write(APIC::APIC::APIC_TIMER, 0x10000);
outb(0x43, 0x28);
outb(0x40, 0x0);
outb(0x21, 0xFF);
outb(0xA1, 0xFF);
uint64_t ticksIn10ms = 0xFFFFFFFF - apic->Read(APIC::APIC::APIC_TCCR);
apic->Write(APIC::APIC::APIC_TIMER, (long)CPU::x64::IRQ0 | (long)APIC::APIC::APICRegisters::APIC_PERIODIC);
apic->Write(APIC::APIC::APIC_TDCR, 0x3);
apic->Write(APIC::APIC::APIC_TICR, ticksIn10ms);
debug("APIC Timer (CPU %d): %d ticks in 10ms", CPU::x64::rdmsr(CPU::x64::MSR_FS_BASE), ticksIn10ms);
}
Timer::~Timer()
{
}
}

5
Architecture/amd64/cpu/GlobalDescriptorTable.cpp
View File

@ -40,10 +40,7 @@ namespace GlobalDescriptorTable
"1:\n"
"movw $16, %%ax\n"
"movw %%ax, %%ds\n"
"movw %%ax, %%es\n"
"movw $0x1b, %%ax\n"
"movw %%ax, %%fs\n"
"movw %%ax, %%gs\n" ::
"movw %%ax, %%es\n" ::
: "memory", "rax");
uint64_t Base = (uint64_t)&tss[Core];

29
Architecture/amd64/cpu/SymmetricMultiprocessing.cpp
View File

@ -23,6 +23,7 @@ enum SMPTrampolineAddress
STACK = 0x570,
GDT = 0x580,
IDT = 0x590,
CORE = 0x600
};
volatile bool CPUEnabled = false;
@ -36,7 +37,7 @@ CPUData *GetCurrentCPU()
{
uint64_t ret = 0;
#if defined(__amd64__)
ret = ((APIC::APIC *)Interrupts::apic)->Read(APIC::APIC::APIC_ID) >> 24;
ret = CPU::x64::rdmsr(CPU::x64::MSR_FS_BASE);
#elif defined(__i386__)
#elif defined(__aarch64__)
#endif
@ -59,18 +60,14 @@ extern "C" void StartCPU()
{
CPU::Interrupts(CPU::Disable);
CPU::InitializeFeatures();
// Enable APIC
CPU::x64::wrmsr(CPU::x64::MSR_APIC_BASE, (CPU::x64::rdmsr(CPU::x64::MSR_APIC_BASE) | 0x800) & ~(1 << 10));
((APIC::APIC *)Interrupts::apic)->Write(APIC::APIC::APIC_SVR, ((APIC::APIC *)Interrupts::apic)->Read(APIC::APIC::APIC_SVR) | 0x1FF);
uint64_t CPU_ID;
// Set CPU_ID variable using APIC
CPU_ID = ((APIC::APIC *)Interrupts::apic)->Read(APIC::APIC::APIC_ID) >> 24;
uintptr_t CoreID = CORE;
CPU::x64::wrmsr(CPU::x64::MSR_FS_BASE, (int)*reinterpret_cast<int *>(CoreID));
uint64_t CPU_ID = CPU::x64::rdmsr(CPU::x64::MSR_FS_BASE);
// Initialize GDT and IDT
Interrupts::Initialize(CPU_ID);
((APIC::APIC *)Interrupts::apic)->RedirectIRQs(CPU_ID);
Interrupts::Enable(CPU_ID);
Interrupts::InitializeTimer(CPU_ID);
CPU::Interrupts(CPU::Enable);
KPrint("CPU %d is online", CPU_ID);
@ -89,10 +86,11 @@ namespace SMP
}
for (uint8_t i = 0; i < ((ACPI::MADT *)madt)->CPUCores + 1; i++)
{
if ((((APIC::APIC *)Interrupts::apic)->Read(APIC::APIC::APIC_ID) >> 24) != ((ACPI::MADT *)madt)->lapic[i]->ACPIProcessorId)
debug("Initializing CPU %d", i);
if ((((APIC::APIC *)Interrupts::apic[0])->Read(APIC::APIC::APIC_ID) >> 24) != ((ACPI::MADT *)madt)->lapic[i]->ACPIProcessorId)
{
((APIC::APIC *)Interrupts::apic)->Write(APIC::APIC::APIC_ICRHI, (((ACPI::MADT *)madt)->lapic[i]->APICId << 24));
((APIC::APIC *)Interrupts::apic)->Write(APIC::APIC::APIC_ICRLO, 0x500);
((APIC::APIC *)Interrupts::apic[0])->Write(APIC::APIC::APIC_ICRHI, (((ACPI::MADT *)madt)->lapic[i]->APICId << 24));
((APIC::APIC *)Interrupts::apic[0])->Write(APIC::APIC::APIC_ICRLO, 0x500);
Memory::Virtual().Map(0x0, 0x0, Memory::PTFlag::RW | Memory::PTFlag::US);
@ -104,14 +102,15 @@ namespace SMP
POKE(volatile uint64_t, PAGE_TABLE) = CPU::x64::readcr3().raw;
POKE(volatile uint64_t, STACK) = (uint64_t)KernelAllocator.RequestPage();
POKE(volatile uint64_t, CORE) = i;
asm volatile("sgdt [0x580]\n"
"sidt [0x590]\n");
POKE(volatile uint64_t, START_ADDR) = (uintptr_t)&StartCPU;
((APIC::APIC *)Interrupts::apic)->Write(APIC::APIC::APIC_ICRHI, (((ACPI::MADT *)madt)->lapic[i]->APICId << 24));
((APIC::APIC *)Interrupts::apic)->Write(APIC::APIC::APIC_ICRLO, 0x600 | ((uint32_t)TRAMPOLINE_START / PAGE_SIZE));
((APIC::APIC *)Interrupts::apic[0])->Write(APIC::APIC::APIC_ICRHI, (((ACPI::MADT *)madt)->lapic[i]->APICId << 24));
((APIC::APIC *)Interrupts::apic[0])->Write(APIC::APIC::APIC_ICRLO, 0x600 | ((uint32_t)TRAMPOLINE_START / PAGE_SIZE));
while (!CPUEnabled)
;

15
Architecture/amd64/cpu/apic.hpp
View File

@ -3,6 +3,9 @@
#include <types.h>
#include <interrupts.hpp>
#include <cpu.hpp>
namespace APIC
{
class APIC
@ -55,9 +58,19 @@ namespace APIC
uint32_t IOGetMaxRedirect(uint32_t APICID);
void RawRedirectIRQ(uint8_t Vector, uint32_t GSI, uint16_t Flags, int CPU, int Status);
void RedirectIRQ(int CPU, uint8_t IRQ, int Status);
APIC();
APIC(int Core);
~APIC();
};
class Timer : public Interrupts::Handler
{
private:
void OnInterruptReceived(CPU::x64::TrapFrame *Frame);
public:
Timer(APIC *apic);
~Timer();
};
}
#endif // !__FENNIX_KERNEL_APIC_H__