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Update APIC according to Intel manual (2.4.3 Interrupt Command Register)

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This commit is contained in:
Alex 2022-10-25 02:42:12 +03:00
parent 62bd906e61
commit c69496cac1
Signed by untrusted user who does not match committer: enderice2
GPG Key ID: EACC3AD603BAB4DD
2 changed files with 71 additions and 13 deletions
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10
Architecture/amd64/cpu/AdvancedProgrammableInterruptController.cpp
View File

@ -90,7 +90,7 @@ namespace APIC
do do
{ {
icr.raw = this->Read(APIC_ICRLO); icr.raw = this->Read(APIC_ICRLO);
} while (icr.DeliveryStatus != 0); } while (icr.DeliveryStatus != Idle);
} }
void APIC::IPI(uint8_t CPU, InterruptCommandRegisterLow icr) void APIC::IPI(uint8_t CPU, InterruptCommandRegisterLow icr)
@ -121,7 +121,7 @@ namespace APIC
{ {
InterruptCommandRegisterLow icr; InterruptCommandRegisterLow icr;
icr.DeliveryMode = INIT; icr.DeliveryMode = INIT;
icr.Level = 1; icr.Level = Assert;
this->Write(APIC_ICRHI, (CPU << 24)); this->Write(APIC_ICRHI, (CPU << 24));
this->Write(APIC_ICRLO, icr.raw); this->Write(APIC_ICRLO, icr.raw);
this->WaitForIPI(); this->WaitForIPI();
@ -141,7 +141,7 @@ namespace APIC
InterruptCommandRegisterLow icr; InterruptCommandRegisterLow icr;
icr.Vector = StartupAddress >> 12; icr.Vector = StartupAddress >> 12;
icr.DeliveryMode = Startup; icr.DeliveryMode = Startup;
icr.Level = 1; icr.Level = Assert;
this->Write(APIC_ICRHI, (CPU << 24)); this->Write(APIC_ICRHI, (CPU << 24));
this->Write(APIC_ICRLO, icr.raw); this->Write(APIC_ICRLO, icr.raw);
this->WaitForIPI(); this->WaitForIPI();
@ -358,8 +358,8 @@ namespace APIC
// Config for IRQ0 timer // Config for IRQ0 timer
LVTTimer timer = {.raw = 0}; LVTTimer timer = {.raw = 0};
timer.Vector = IRQ0; timer.Vector = IRQ0;
timer.Mask = 0; timer.Mask = Unmasked;
timer.TimerMode = 1; timer.TimerMode = Periodic;
// Initialize APIC timer // Initialize APIC timer
this->lapic->Write(APIC_TDCR, 0x0); this->lapic->Write(APIC_TDCR, 0x0);

74
Architecture/amd64/cpu/apic.hpp
View File

@ -51,13 +51,71 @@ namespace APIC
enum APICDeliveryMode enum APICDeliveryMode
{ {
Fixed = 0, Fixed = 0b000,
LowestPriority = 1, LowestPriority = 0b001, /* Reserved */
SMI = 2, SMI = 0b010,
NMI = 4, APIC_DELIVERY_MODE_RESERVED0 = 0b011, /* Reserved */
INIT = 5, NMI = 0b100,
Startup = 6, INIT = 0b101,
ExtINT = 7 Startup = 0b110,
ExtINT = 0b111 /* Reserved */
};
enum APICDestinationMode
{
Physical = 0b0,
Logical = 0b1
};
enum APICDeliveryStatus
{
Idle = 0b0,
SendPending = 0b1
};
enum APICLevel
{
DeAssert = 0b0,
Assert = 0b1
};
enum APICTriggerMode
{
Edge = 0b0,
Level = 0b1
};
enum APICDestinationShorthand
{
NoShorthand = 0b00,
Self = 0b01,
AllIncludingSelf = 0b10,
AllExcludingSelf = 0b11
};
enum APICTimerDivide
{
DivideBy2 = 0b000,
DivideBy4 = 0b001,
DivideBy8 = 0b010,
DivideBy16 = 0b011,
DivideBy32 = 0b100,
DivideBy64 = 0b101,
DivideBy128 = 0b110,
DivideBy1 = 0b111
};
enum LVTTimerMask
{
Unmasked = 0b0,
Masked = 0b1
};
enum LVTTimerMode
{
OneShot = 0b00,
Periodic = 0b01,
TSCDeadline = 0b10
}; };
typedef union typedef union
@ -218,7 +276,7 @@ namespace APIC
uint64_t DestinationID : 8; uint64_t DestinationID : 8;
}; };
uint64_t raw; uint64_t raw;
} __attribute__((packed)) RedirectEntry; } __attribute__((packed)) IOAPICRedirectEntry;
typedef union typedef union
{ {