mirror of
https://github.com/EnderIce2/Fennix.git
synced 2025-07-20 19:51:43 +00:00
Various QoL changes
This commit is contained in:
Alex
219
Core/CPU.cpp
219
Core/CPU.cpp
@@ -24,6 +24,13 @@
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#include "../kernel.h"
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#if defined(a64)
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using namespace CPU::x64;
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#elif defined(a32)
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using namespace CPU::x32;
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#elif defined(aa64)
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#endif
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namespace CPU
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{
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static bool SSEEnabled = false;
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@@ -199,18 +206,19 @@ namespace CPU
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return PT;
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}
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void InitializeFeatures(long Core)
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struct SupportedFeat
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{
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static int BSP = 0;
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bool PGESupport = false;
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bool SSESupport = false;
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#if defined(a64)
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bool UMIPSupport = false;
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bool SMEPSupport = false;
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bool SMAPSupport = false;
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bool PGE = false;
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bool SSE = false;
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bool UMIP = false;
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bool SMEP = false;
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bool SMAP = false;
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bool FSGSBASE = false;
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};
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x64::CR0 cr0 = x64::readcr0();
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x64::CR4 cr4 = x64::readcr4();
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SupportedFeat GetCPUFeat()
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{
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SupportedFeat feat{};
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if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
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{
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@@ -219,11 +227,12 @@ namespace CPU
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cpuid1.Get();
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cpuid7.Get();
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PGESupport = cpuid1.EDX.PGE;
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SSESupport = cpuid1.EDX.SSE;
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SMEPSupport = cpuid7.EBX.SMEP;
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SMAPSupport = cpuid7.EBX.SMAP;
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UMIPSupport = cpuid7.ECX.UMIP;
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feat.PGE = cpuid1.EDX.PGE;
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feat.SSE = cpuid1.EDX.SSE;
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feat.SMEP = cpuid7.EBX.SMEP;
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feat.SMAP = cpuid7.EBX.SMAP;
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feat.UMIP = cpuid7.ECX.UMIP;
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feat.FSGSBASE = cpuid7.EBX.FSGSBASE;
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}
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else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
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{
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@@ -231,83 +240,94 @@ namespace CPU
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CPU::x86::Intel::CPUID0x00000007_0 cpuid7_0;
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cpuid1.Get();
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cpuid7_0.Get();
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PGESupport = cpuid1.EDX.PGE;
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SSESupport = cpuid1.EDX.SSE;
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SMEPSupport = cpuid7_0.EBX.SMEP;
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SMAPSupport = cpuid7_0.EBX.SMAP;
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UMIPSupport = cpuid7_0.ECX.UMIP;
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feat.PGE = cpuid1.EDX.PGE;
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feat.SSE = cpuid1.EDX.SSE;
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feat.SMEP = cpuid7_0.EBX.SMEP;
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feat.SMAP = cpuid7_0.EBX.SMAP;
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feat.UMIP = cpuid7_0.ECX.UMIP;
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feat.FSGSBASE = cpuid7_0.EBX.FSGSBase;
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}
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return feat;
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}
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void InitializeFeatures(int Core)
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{
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static int BSP = 0;
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SupportedFeat feat = GetCPUFeat();
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CR0 cr0 = readcr0();
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CR4 cr4 = readcr4();
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if (Config.SIMD == false)
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{
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debug("Disabling SSE support...");
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SSESupport = false;
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feat.SSE = false;
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}
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if (PGESupport)
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if (feat.PGE)
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{
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debug("Enabling global pages support...");
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if (!BSP)
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KPrint("Global Pages is supported.");
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cr4.PGE = 1;
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cr4.PGE = true;
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}
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bool SSEEnableAfter = false;
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/* Not sure if my code is not working properly or something else is the issue. */
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if ((strcmp(Hypervisor(), x86_CPUID_VENDOR_VIRTUALBOX) != 0) &&
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SSESupport)
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feat.SSE)
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{
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debug("Enabling SSE support...");
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if (!BSP)
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KPrint("SSE is supported.");
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cr0.EM = 0;
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cr0.MP = 1;
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cr4.OSFXSR = 1;
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cr4.OSXMMEXCPT = 1;
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cr0.EM = false;
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cr0.MP = true;
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cr4.OSFXSR = true;
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cr4.OSXMMEXCPT = true;
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CPUData *CoreData = GetCPU(Core);
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CoreData->Data.FPU.mxcsr = 0b0001111110000000;
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CoreData->Data.FPU.mxcsrmask = 0b1111111110111111;
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CoreData->Data.FPU.fcw = 0b0000001100111111;
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CPU::x64::fxrstor(&CoreData->Data.FPU);
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fxrstor(&CoreData->Data.FPU);
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SSEEnableAfter = true;
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}
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cr0.NW = 0;
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cr0.CD = 0;
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cr0.WP = 1;
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cr0.NW = false;
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cr0.CD = false;
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cr0.WP = true;
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x64::writecr0(cr0);
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writecr0(cr0);
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if (strcmp(Hypervisor(), x86_CPUID_VENDOR_VIRTUALBOX) != 0 &&
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strcmp(Hypervisor(), x86_CPUID_VENDOR_TCG) != 0)
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{
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// FIXME: I don't think this is reporting correctly. This has to be fixed asap.
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debug("Enabling UMIP, SMEP & SMAP support...");
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if (UMIPSupport)
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if (feat.UMIP)
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{
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if (!BSP)
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KPrint("UMIP is supported.");
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debug("UMIP is supported.");
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// cr4.UMIP = 1;
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fixme("UMIP is supported.");
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// cr4.UMIP = true;
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}
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if (SMEPSupport)
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if (feat.SMEP)
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{
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if (!BSP)
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KPrint("SMEP is supported.");
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debug("SMEP is supported.");
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// cr4.SMEP = 1;
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fixme("SMEP is supported.");
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// cr4.SMEP = true;
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}
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if (SMAPSupport)
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if (feat.SMAP)
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{
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if (!BSP)
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KPrint("SMAP is supported.");
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debug("SMAP is supported.");
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// cr4.SMAP = 1;
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fixme("SMAP is supported.");
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// cr4.SMAP = true;
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}
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}
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else
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@@ -321,117 +341,24 @@ namespace CPU
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}
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}
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if (feat.FSGSBASE)
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{
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if (!BSP)
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KPrint("FSGSBASE is supported.");
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fixme("FSGSBASE is supported.");
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cr4.FSGSBASE = true;
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}
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debug("Writing CR4...");
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x64::writecr4(cr4);
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writecr4(cr4);
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debug("Wrote CR4.");
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debug("Enabling PAT support...");
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x64::wrmsr(x64::MSR_CR_PAT, 0x6 | (0x0 << 8) | (0x1 << 16));
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wrmsr(MSR_CR_PAT, 0x6 | (0x0 << 8) | (0x1 << 16));
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if (!BSP++)
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trace("Features for BSP initialized.");
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if (SSEEnableAfter)
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SSEEnabled = true;
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#elif defined(a32)
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x32::CR0 cr0 = x32::readcr0();
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x32::CR4 cr4 = x32::readcr4();
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if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
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{
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CPU::x86::AMD::CPUID0x00000001 cpuid1;
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cpuid1.Get();
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PGESupport = cpuid1.EDX.PGE;
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SSESupport = cpuid1.EDX.SSE;
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}
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else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
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{
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CPU::x86::Intel::CPUID0x00000001 cpuid1;
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cpuid1.Get();
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PGESupport = cpuid1.EDX.PGE;
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SSESupport = cpuid1.EDX.SSE;
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}
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if (Config.SIMD == false)
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{
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debug("Disabling SSE support...");
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SSESupport = false;
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}
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if (PGESupport)
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{
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debug("Enabling global pages support...");
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if (!BSP)
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KPrint("Global Pages is supported.");
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cr4.PGE = 1;
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}
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bool SSEEnableAfter = false;
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/* Not sure if my code is not working properly or something else is the issue. */
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if ((strcmp(Hypervisor(), x86_CPUID_VENDOR_TCG) != 0 &&
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strcmp(Hypervisor(), x86_CPUID_VENDOR_VIRTUALBOX) != 0) &&
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SSESupport)
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{
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debug("Enabling FPU...");
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bool FPU = false;
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{
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x32::CR0 _cr0;
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// __asm__ __volatile__(
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// "mov %%cr0, %0\n"
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// "and $0xfffffff8, %0\n"
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// "mov %0, %%cr0\n"
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// "fninit\n"
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// "fwait\n"
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// "mov %%cr0, %0\n"
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// : "=r"(_cr0.raw)
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// :
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// : "memory");
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_cr0 = x32::readcr0();
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if ((_cr0.EM) == 0)
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{
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FPU = true;
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debug("FPU is supported");
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}
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}
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if (FPU)
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KPrint("FPU is supported.");
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debug("Enabling SSE support...");
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if (!BSP)
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KPrint("SSE is supported.");
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cr0.EM = 0;
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cr0.MP = 1;
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cr4.OSFXSR = 1;
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cr4.OSXMMEXCPT = 1;
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CPUData *CoreData = GetCPU(Core);
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CoreData->Data.FPU.mxcsr = 0b0001111110000000;
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CoreData->Data.FPU.mxcsrmask = 0b1111111110111111;
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CoreData->Data.FPU.fcw = 0b0000001100111111;
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CPU::x64::fxrstor(&CoreData->Data.FPU);
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SSEEnableAfter = true;
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}
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cr0.NW = 0;
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cr0.CD = 0;
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cr0.WP = 1;
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x32::writecr0(cr0);
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debug("Writing CR4...");
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x32::writecr4(cr4);
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debug("Wrote CR4.");
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debug("Enabling PAT support...");
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x32::wrmsr(x32::MSR_CR_PAT, 0x6 | (0x0 << 8) | (0x1 << 16));
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if (!BSP++)
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trace("Features for BSP initialized.");
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if (SSEEnableAfter)
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SSEEnabled = true;
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#elif defined(aa64)
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#endif
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}
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uint64_t Counter()
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@@ -99,7 +99,7 @@ NIF void MapFromZero(PageTable *PT)
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va.Unmap((void *)0);
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}
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NIF void MapFramebuffer(PageTable *PT)
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NIF void MapFramebuffer(PageTable *PT, bool PSE, bool OneGB)
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{
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debug("Mapping Framebuffer");
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Virtual va = Virtual(PT);
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@@ -109,10 +109,20 @@ NIF void MapFramebuffer(PageTable *PT)
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if (!bInfo.Framebuffer[itrfb].BaseAddress)
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break;
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va.OptimizedMap((void *)bInfo.Framebuffer[itrfb].BaseAddress,
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(void *)bInfo.Framebuffer[itrfb].BaseAddress,
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(size_t)(bInfo.Framebuffer[itrfb].Pitch * bInfo.Framebuffer[itrfb].Height),
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PTFlag::RW | PTFlag::US | PTFlag::G);
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size_t fbSize = bInfo.Framebuffer[itrfb].Pitch * bInfo.Framebuffer[itrfb].Height;
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if (PSE && OneGB)
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{
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va.OptimizedMap(bInfo.Framebuffer[itrfb].BaseAddress,
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bInfo.Framebuffer[itrfb].BaseAddress,
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fbSize, PTFlag::RW | PTFlag::US | PTFlag::G);
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}
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else
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{
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va.Map(bInfo.Framebuffer[itrfb].BaseAddress,
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bInfo.Framebuffer[itrfb].BaseAddress,
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fbSize, PTFlag::RW | PTFlag::US | PTFlag::G);
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}
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itrfb++;
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}
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}
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@@ -337,7 +347,7 @@ NIF void InitializeMemoryManagement()
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#endif
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MapFromZero(KernelPageTable);
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MapFramebuffer(KernelPageTable);
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MapFramebuffer(KernelPageTable, PSESupport, Page1GBSupport);
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MapKernel(KernelPageTable);
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trace("Applying new page table from address %#lx", KernelPageTable);
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