mirror of
https://github.com/EnderIce2/Fennix.git
synced 2025-07-13 16:29:17 +00:00
Kernel/multiboot2_64
This commit is contained in:
EnderIce2
@ -1,10 +0,0 @@
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#include <types.h>
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#include <debug.h>
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#include <cpu.hpp>
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EXTERNC void arm64Entry(uint64_t dtb_ptr32, uint64_t x1, uint64_t x2, uint64_t x3)
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{
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trace("Hello, World!");
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CPU::Halt(true);
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}
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@ -1,14 +0,0 @@
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#include <syscalls.hpp>
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#include <cpu.hpp>
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extern "C" __attribute__((naked, used, no_stack_protector)) void SystemCallHandlerStub()
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{
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}
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extern "C" uint64_t SystemCallsHandler(SyscallsFrame *regs);
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void InitializeSystemCalls()
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{
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}
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@ -1,40 +0,0 @@
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#include <smp.hpp>
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#include <interrupts.hpp>
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#include <memory.hpp>
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#include <cpu.hpp>
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#include "../../../kernel.h"
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volatile bool CPUEnabled = false;
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#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
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static __attribute__((aligned(PAGE_SIZE))) CPUData CPUs[MAX_CPU] = {0};
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CPUData *GetCPU(uint64_t id) { return &CPUs[id]; }
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CPUData *GetCurrentCPU()
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{
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uint64_t ret = 0;
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if (!CPUs[ret].IsActive)
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{
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error("CPU %d is not active!", ret);
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return &CPUs[0];
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}
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if (CPUs[ret].Checksum != CPU_DATA_CHECKSUM)
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{
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error("CPU %d data is corrupted!", ret);
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return &CPUs[0];
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}
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return &CPUs[ret];
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}
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namespace SMP
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{
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void Initialize(void *madt)
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{
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fixme("SMP::Initialize() is not implemented!");
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}
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}
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@ -1,42 +0,0 @@
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ENTRY(_start)
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SECTIONS
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{
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. = 0x80000;
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_kernel_start = .;
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.text :
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{
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KEEP(*(.text.boot))
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*(.text .text.*)
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}
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. = ALIGN(4096);
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_kernel_text_end = .;
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.data :
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{
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*(.data .data.*)
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}
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. = ALIGN(4096);
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_kernel_data_end = .;
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.rodata :
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{
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*(.rodata .rodata.*)
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}
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. = ALIGN(4096);
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_kernel_rodata_end = .;
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.bss :
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{
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*(.bss .bss.*)
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}
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. = ALIGN(4096);
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_kernel_end = .;
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_bss_size = _kernel_end - _kernel_rodata_end;
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/DISCARD/ :
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{
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*(.comment*)
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*(.note*)
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}
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}
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@ -1,17 +0,0 @@
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// .section ".text.boot"
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//
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// .global _start
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// .org 0x80000
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// _start:
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// ldr x5, =_start
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// mov sp, x5
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// ldr x5, =_kernel_rodata_end
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// ldr w6, =_bss_size
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// 1: cbz w6, 2f
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// str xzr, [x5], #8
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// sub w6, w6, #1
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// cbnz w6, 1b
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// 2: bl arm64Entry
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// Halt:
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// wfe
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// b Halt
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@ -1,17 +0,0 @@
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.section ".text.boot"
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.global _start
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.org 0x80000
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_start:
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ldr x5, =_start
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mov sp, x5
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ldr x5, =_kernel_rodata_end
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ldr w6, =_bss_size
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1: cbz w6, 2f
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str xzr, [x5], #8
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sub w6, w6, #1
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cbnz w6, 1b
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2: bl arm64Entry
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Halt:
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wfe
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b Halt
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@ -1 +0,0 @@
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// C++ constructor/destructor stuff
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@ -1 +0,0 @@
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// C++ constructor/destructor stuff
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@ -1,13 +0,0 @@
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.section .init
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.global _init
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.type _init, @function
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_init:
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// push %rbp
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// movq %rsp, %rbp
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.section .fini
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.global _fini
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.type _fini, @function
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_fini:
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// push %rbp
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// movq %rsp, %rbp
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@ -1,7 +0,0 @@
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.section .init
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// popq %rbp
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ret
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.section .fini
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// popq %rbp
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ret
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@ -1,130 +0,0 @@
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#include "acpi.hpp"
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#include <debug.h>
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#include <io.h>
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#pragma GCC diagnostic ignored "-Wint-to-pointer-cast"
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namespace ACPI
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{
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void *ACPI::FindTable(ACPI::ACPIHeader *ACPIHeader, char *Signature)
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{
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for (uint64_t t = 0; t < ((ACPIHeader->Length - sizeof(ACPI::ACPIHeader)) / (XSDTSupported ? 8 : 4)); t++)
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{
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// Should I be concerned about unaligned memory access?
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ACPI::ACPIHeader *SDTHdr = nullptr;
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if (XSDTSupported)
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SDTHdr = (ACPI::ACPIHeader *)(*(uint64_t *)((uint64_t)ACPIHeader + sizeof(ACPI::ACPIHeader) + (t * 8)));
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else
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SDTHdr = (ACPI::ACPIHeader *)(*(uint32_t *)((uint64_t)ACPIHeader + sizeof(ACPI::ACPIHeader) + (t * 4)));
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for (uint64_t i = 0; i < 4; i++)
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{
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if (SDTHdr->Signature[i] != Signature[i])
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break;
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if (i == 3)
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{
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trace("%s found!", Signature);
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return SDTHdr;
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}
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}
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}
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// warn("%s not found!", Signature);
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return nullptr;
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}
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void ACPI::SearchTables(ACPIHeader *Header)
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{
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if (!Header)
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return;
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HPET = (HPETHeader *)FindTable(XSDT, (char *)"HPET");
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FADT = (FADTHeader *)FindTable(XSDT, (char *)"FACP");
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MCFG = (MCFGHeader *)FindTable(XSDT, (char *)"MCFG");
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BGRT = (BGRTHeader *)FindTable(XSDT, (char *)"BGRT");
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SRAT = (SRATHeader *)FindTable(XSDT, (char *)"SRAT");
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TPM2 = (TPM2Header *)FindTable(XSDT, (char *)"TPM2");
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TCPA = (TCPAHeader *)FindTable(XSDT, (char *)"TCPA");
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WAET = (WAETHeader *)FindTable(XSDT, (char *)"WAET");
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MADT = (MADTHeader *)FindTable(XSDT, (char *)"APIC");
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HEST = (HESTHeader *)FindTable(XSDT, (char *)"HEST");
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FindTable(XSDT, (char *)"BERT");
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FindTable(XSDT, (char *)"CPEP");
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FindTable(XSDT, (char *)"DSDT");
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FindTable(XSDT, (char *)"ECDT");
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FindTable(XSDT, (char *)"EINJ");
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FindTable(XSDT, (char *)"ERST");
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FindTable(XSDT, (char *)"FACS");
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FindTable(XSDT, (char *)"MSCT");
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FindTable(XSDT, (char *)"MPST");
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FindTable(XSDT, (char *)"OEMx");
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FindTable(XSDT, (char *)"PMTT");
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FindTable(XSDT, (char *)"PSDT");
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FindTable(XSDT, (char *)"RASF");
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FindTable(XSDT, (char *)"RSDT");
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FindTable(XSDT, (char *)"SBST");
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FindTable(XSDT, (char *)"SLIT");
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FindTable(XSDT, (char *)"SSDT");
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FindTable(XSDT, (char *)"XSDT");
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FindTable(XSDT, (char *)"DRTM");
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FindTable(XSDT, (char *)"FPDT");
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FindTable(XSDT, (char *)"GTDT");
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FindTable(XSDT, (char *)"PCCT");
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FindTable(XSDT, (char *)"S3PT");
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FindTable(XSDT, (char *)"MATR");
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FindTable(XSDT, (char *)"MSDM");
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FindTable(XSDT, (char *)"WPBT");
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FindTable(XSDT, (char *)"OSDT");
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FindTable(XSDT, (char *)"RSDP");
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FindTable(XSDT, (char *)"NFIT");
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FindTable(XSDT, (char *)"ASF!");
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FindTable(XSDT, (char *)"BOOT");
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FindTable(XSDT, (char *)"CSRT");
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FindTable(XSDT, (char *)"DBG2");
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FindTable(XSDT, (char *)"DBGP");
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FindTable(XSDT, (char *)"DMAR");
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FindTable(XSDT, (char *)"IBFT");
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FindTable(XSDT, (char *)"IORT");
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FindTable(XSDT, (char *)"IVRS");
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FindTable(XSDT, (char *)"LPIT");
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FindTable(XSDT, (char *)"MCHI");
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FindTable(XSDT, (char *)"MTMR");
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FindTable(XSDT, (char *)"SLIC");
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FindTable(XSDT, (char *)"SPCR");
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FindTable(XSDT, (char *)"SPMI");
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FindTable(XSDT, (char *)"UEFI");
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FindTable(XSDT, (char *)"VRTC");
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FindTable(XSDT, (char *)"WDAT");
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FindTable(XSDT, (char *)"WDDT");
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FindTable(XSDT, (char *)"WDRT");
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}
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ACPI::ACPI(BootInfo *Info)
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{
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trace("Initializing ACPI");
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if (Info->RSDP->Revision >= 2 && Info->RSDP->XSDTAddress)
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{
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debug("XSDT supported");
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XSDTSupported = true;
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XSDT = (ACPIHeader *)(Info->RSDP->XSDTAddress);
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}
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else
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{
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debug("RSDT supported");
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XSDT = (ACPIHeader *)(uintptr_t)Info->RSDP->RSDTAddress;
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}
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this->SearchTables(XSDT);
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if (FADT)
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{
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outb(FADT->SMI_CommandPort, FADT->AcpiEnable);
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while (!(inw(FADT->PM1aControlBlock) & 1))
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;
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}
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}
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ACPI::~ACPI()
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{
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}
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}
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@ -1,213 +0,0 @@
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#include "acpi.hpp"
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#include <time.hpp>
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#include <debug.h>
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#include <smp.hpp>
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#include <io.h>
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|
||||
#include "cpu/apic.hpp"
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|
||||
#define ACPI_TIMER 0x0001
|
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#define ACPI_BUSMASTER 0x0010
|
||||
#define ACPI_GLOBAL 0x0020
|
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#define ACPI_POWER_BUTTON 0x0100
|
||||
#define ACPI_SLEEP_BUTTON 0x0200
|
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#define ACPI_RTC_ALARM 0x0400
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#define ACPI_PCIE_WAKE 0x4000
|
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#define ACPI_WAKE 0x8000
|
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|
||||
namespace ACPI
|
||||
{
|
||||
__attribute__((always_inline)) inline bool IsCanonical(uint64_t Address)
|
||||
{
|
||||
return ((Address <= 0x00007FFFFFFFFFFF) || ((Address >= 0xFFFF800000000000) && (Address <= 0xFFFFFFFFFFFFFFFF)));
|
||||
}
|
||||
|
||||
#define ACPI_ENABLED 0x0001
|
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#define ACPI_SLEEP 0x2000
|
||||
|
||||
#define ACPI_GAS_MMIO 0
|
||||
#define ACPI_GAS_IO 1
|
||||
#define ACPI_GAS_PCI 2
|
||||
|
||||
void DSDT::OnInterruptReceived(CPU::x64::TrapFrame *Frame)
|
||||
{
|
||||
debug("SCI Handle Triggered");
|
||||
uint16_t Event = 0;
|
||||
{
|
||||
uint16_t a = 0, b = 0;
|
||||
if (acpi->FADT->PM1aEventBlock)
|
||||
{
|
||||
a = inw(acpi->FADT->PM1aEventBlock);
|
||||
outw(acpi->FADT->PM1aEventBlock, a);
|
||||
}
|
||||
if (acpi->FADT->PM1bEventBlock)
|
||||
{
|
||||
b = inw(acpi->FADT->PM1bEventBlock);
|
||||
outw(acpi->FADT->PM1bEventBlock, b);
|
||||
}
|
||||
Event = a | b;
|
||||
}
|
||||
|
||||
debug("SCI Event: %#lx", Event);
|
||||
if (Event & ACPI_BUSMASTER)
|
||||
{
|
||||
fixme("ACPI Busmaster");
|
||||
}
|
||||
else if (Event & ACPI_GLOBAL)
|
||||
{
|
||||
fixme("ACPI Global");
|
||||
}
|
||||
else if (Event & ACPI_POWER_BUTTON)
|
||||
{
|
||||
this->Shutdown();
|
||||
Time::Clock tm = Time::ReadClock();
|
||||
while (tm.Second == Time::ReadClock().Second)
|
||||
;
|
||||
outw(0xB004, 0x2000);
|
||||
outw(0x604, 0x2000);
|
||||
outw(0x4004, 0x3400);
|
||||
CPU::Stop();
|
||||
}
|
||||
else if (Event & ACPI_SLEEP_BUTTON)
|
||||
{
|
||||
fixme("ACPI Sleep Button");
|
||||
}
|
||||
else if (Event & ACPI_RTC_ALARM)
|
||||
{
|
||||
fixme("ACPI RTC Alarm");
|
||||
}
|
||||
else if (Event & ACPI_PCIE_WAKE)
|
||||
{
|
||||
fixme("ACPI PCIe Wake");
|
||||
}
|
||||
else if (Event & ACPI_WAKE)
|
||||
{
|
||||
fixme("ACPI Wake");
|
||||
}
|
||||
else if (Event & ACPI_TIMER)
|
||||
{
|
||||
fixme("ACPI Timer");
|
||||
}
|
||||
else
|
||||
{
|
||||
error("ACPI unknown event %#lx on CPU %d", Event, GetCurrentCPU()->ID);
|
||||
CPU::Stop();
|
||||
}
|
||||
UNUSED(Frame);
|
||||
}
|
||||
|
||||
void DSDT::Shutdown()
|
||||
{
|
||||
trace("Shutting down...");
|
||||
if (SCI_EN == 1)
|
||||
{
|
||||
outw(acpi->FADT->PM1aControlBlock, (inw(acpi->FADT->PM1aControlBlock) & 0xE3FF) | ((SLP_TYPa << 10) | ACPI_SLEEP));
|
||||
if (acpi->FADT->PM1bControlBlock)
|
||||
outw(acpi->FADT->PM1bControlBlock, (inw(acpi->FADT->PM1bControlBlock) & 0xE3FF) | ((SLP_TYPb << 10) | ACPI_SLEEP));
|
||||
outw(PM1a_CNT, SLP_TYPa | SLP_EN);
|
||||
if (PM1b_CNT)
|
||||
outw(PM1b_CNT, SLP_TYPb | SLP_EN);
|
||||
}
|
||||
}
|
||||
|
||||
void DSDT::Reboot()
|
||||
{
|
||||
trace("Rebooting...");
|
||||
switch (acpi->FADT->ResetReg.AddressSpace)
|
||||
{
|
||||
case ACPI_GAS_MMIO:
|
||||
*(uint8_t *)(acpi->FADT->ResetReg.Address) = acpi->FADT->ResetValue;
|
||||
break;
|
||||
case ACPI_GAS_IO:
|
||||
outb(acpi->FADT->ResetReg.Address, acpi->FADT->ResetValue);
|
||||
break;
|
||||
case ACPI_GAS_PCI:
|
||||
fixme("ACPI_GAS_PCI not supported.");
|
||||
/*
|
||||
seg - 0
|
||||
bus - 0
|
||||
dev - (FADT->ResetReg.Address >> 32) & 0xFFFF
|
||||
function - (FADT->ResetReg.Address >> 16) & 0xFFFF
|
||||
offset - FADT->ResetReg.Address & 0xFFFF
|
||||
value - FADT->ResetValue
|
||||
*/
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
DSDT::DSDT(ACPI *acpi) : Interrupts::Handler(acpi->FADT->SCI_Interrupt + CPU::x64::IRQ0)
|
||||
{
|
||||
this->acpi = acpi;
|
||||
uint64_t Address = ((IsCanonical(acpi->FADT->X_Dsdt) && acpi->XSDTSupported) ? acpi->FADT->X_Dsdt : acpi->FADT->Dsdt);
|
||||
uint8_t *S5Address = (uint8_t *)(Address) + 36;
|
||||
ACPI::ACPI::ACPIHeader *Header = (ACPI::ACPI::ACPIHeader *)Address;
|
||||
uint64_t Length = Header->Length;
|
||||
while (Length-- > 0)
|
||||
{
|
||||
if (!memcmp(S5Address, "_S5_", 4))
|
||||
break;
|
||||
S5Address++;
|
||||
}
|
||||
if (Length <= 0)
|
||||
{
|
||||
warn("_S5 not present in ACPI");
|
||||
return;
|
||||
}
|
||||
if ((*(S5Address - 1) == 0x08 || (*(S5Address - 2) == 0x08 && *(S5Address - 1) == '\\')) && *(S5Address + 4) == 0x12)
|
||||
{
|
||||
S5Address += 5;
|
||||
S5Address += ((*S5Address & 0xC0) >> 6) + 2;
|
||||
if (*S5Address == 0x0A)
|
||||
S5Address++;
|
||||
SLP_TYPa = *(S5Address) << 10;
|
||||
S5Address++;
|
||||
if (*S5Address == 0x0A)
|
||||
S5Address++;
|
||||
SLP_TYPb = *(S5Address) << 10;
|
||||
SMI_CMD = acpi->FADT->SMI_CommandPort;
|
||||
ACPI_ENABLE = acpi->FADT->AcpiEnable;
|
||||
ACPI_DISABLE = acpi->FADT->AcpiDisable;
|
||||
PM1a_CNT = acpi->FADT->PM1aControlBlock;
|
||||
PM1b_CNT = acpi->FADT->PM1bControlBlock;
|
||||
PM1_CNT_LEN = acpi->FADT->PM1ControlLength;
|
||||
SLP_EN = 1 << 13;
|
||||
SCI_EN = 1;
|
||||
trace("ACPI Shutdown is supported");
|
||||
ACPIShutdownSupported = true;
|
||||
|
||||
uint16_t value = ACPI_POWER_BUTTON | ACPI_SLEEP_BUTTON | ACPI_WAKE;
|
||||
{
|
||||
uint16_t a = acpi->FADT->PM1aEventBlock + (acpi->FADT->PM1EventLength / 2);
|
||||
uint16_t b = acpi->FADT->PM1bEventBlock + (acpi->FADT->PM1EventLength / 2);
|
||||
debug("SCI Event: %#llx [a:%#x b:%#x]", value, a, b);
|
||||
if (acpi->FADT->PM1aEventBlock)
|
||||
outw(a, value);
|
||||
if (acpi->FADT->PM1bEventBlock)
|
||||
outw(b, value);
|
||||
}
|
||||
|
||||
{
|
||||
uint16_t a = 0, b = 0;
|
||||
if (acpi->FADT->PM1aEventBlock)
|
||||
{
|
||||
a = inw(acpi->FADT->PM1aEventBlock);
|
||||
outw(acpi->FADT->PM1aEventBlock, a);
|
||||
}
|
||||
if (acpi->FADT->PM1bEventBlock)
|
||||
{
|
||||
b = inw(acpi->FADT->PM1bEventBlock);
|
||||
outw(acpi->FADT->PM1bEventBlock, b);
|
||||
}
|
||||
}
|
||||
((APIC::APIC *)Interrupts::apic[0])->RedirectIRQ(0, acpi->FADT->SCI_Interrupt, 1);
|
||||
return;
|
||||
}
|
||||
warn("Failed to parse _S5 in ACPI");
|
||||
SCI_EN = 0;
|
||||
}
|
||||
|
||||
DSDT::~DSDT()
|
||||
{
|
||||
}
|
||||
}
|
||||
@ -1,257 +0,0 @@
|
||||
#include <boot/binfo.h>
|
||||
#include <types.h>
|
||||
#include <debug.h>
|
||||
#include <convert.h>
|
||||
|
||||
#include "../../../tools/limine/limine.h"
|
||||
#include "../../kernel.h"
|
||||
|
||||
void init_limine();
|
||||
|
||||
static volatile struct limine_entry_point_request EntryPointRequest = {
|
||||
.id = LIMINE_ENTRY_POINT_REQUEST,
|
||||
.revision = 0,
|
||||
.response = NULL,
|
||||
.entry = init_limine};
|
||||
static volatile struct limine_bootloader_info_request BootloaderInfoRequest = {
|
||||
.id = LIMINE_BOOTLOADER_INFO_REQUEST,
|
||||
.revision = 0};
|
||||
static volatile struct limine_terminal_request TerminalRequest = {
|
||||
.id = LIMINE_TERMINAL_REQUEST,
|
||||
.revision = 0};
|
||||
static volatile struct limine_framebuffer_request FramebufferRequest = {
|
||||
.id = LIMINE_FRAMEBUFFER_REQUEST,
|
||||
.revision = 0};
|
||||
static volatile struct limine_memmap_request MemmapRequest = {
|
||||
.id = LIMINE_MEMMAP_REQUEST,
|
||||
.revision = 0};
|
||||
static volatile struct limine_kernel_address_request KernelAddressRequest = {
|
||||
.id = LIMINE_KERNEL_ADDRESS_REQUEST,
|
||||
.revision = 0};
|
||||
static volatile struct limine_rsdp_request RsdpRequest = {
|
||||
.id = LIMINE_RSDP_REQUEST,
|
||||
.revision = 0};
|
||||
static volatile struct limine_kernel_file_request KernelFileRequest = {
|
||||
.id = LIMINE_KERNEL_FILE_REQUEST,
|
||||
.revision = 0};
|
||||
static volatile struct limine_module_request ModuleRequest = {
|
||||
.id = LIMINE_MODULE_REQUEST,
|
||||
.revision = 0};
|
||||
|
||||
static volatile struct limine_smbios_request SmbiosRequest = {
|
||||
.id = LIMINE_SMBIOS_REQUEST,
|
||||
.revision = 0};
|
||||
|
||||
SafeFunction __no_instrument_function void init_limine()
|
||||
{
|
||||
struct BootInfo binfo;
|
||||
struct limine_bootloader_info_response *BootloaderInfoResponse = BootloaderInfoRequest.response;
|
||||
info("Bootloader: %s %s", BootloaderInfoResponse->name, BootloaderInfoResponse->version);
|
||||
|
||||
struct limine_terminal_response *TerminalResponse = TerminalRequest.response;
|
||||
|
||||
if (TerminalResponse == NULL || TerminalResponse->terminal_count < 1)
|
||||
{
|
||||
warn("No terminal available.");
|
||||
while (1)
|
||||
asmv("hlt");
|
||||
}
|
||||
TerminalResponse->write(TerminalResponse->terminals[0], "\033[37mPlease wait... ", 20);
|
||||
|
||||
struct limine_framebuffer_response *FrameBufferResponse = FramebufferRequest.response;
|
||||
struct limine_memmap_response *MemmapResponse = MemmapRequest.response;
|
||||
struct limine_kernel_address_response *KernelAddressResponse = KernelAddressRequest.response;
|
||||
struct limine_rsdp_response *RsdpResponse = RsdpRequest.response;
|
||||
struct limine_kernel_file_response *KernelFileResponse = KernelFileRequest.response;
|
||||
struct limine_module_response *ModuleResponse = ModuleRequest.response;
|
||||
struct limine_smbios_response *SmbiosResponse = SmbiosRequest.response;
|
||||
|
||||
if (FrameBufferResponse == NULL || FrameBufferResponse->framebuffer_count < 1)
|
||||
{
|
||||
error("No framebuffer available [%p;%ld]", FrameBufferResponse,
|
||||
(FrameBufferResponse == NULL) ? 0 : FrameBufferResponse->framebuffer_count);
|
||||
TerminalResponse->write(TerminalResponse->terminals[0], "No framebuffer available", 24);
|
||||
while (1)
|
||||
asmv("hlt");
|
||||
}
|
||||
|
||||
if (MemmapResponse == NULL || MemmapResponse->entry_count < 1)
|
||||
{
|
||||
error("No memory map available [%p;%ld]", MemmapResponse,
|
||||
(MemmapResponse == NULL) ? 0 : MemmapResponse->entry_count);
|
||||
TerminalResponse->write(TerminalResponse->terminals[0], "No memory map available", 23);
|
||||
while (1)
|
||||
asmv("hlt");
|
||||
}
|
||||
|
||||
if (KernelAddressResponse == NULL)
|
||||
{
|
||||
error("No kernel address available [%p]", KernelAddressResponse);
|
||||
TerminalResponse->write(TerminalResponse->terminals[0], "No kernel address available", 27);
|
||||
while (1)
|
||||
asmv("hlt");
|
||||
}
|
||||
|
||||
if (RsdpResponse == NULL || RsdpResponse->address == 0)
|
||||
{
|
||||
error("No RSDP address available [%p;%p]", RsdpResponse,
|
||||
(RsdpResponse == NULL) ? 0 : RsdpResponse->address);
|
||||
TerminalResponse->write(TerminalResponse->terminals[0], "No RSDP address available", 25);
|
||||
while (1)
|
||||
asmv("hlt");
|
||||
}
|
||||
|
||||
if (KernelFileResponse == NULL || KernelFileResponse->kernel_file == NULL)
|
||||
{
|
||||
error("No kernel file available [%p;%p]", KernelFileResponse,
|
||||
(KernelFileResponse == NULL) ? 0 : KernelFileResponse->kernel_file);
|
||||
TerminalResponse->write(TerminalResponse->terminals[0], "No kernel file available", 24);
|
||||
while (1)
|
||||
asmv("hlt");
|
||||
}
|
||||
|
||||
if (ModuleResponse == NULL || ModuleResponse->module_count < 1)
|
||||
{
|
||||
error("No module information available [%p;%ld]", ModuleResponse,
|
||||
(ModuleResponse == NULL) ? 0 : ModuleResponse->module_count);
|
||||
TerminalResponse->write(TerminalResponse->terminals[0], "No module information available", 31);
|
||||
while (1)
|
||||
asmv("hlt");
|
||||
}
|
||||
|
||||
for (uint64_t i = 0; i < FrameBufferResponse->framebuffer_count; i++)
|
||||
{
|
||||
struct limine_framebuffer *framebuffer = FrameBufferResponse->framebuffers[i];
|
||||
binfo.Framebuffer[i].BaseAddress = (void *)((uint64_t)framebuffer->address - 0xffff800000000000);
|
||||
binfo.Framebuffer[i].Width = framebuffer->width;
|
||||
binfo.Framebuffer[i].Height = framebuffer->height;
|
||||
binfo.Framebuffer[i].Pitch = framebuffer->pitch;
|
||||
binfo.Framebuffer[i].BitsPerPixel = framebuffer->bpp;
|
||||
binfo.Framebuffer[i].MemoryModel = framebuffer->memory_model;
|
||||
binfo.Framebuffer[i].RedMaskSize = framebuffer->red_mask_size;
|
||||
binfo.Framebuffer[i].RedMaskShift = framebuffer->red_mask_shift;
|
||||
binfo.Framebuffer[i].GreenMaskSize = framebuffer->green_mask_size;
|
||||
binfo.Framebuffer[i].GreenMaskShift = framebuffer->green_mask_shift;
|
||||
binfo.Framebuffer[i].BlueMaskSize = framebuffer->blue_mask_size;
|
||||
binfo.Framebuffer[i].BlueMaskShift = framebuffer->blue_mask_shift;
|
||||
binfo.Framebuffer[i].ExtendedDisplayIdentificationData = framebuffer->edid;
|
||||
binfo.Framebuffer[i].EDIDSize = framebuffer->edid_size;
|
||||
debug("Framebuffer %d: %dx%d %d bpp", i, framebuffer->width, framebuffer->height, framebuffer->bpp);
|
||||
debug("More info:\nAddress: %p\nPitch: %ld\nMemoryModel: %d\nRedMaskSize: %d\nRedMaskShift: %d\nGreenMaskSize: %d\nGreenMaskShift: %d\nBlueMaskSize: %d\nBlueMaskShift: %d\nEDID: %p\nEDIDSize: %d",
|
||||
(uint64_t)framebuffer->address - 0xffff800000000000, framebuffer->pitch, framebuffer->memory_model, framebuffer->red_mask_size, framebuffer->red_mask_shift, framebuffer->green_mask_size, framebuffer->green_mask_shift, framebuffer->blue_mask_size, framebuffer->blue_mask_shift, framebuffer->edid, framebuffer->edid_size);
|
||||
}
|
||||
|
||||
binfo.Memory.Entries = MemmapResponse->entry_count;
|
||||
for (uint64_t i = 0; i < MemmapResponse->entry_count; i++)
|
||||
{
|
||||
if (MemmapResponse->entry_count > MAX_MEMORY_ENTRIES)
|
||||
{
|
||||
warn("Too many memory entries, skipping the rest...");
|
||||
break;
|
||||
}
|
||||
|
||||
struct limine_memmap_entry *entry = MemmapResponse->entries[i];
|
||||
binfo.Memory.Size += entry->length;
|
||||
switch (entry->type)
|
||||
{
|
||||
case LIMINE_MEMMAP_USABLE:
|
||||
binfo.Memory.Entry[i].BaseAddress = (void *)entry->base;
|
||||
binfo.Memory.Entry[i].Length = entry->length;
|
||||
binfo.Memory.Entry[i].Type = Usable;
|
||||
break;
|
||||
case LIMINE_MEMMAP_RESERVED:
|
||||
binfo.Memory.Entry[i].BaseAddress = (void *)entry->base;
|
||||
binfo.Memory.Entry[i].Length = entry->length;
|
||||
binfo.Memory.Entry[i].Type = Reserved;
|
||||
break;
|
||||
case LIMINE_MEMMAP_ACPI_RECLAIMABLE:
|
||||
binfo.Memory.Entry[i].BaseAddress = (void *)entry->base;
|
||||
binfo.Memory.Entry[i].Length = entry->length;
|
||||
binfo.Memory.Entry[i].Type = ACPIReclaimable;
|
||||
break;
|
||||
case LIMINE_MEMMAP_ACPI_NVS:
|
||||
binfo.Memory.Entry[i].BaseAddress = (void *)entry->base;
|
||||
binfo.Memory.Entry[i].Length = entry->length;
|
||||
binfo.Memory.Entry[i].Type = ACPINVS;
|
||||
break;
|
||||
case LIMINE_MEMMAP_BAD_MEMORY:
|
||||
binfo.Memory.Entry[i].BaseAddress = (void *)entry->base;
|
||||
binfo.Memory.Entry[i].Length = entry->length;
|
||||
binfo.Memory.Entry[i].Type = BadMemory;
|
||||
break;
|
||||
case LIMINE_MEMMAP_BOOTLOADER_RECLAIMABLE:
|
||||
binfo.Memory.Entry[i].BaseAddress = (void *)entry->base;
|
||||
binfo.Memory.Entry[i].Length = entry->length;
|
||||
binfo.Memory.Entry[i].Type = BootloaderReclaimable;
|
||||
break;
|
||||
case LIMINE_MEMMAP_KERNEL_AND_MODULES:
|
||||
binfo.Memory.Entry[i].BaseAddress = (void *)entry->base;
|
||||
binfo.Memory.Entry[i].Length = entry->length;
|
||||
binfo.Memory.Entry[i].Type = KernelAndModules;
|
||||
break;
|
||||
case LIMINE_MEMMAP_FRAMEBUFFER:
|
||||
binfo.Memory.Entry[i].BaseAddress = (void *)entry->base;
|
||||
binfo.Memory.Entry[i].Length = entry->length;
|
||||
binfo.Memory.Entry[i].Type = Framebuffer;
|
||||
break;
|
||||
default:
|
||||
binfo.Memory.Entry[i].BaseAddress = (void *)entry->base;
|
||||
binfo.Memory.Entry[i].Length = entry->length;
|
||||
binfo.Memory.Entry[i].Type = Unknown;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
for (uint64_t i = 0; i < ModuleResponse->module_count; i++)
|
||||
{
|
||||
if (i > MAX_MODULES)
|
||||
{
|
||||
warn("Too many modules, skipping the rest...");
|
||||
break;
|
||||
}
|
||||
|
||||
binfo.Modules[i].Address = (void *)((uint64_t)ModuleResponse->modules[i]->address - 0xffff800000000000);
|
||||
strncpy(binfo.Modules[i].Path,
|
||||
ModuleResponse->modules[i]->path,
|
||||
strlen(ModuleResponse->modules[i]->path) + 1);
|
||||
strncpy(binfo.Modules[i].CommandLine,
|
||||
ModuleResponse->modules[i]->cmdline,
|
||||
strlen(ModuleResponse->modules[i]->cmdline) + 1);
|
||||
binfo.Modules[i].Size = ModuleResponse->modules[i]->size;
|
||||
debug("Module %d:\nAddress: %p\nPath: %s\nCommand Line: %s\nSize: %ld", i,
|
||||
(uint64_t)ModuleResponse->modules[i]->address - 0xffff800000000000, ModuleResponse->modules[i]->path,
|
||||
ModuleResponse->modules[i]->cmdline, ModuleResponse->modules[i]->size);
|
||||
}
|
||||
|
||||
binfo.RSDP = (struct RSDPInfo *)((uint64_t)RsdpResponse->address - 0xffff800000000000);
|
||||
trace("RSDP: %p(%p) [Signature: %.8s] [OEM: %.6s]",
|
||||
RsdpResponse->address, binfo.RSDP, binfo.RSDP->Signature, binfo.RSDP->OEMID);
|
||||
|
||||
debug("SMBIOS: %p %p", SmbiosResponse->entry_32, SmbiosResponse->entry_64);
|
||||
if (SmbiosResponse->entry_32 != NULL)
|
||||
binfo.SMBIOSPtr = (void *)((uint64_t)SmbiosResponse->entry_32 - 0xffff800000000000);
|
||||
else if (SmbiosResponse->entry_64 != NULL)
|
||||
binfo.SMBIOSPtr = (void *)((uint64_t)SmbiosResponse->entry_64 - 0xffff800000000000);
|
||||
else
|
||||
binfo.SMBIOSPtr = NULL;
|
||||
|
||||
binfo.Kernel.PhysicalBase = (void *)KernelAddressResponse->physical_base;
|
||||
binfo.Kernel.VirtualBase = (void *)KernelAddressResponse->virtual_base;
|
||||
binfo.Kernel.FileBase = KernelFileResponse->kernel_file->address;
|
||||
strncpy(binfo.Kernel.CommandLine,
|
||||
KernelFileResponse->kernel_file->cmdline,
|
||||
strlen(KernelFileResponse->kernel_file->cmdline) + 1);
|
||||
binfo.Kernel.Size = KernelFileResponse->kernel_file->size;
|
||||
trace("Kernel physical address: %p", KernelAddressResponse->physical_base);
|
||||
trace("Kernel virtual address: %p", KernelAddressResponse->virtual_base);
|
||||
|
||||
strncpy(binfo.Bootloader.Name,
|
||||
BootloaderInfoResponse->name,
|
||||
strlen(BootloaderInfoResponse->name) + 1);
|
||||
strncpy(binfo.Bootloader.Version,
|
||||
BootloaderInfoResponse->version,
|
||||
strlen(BootloaderInfoResponse->version) + 1);
|
||||
|
||||
// Call kernel entry point
|
||||
Entry(&binfo);
|
||||
}
|
||||
@ -1,69 +0,0 @@
|
||||
#include "acpi.hpp"
|
||||
|
||||
#include <memory.hpp>
|
||||
#include <debug.h>
|
||||
|
||||
#include "../../kernel.h"
|
||||
|
||||
namespace ACPI
|
||||
{
|
||||
MADT::MADT(ACPI::MADTHeader *madt)
|
||||
{
|
||||
trace("Initializing MADT");
|
||||
CPUCores = 0;
|
||||
LAPICAddress = (LAPIC *)(uintptr_t)madt->LocalControllerAddress;
|
||||
for (uint8_t *ptr = (uint8_t *)(madt->Entries);
|
||||
(uintptr_t)(ptr) < (uintptr_t)(madt) + madt->Header.Length;
|
||||
ptr += *(ptr + 1))
|
||||
{
|
||||
switch (*(ptr))
|
||||
{
|
||||
case 0:
|
||||
{
|
||||
if (ptr[4] & 1)
|
||||
{
|
||||
lapic.push_back((LocalAPIC *)ptr);
|
||||
KPrint("Local APIC \e8888FF%d\eCCCCCC (APIC \e8888FF%d\eCCCCCC) found.", lapic.back()->ACPIProcessorId, lapic.back()->APICId);
|
||||
CPUCores++;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case 1:
|
||||
{
|
||||
ioapic.push_back((MADTIOApic *)ptr);
|
||||
KPrint("I/O APIC \e8888FF%d\eCCCCCC (Address \e8888FF%#lx\eCCCCCC) found.", ioapic.back()->APICID, ioapic.back()->Address);
|
||||
Memory::Virtual().Map((void *)(uintptr_t)ioapic.back()->Address, (void *)(uintptr_t)ioapic.back()->Address, Memory::PTFlag::RW | Memory::PTFlag::PCD); // Make sure that the address is mapped.
|
||||
break;
|
||||
}
|
||||
case 2:
|
||||
{
|
||||
iso.push_back((MADTIso *)ptr);
|
||||
KPrint("ISO (IRQ:\e8888FF%#lx\eCCCCCC, BUS:\e8888FF%#lx\eCCCCCC, GSI:\e8888FF%#lx\eCCCCCC, %s\eCCCCCC/%s\eCCCCCC) found.",
|
||||
iso.back()->IRQSource, iso.back()->BuSSource, iso.back()->GSI,
|
||||
iso.back()->Flags & 0x00000004 ? "\e1770FFActive High" : "\e475EFFActive Low",
|
||||
iso.back()->Flags & 0x00000100 ? "\e00962DEdge Triggered" : "\e008F58Level Triggered");
|
||||
break;
|
||||
}
|
||||
case 4:
|
||||
{
|
||||
nmi.push_back((MADTNmi *)ptr);
|
||||
KPrint("NMI \e8888FF%#lx\eCCCCCC (lint:\e8888FF%#lx\eCCCCCC) found.", nmi.back()->processor, nmi.back()->lint);
|
||||
break;
|
||||
}
|
||||
case 5:
|
||||
{
|
||||
LAPICAddress = (LAPIC *)ptr;
|
||||
KPrint("APIC found at \e8888FF%#lx\eCCCCCC", LAPICAddress);
|
||||
break;
|
||||
}
|
||||
}
|
||||
Memory::Virtual().Map((void *)LAPICAddress, (void *)LAPICAddress, Memory::PTFlag::RW | Memory::PTFlag::PCD); // I should map more than one page?
|
||||
}
|
||||
CPUCores--; // We start at 0 (BSP) and end at 11 (APs), so we have 12 cores.
|
||||
KPrint("Total CPU cores: %d", CPUCores + 1);
|
||||
}
|
||||
|
||||
MADT::~MADT()
|
||||
{
|
||||
}
|
||||
}
|
||||
@ -1,85 +0,0 @@
|
||||
#include <syscalls.hpp>
|
||||
|
||||
#include <cpu.hpp>
|
||||
|
||||
#include "cpu/gdt.hpp"
|
||||
|
||||
// https://supercip971.github.io/02-wingos-syscalls.html
|
||||
using namespace CPU::x64;
|
||||
|
||||
// "Core/SystemCalls.cpp"
|
||||
extern "C" uint64_t SystemCallsHandler(SyscallsFrame *regs);
|
||||
|
||||
extern "C" void SystemCallHandlerStub();
|
||||
|
||||
extern "C" __attribute__((naked, used, no_stack_protector)) void SystemCallHandlerStub_broken()
|
||||
{
|
||||
// asmv(
|
||||
// // "cmp $0x08, 0x8(%rsp)\n"
|
||||
// // "je 1f\n"
|
||||
// "swapgs\n"
|
||||
// // "1:\n"
|
||||
|
||||
// "mov %rsp, 0x8(%gs)\n" // CPUData->TempStack
|
||||
// "mov 0x0(%gs), %rsp\n" // CPUData->SystemCallStack
|
||||
// "push $0x1b\n" // user data segment
|
||||
// "push 0x8(%gs)\n" // saved stack
|
||||
// "push %r11\n" // saved rflags
|
||||
// "push $0x23\n" // user code segment
|
||||
// "push %rcx\n" // Current RIP
|
||||
|
||||
// "push %rax\n"
|
||||
// "push %rbx\n"
|
||||
// "push %rcx\n"
|
||||
// "push %rdx\n"
|
||||
// "push %rsi\n"
|
||||
// "push %rdi\n"
|
||||
// "push %rbp\n"
|
||||
// "push %r8\n"
|
||||
// "push %r9\n"
|
||||
// "push %r10\n"
|
||||
// "push %r11\n"
|
||||
// "push %r12\n"
|
||||
// "push %r13\n"
|
||||
// "push %r14\n"
|
||||
// "push %r15\n"
|
||||
|
||||
// "mov %rsp, %rdi\n"
|
||||
// "mov $0, %rbp\n"
|
||||
// "call SystemCallsHandler\n"
|
||||
|
||||
// "pop %r15\n"
|
||||
// "pop %r14\n"
|
||||
// "pop %r13\n"
|
||||
// "pop %r12\n"
|
||||
// "pop %r11\n"
|
||||
// "pop %r10\n"
|
||||
// "pop %r9\n"
|
||||
// "pop %r8\n"
|
||||
// "pop %rbp\n"
|
||||
// "pop %rdi\n"
|
||||
// "pop %rsi\n"
|
||||
// "pop %rdx\n"
|
||||
// "pop %rcx\n"
|
||||
// "pop %rbx\n"
|
||||
// /* "pop %rax\n" */
|
||||
|
||||
// "mov 0x8(%gs), %rsp\n" // CPUData->TempStack
|
||||
|
||||
// // "cmp $0x08, 0x8(%rsp)\n"
|
||||
// // "je 1f\n"
|
||||
// "swapgs\n"
|
||||
// // "1:\n"
|
||||
|
||||
// "sti\n"
|
||||
|
||||
// "sysretq\n");
|
||||
}
|
||||
|
||||
void InitializeSystemCalls()
|
||||
{
|
||||
wrmsr(MSR_EFER, rdmsr(MSR_EFER) | 1);
|
||||
wrmsr(MSR_STAR, ((uint64_t)(GDT_KERNEL_CODE) << 32) | ((uint64_t)(GDT_KERNEL_DATA | 3) << 48));
|
||||
wrmsr(MSR_LSTAR, (uint64_t)SystemCallHandlerStub);
|
||||
wrmsr(MSR_SYSCALL_MASK, (uint64_t)(1 << 9));
|
||||
}
|
||||
@ -1,59 +0,0 @@
|
||||
[BITS 64]
|
||||
|
||||
%macro PushAllSC 0
|
||||
push rax
|
||||
push rbx
|
||||
push rcx
|
||||
push rdx
|
||||
push rsi
|
||||
push rdi
|
||||
push rbp
|
||||
push r8
|
||||
push r9
|
||||
push r10
|
||||
push r11
|
||||
push r12
|
||||
push r13
|
||||
push r14
|
||||
push r15
|
||||
%endmacro
|
||||
|
||||
%macro PopAllSC 0
|
||||
pop r15
|
||||
pop r14
|
||||
pop r13
|
||||
pop r12
|
||||
pop r11
|
||||
pop r10
|
||||
pop r9
|
||||
pop r8
|
||||
pop rbp
|
||||
pop rdi
|
||||
pop rsi
|
||||
pop rdx
|
||||
pop rcx
|
||||
pop rbx
|
||||
%endmacro
|
||||
|
||||
ALIGN 4096
|
||||
extern SystemCallsHandler
|
||||
global SystemCallHandlerStub
|
||||
SystemCallHandlerStub:
|
||||
swapgs ; Swap gs and kernelgs
|
||||
mov [gs:0x8], rsp ; CPUData->TempStack
|
||||
mov rsp, [gs:0x0] ; CPUData->SystemCallStack
|
||||
push qword 0x1b ; User data segment
|
||||
push qword [gs:0x8] ; Saved stack
|
||||
push r11 ; Saved rflags
|
||||
push qword 0x23 ; User code segment
|
||||
push rcx ; Current instruction pointer
|
||||
cld ; Clear direction flag
|
||||
PushAllSC ; Push all registers
|
||||
mov rdi, rsp ; Pass pointer to registers
|
||||
mov rbp, 0 ; Pass 0 as return address
|
||||
call SystemCallsHandler ; Call system call handler
|
||||
PopAllSC ; Pop all registers except rax
|
||||
mov rsp, [gs:0x8] ; Restore stack
|
||||
swapgs ; Swap back gs and kernelgs
|
||||
sti ; Enable interrupts
|
||||
o64 sysret ; Return to user mode
|
||||
@ -1,277 +0,0 @@
|
||||
#ifndef __FENNIX_KERNEL_ACPI_H__
|
||||
#define __FENNIX_KERNEL_ACPI_H__
|
||||
|
||||
#include <types.h>
|
||||
|
||||
#include <boot/binfo.h>
|
||||
#include <interrupts.hpp>
|
||||
#include <vector.hpp>
|
||||
#include <cpu.hpp>
|
||||
|
||||
namespace ACPI
|
||||
{
|
||||
class ACPI
|
||||
{
|
||||
public:
|
||||
struct ACPIHeader
|
||||
{
|
||||
unsigned char Signature[4];
|
||||
uint32_t Length;
|
||||
uint8_t Revision;
|
||||
uint8_t Checksum;
|
||||
uint8_t OEMID[6];
|
||||
uint8_t OEMTableID[8];
|
||||
uint32_t OEMRevision;
|
||||
uint32_t CreatorID;
|
||||
uint32_t CreatorRevision;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct GenericAddressStructure
|
||||
{
|
||||
uint8_t AddressSpace;
|
||||
uint8_t BitWidth;
|
||||
uint8_t BitOffset;
|
||||
uint8_t AccessSize;
|
||||
uint64_t Address;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct MCFGHeader
|
||||
{
|
||||
struct ACPIHeader Header;
|
||||
uint64_t Reserved;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct HPETHeader
|
||||
{
|
||||
ACPIHeader Header;
|
||||
uint8_t HardwareRevID;
|
||||
uint8_t ComparatorCount : 5;
|
||||
uint8_t CounterSize : 1;
|
||||
uint8_t Reserved : 1;
|
||||
uint8_t LegacyReplacement : 1;
|
||||
uint16_t PCIVendorID;
|
||||
struct GenericAddressStructure Address;
|
||||
uint8_t HPETNumber;
|
||||
uint16_t MinimumTick;
|
||||
uint8_t PageProtection;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct FADTHeader
|
||||
{
|
||||
ACPIHeader Header;
|
||||
uint32_t FirmwareCtrl;
|
||||
uint32_t Dsdt;
|
||||
uint8_t Reserved;
|
||||
uint8_t PreferredPowerManagementProfile;
|
||||
uint16_t SCI_Interrupt;
|
||||
uint32_t SMI_CommandPort;
|
||||
uint8_t AcpiEnable;
|
||||
uint8_t AcpiDisable;
|
||||
uint8_t S4BIOS_REQ;
|
||||
uint8_t PSTATE_Control;
|
||||
uint32_t PM1aEventBlock;
|
||||
uint32_t PM1bEventBlock;
|
||||
uint32_t PM1aControlBlock;
|
||||
uint32_t PM1bControlBlock;
|
||||
uint32_t PM2ControlBlock;
|
||||
uint32_t PMTimerBlock;
|
||||
uint32_t GPE0Block;
|
||||
uint32_t GPE1Block;
|
||||
uint8_t PM1EventLength;
|
||||
uint8_t PM1ControlLength;
|
||||
uint8_t PM2ControlLength;
|
||||
uint8_t PMTimerLength;
|
||||
uint8_t GPE0Length;
|
||||
uint8_t GPE1Length;
|
||||
uint8_t GPE1Base;
|
||||
uint8_t CStateControl;
|
||||
uint16_t WorstC2Latency;
|
||||
uint16_t WorstC3Latency;
|
||||
uint16_t FlushSize;
|
||||
uint16_t FlushStride;
|
||||
uint8_t DutyOffset;
|
||||
uint8_t DutyWidth;
|
||||
uint8_t DayAlarm;
|
||||
uint8_t MonthAlarm;
|
||||
uint8_t Century;
|
||||
uint16_t BootArchitectureFlags;
|
||||
uint8_t Reserved2;
|
||||
uint32_t Flags;
|
||||
struct GenericAddressStructure ResetReg;
|
||||
uint8_t ResetValue;
|
||||
uint8_t Reserved3[3];
|
||||
uint64_t X_FirmwareControl;
|
||||
uint64_t X_Dsdt;
|
||||
struct GenericAddressStructure X_PM1aEventBlock;
|
||||
struct GenericAddressStructure X_PM1bEventBlock;
|
||||
struct GenericAddressStructure X_PM1aControlBlock;
|
||||
struct GenericAddressStructure X_PM1bControlBlock;
|
||||
struct GenericAddressStructure X_PM2ControlBlock;
|
||||
struct GenericAddressStructure X_PMTimerBlock;
|
||||
struct GenericAddressStructure X_GPE0Block;
|
||||
struct GenericAddressStructure X_GPE1Block;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct BGRTHeader
|
||||
{
|
||||
ACPIHeader Header;
|
||||
uint16_t Version;
|
||||
uint8_t Status;
|
||||
uint8_t ImageType;
|
||||
uint64_t ImageAddress;
|
||||
uint32_t ImageOffsetX;
|
||||
uint32_t ImageOffsetY;
|
||||
};
|
||||
|
||||
struct SRATHeader
|
||||
{
|
||||
ACPIHeader Header;
|
||||
uint32_t TableRevision; // Must be value 1
|
||||
uint64_t Reserved; // Reserved, must be zero
|
||||
};
|
||||
|
||||
struct TPM2Header
|
||||
{
|
||||
ACPIHeader Header;
|
||||
uint32_t Flags;
|
||||
uint64_t ControlAddress;
|
||||
uint32_t StartMethod;
|
||||
};
|
||||
|
||||
struct TCPAHeader
|
||||
{
|
||||
ACPIHeader Header;
|
||||
uint16_t Reserved;
|
||||
uint32_t MaxLogLength;
|
||||
uint64_t LogAddress;
|
||||
};
|
||||
|
||||
struct WAETHeader
|
||||
{
|
||||
ACPIHeader Header;
|
||||
uint32_t Flags;
|
||||
};
|
||||
|
||||
struct HESTHeader
|
||||
{
|
||||
ACPIHeader Header;
|
||||
uint32_t ErrorSourceCount;
|
||||
};
|
||||
|
||||
struct MADTHeader
|
||||
{
|
||||
ACPIHeader Header;
|
||||
uint32_t LocalControllerAddress;
|
||||
uint32_t Flags;
|
||||
char Entries[];
|
||||
} __attribute__((packed));
|
||||
|
||||
ACPIHeader *XSDT = nullptr;
|
||||
MCFGHeader *MCFG = nullptr;
|
||||
HPETHeader *HPET = nullptr;
|
||||
FADTHeader *FADT = nullptr;
|
||||
BGRTHeader *BGRT = nullptr;
|
||||
SRATHeader *SRAT = nullptr;
|
||||
TPM2Header *TPM2 = nullptr;
|
||||
TCPAHeader *TCPA = nullptr;
|
||||
WAETHeader *WAET = nullptr;
|
||||
MADTHeader *MADT = nullptr;
|
||||
HESTHeader *HEST = nullptr;
|
||||
bool XSDTSupported = false;
|
||||
|
||||
void *FindTable(ACPIHeader *ACPIHeader, char *Signature);
|
||||
void SearchTables(ACPIHeader *Header);
|
||||
ACPI(BootInfo *Info);
|
||||
~ACPI();
|
||||
};
|
||||
|
||||
class MADT
|
||||
{
|
||||
public:
|
||||
struct APICHeader
|
||||
{
|
||||
uint8_t Type;
|
||||
uint8_t Length;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct MADTIOApic
|
||||
{
|
||||
struct APICHeader Header;
|
||||
uint8_t APICID;
|
||||
uint8_t reserved;
|
||||
uint32_t Address;
|
||||
uint32_t GSIBase;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct MADTIso
|
||||
{
|
||||
struct APICHeader Header;
|
||||
uint8_t BuSSource;
|
||||
uint8_t IRQSource;
|
||||
uint32_t GSI;
|
||||
uint16_t Flags;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct MADTNmi
|
||||
{
|
||||
struct APICHeader Header;
|
||||
uint8_t processor;
|
||||
uint16_t flags;
|
||||
uint8_t lint;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct LocalAPIC
|
||||
{
|
||||
struct APICHeader Header;
|
||||
uint8_t ACPIProcessorId;
|
||||
uint8_t APICId;
|
||||
uint32_t Flags;
|
||||
} __attribute__((packed));
|
||||
|
||||
struct LAPIC
|
||||
{
|
||||
uint8_t id;
|
||||
uintptr_t PhysicalAddress;
|
||||
void *VirtualAddress;
|
||||
};
|
||||
|
||||
Vector<MADTIOApic *> ioapic;
|
||||
Vector<MADTIso *> iso;
|
||||
Vector<MADTNmi *> nmi;
|
||||
Vector<LocalAPIC *> lapic;
|
||||
struct LAPIC *LAPICAddress;
|
||||
uint16_t CPUCores;
|
||||
|
||||
MADT(ACPI::MADTHeader *madt);
|
||||
~MADT();
|
||||
};
|
||||
|
||||
class DSDT : public Interrupts::Handler
|
||||
{
|
||||
private:
|
||||
uint32_t SMI_CMD = 0;
|
||||
uint8_t ACPI_ENABLE = 0;
|
||||
uint8_t ACPI_DISABLE = 0;
|
||||
uint32_t PM1a_CNT = 0;
|
||||
uint32_t PM1b_CNT = 0;
|
||||
uint16_t SLP_TYPa = 0;
|
||||
uint16_t SLP_TYPb = 0;
|
||||
uint16_t SLP_EN = 0;
|
||||
uint16_t SCI_EN = 0;
|
||||
uint8_t PM1_CNT_LEN = 0;
|
||||
|
||||
ACPI *acpi;
|
||||
void OnInterruptReceived(CPU::x64::TrapFrame *Frame);
|
||||
|
||||
public:
|
||||
bool ACPIShutdownSupported = false;
|
||||
|
||||
void Reboot();
|
||||
void Shutdown();
|
||||
|
||||
DSDT(ACPI *acpi);
|
||||
~DSDT();
|
||||
};
|
||||
}
|
||||
|
||||
#endif // !__FENNIX_KERNEL_ACPI_H__
|
||||
@ -1,354 +0,0 @@
|
||||
#include "apic.hpp"
|
||||
|
||||
#include <memory.hpp>
|
||||
#include <uart.hpp>
|
||||
#include <lock.hpp>
|
||||
#include <cpu.hpp>
|
||||
#include <smp.hpp>
|
||||
#include <io.h>
|
||||
|
||||
#include "../../../kernel.h"
|
||||
#include "../acpi.hpp"
|
||||
|
||||
NewLock(APICLock);
|
||||
|
||||
using namespace CPU::x64;
|
||||
|
||||
/*
|
||||
In constructor ‘APIC::APIC::APIC(int)’:
|
||||
warning: left shift count >= width of type
|
||||
| APICBaseAddress = BaseStruct.ApicBaseLo << 12u | BaseStruct.ApicBaseHi << 32u;
|
||||
| ~~~~~~~~~~~~~~~~~~~~~~^~~~~~
|
||||
*/
|
||||
#pragma GCC diagnostic ignored "-Wshift-count-overflow"
|
||||
|
||||
namespace APIC
|
||||
{
|
||||
// headache
|
||||
// https://www.amd.com/system/files/TechDocs/24593.pdf
|
||||
// https://www.naic.edu/~phil/software/intel/318148.pdf
|
||||
|
||||
uint32_t APIC::Read(uint32_t Register)
|
||||
{
|
||||
if (Register != APIC_ICRLO &&
|
||||
Register != APIC_ICRHI &&
|
||||
Register != APIC_ID)
|
||||
debug("APIC::Read(%#lx) [x2=%d]", Register, x2APICSupported ? 1 : 0);
|
||||
if (x2APICSupported)
|
||||
{
|
||||
if (Register != APIC_ICRHI)
|
||||
return rdmsr((Register >> 4) + 0x800);
|
||||
else
|
||||
return rdmsr(0x30 + 0x800);
|
||||
}
|
||||
else
|
||||
{
|
||||
CPU::MemBar::Barrier();
|
||||
uint32_t ret = *((volatile uint32_t *)((uintptr_t)APICBaseAddress + Register));
|
||||
CPU::MemBar::Barrier();
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
void APIC::Write(uint32_t Register, uint32_t Value)
|
||||
{
|
||||
if (Register != APIC_EOI &&
|
||||
Register != APIC_TDCR &&
|
||||
Register != APIC_TIMER &&
|
||||
Register != APIC_TICR &&
|
||||
Register != APIC_ICRLO &&
|
||||
Register != APIC_ICRHI)
|
||||
debug("APIC::Write(%#lx, %#lx) [x2=%d]", Register, Value, x2APICSupported ? 1 : 0);
|
||||
if (x2APICSupported)
|
||||
{
|
||||
if (Register != APIC_ICRHI)
|
||||
wrmsr((Register >> 4) + 0x800, Value);
|
||||
else
|
||||
wrmsr(MSR_X2APIC_ICR, Value);
|
||||
}
|
||||
else
|
||||
{
|
||||
CPU::MemBar::Barrier();
|
||||
*((volatile uint32_t *)(((uintptr_t)APICBaseAddress) + Register)) = Value;
|
||||
CPU::MemBar::Barrier();
|
||||
}
|
||||
}
|
||||
|
||||
void APIC::IOWrite(uint64_t Base, uint32_t Register, uint32_t Value)
|
||||
{
|
||||
debug("APIC::IOWrite(%#lx, %#lx, %#lx)", Base, Register, Value);
|
||||
CPU::MemBar::Barrier();
|
||||
*((volatile uint32_t *)(((uintptr_t)Base))) = Register;
|
||||
CPU::MemBar::Barrier();
|
||||
*((volatile uint32_t *)(((uintptr_t)Base + 16))) = Value;
|
||||
CPU::MemBar::Barrier();
|
||||
}
|
||||
|
||||
uint32_t APIC::IORead(uint64_t Base, uint32_t Register)
|
||||
{
|
||||
debug("APIC::IORead(%#lx, %#lx)", Base, Register);
|
||||
CPU::MemBar::Barrier();
|
||||
*((volatile uint32_t *)(((uintptr_t)Base))) = Register;
|
||||
CPU::MemBar::Barrier();
|
||||
uint32_t ret = *((volatile uint32_t *)(((uintptr_t)Base + 16)));
|
||||
CPU::MemBar::Barrier();
|
||||
return ret;
|
||||
}
|
||||
|
||||
void APIC::EOI() { this->Write(APIC_EOI, 0); }
|
||||
|
||||
void APIC::WaitForIPI()
|
||||
{
|
||||
InterruptCommandRegisterLow icr = {.raw = 0};
|
||||
do
|
||||
{
|
||||
icr.raw = this->Read(APIC_ICRLO);
|
||||
} while (icr.DeliveryStatus != Idle);
|
||||
}
|
||||
|
||||
void APIC::IPI(uint8_t CPU, InterruptCommandRegisterLow icr)
|
||||
{
|
||||
SmartCriticalSection(APICLock);
|
||||
if (x2APICSupported)
|
||||
{
|
||||
fixme("Not implemented for x2APIC");
|
||||
// wrmsr(MSR_X2APIC_ICR, ((uint64_t)CPU) << 32);
|
||||
}
|
||||
else
|
||||
{
|
||||
this->Write(APIC_ICRHI, (CPU << 24));
|
||||
this->Write(APIC_ICRLO, icr.raw);
|
||||
this->WaitForIPI();
|
||||
}
|
||||
}
|
||||
|
||||
void APIC::SendInitIPI(uint8_t CPU)
|
||||
{
|
||||
SmartCriticalSection(APICLock);
|
||||
if (x2APICSupported)
|
||||
{
|
||||
fixme("Not implemented for x2APIC");
|
||||
// wrmsr(MSR_X2APIC_ICR, ((uint64_t)CPU) << 32);
|
||||
}
|
||||
else
|
||||
{
|
||||
InterruptCommandRegisterLow icr = {.raw = 0};
|
||||
icr.DeliveryMode = INIT;
|
||||
icr.Level = Assert;
|
||||
this->Write(APIC_ICRHI, (CPU << 24));
|
||||
this->Write(APIC_ICRLO, icr.raw);
|
||||
this->WaitForIPI();
|
||||
}
|
||||
}
|
||||
|
||||
void APIC::SendStartupIPI(uint8_t CPU, uint64_t StartupAddress)
|
||||
{
|
||||
SmartCriticalSection(APICLock);
|
||||
if (x2APICSupported)
|
||||
{
|
||||
warn("Not tested for x2APIC");
|
||||
wrmsr(MSR_X2APIC_ICR, ((uint64_t)CPU) << 32 | StartupAddress);
|
||||
}
|
||||
else
|
||||
{
|
||||
InterruptCommandRegisterLow icr = {.raw = 0};
|
||||
icr.Vector = StartupAddress >> 12;
|
||||
icr.DeliveryMode = Startup;
|
||||
icr.Level = Assert;
|
||||
this->Write(APIC_ICRHI, (CPU << 24));
|
||||
this->Write(APIC_ICRLO, icr.raw);
|
||||
this->WaitForIPI();
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t APIC::IOGetMaxRedirect(uint32_t APICID)
|
||||
{
|
||||
uint32_t TableAddress = (this->IORead((((ACPI::MADT *)PowerManager->GetMADT())->ioapic[APICID]->Address), GetIOAPICVersion));
|
||||
return ((IOAPICVersion *)&TableAddress)->MaximumRedirectionEntry;
|
||||
}
|
||||
|
||||
void APIC::RawRedirectIRQ(uint8_t Vector, uint32_t GSI, uint16_t Flags, int CPU, int Status)
|
||||
{
|
||||
uint64_t Value = Vector;
|
||||
|
||||
int64_t IOAPICTarget = -1;
|
||||
for (uint64_t i = 0; ((ACPI::MADT *)PowerManager->GetMADT())->ioapic[i] != 0; i++)
|
||||
if (((ACPI::MADT *)PowerManager->GetMADT())->ioapic[i]->GSIBase <= GSI)
|
||||
if (((ACPI::MADT *)PowerManager->GetMADT())->ioapic[i]->GSIBase + IOGetMaxRedirect(i) > GSI)
|
||||
{
|
||||
IOAPICTarget = i;
|
||||
break;
|
||||
}
|
||||
|
||||
if (IOAPICTarget == -1)
|
||||
{
|
||||
error("No ISO table found for I/O APIC");
|
||||
return;
|
||||
}
|
||||
|
||||
// TODO: IOAPICRedirectEntry Entry = {.raw = 0};
|
||||
|
||||
if (Flags & ActiveHighLow)
|
||||
Value |= (1 << 13);
|
||||
|
||||
if (Flags & EdgeLevel)
|
||||
Value |= (1 << 15);
|
||||
|
||||
if (!Status)
|
||||
Value |= (1 << 16);
|
||||
|
||||
Value |= (((uintptr_t)CPU) << 56);
|
||||
uint32_t IORegister = (GSI - ((ACPI::MADT *)PowerManager->GetMADT())->ioapic[IOAPICTarget]->GSIBase) * 2 + 16;
|
||||
|
||||
this->IOWrite(((ACPI::MADT *)PowerManager->GetMADT())->ioapic[IOAPICTarget]->Address, IORegister, (uint32_t)Value);
|
||||
this->IOWrite(((ACPI::MADT *)PowerManager->GetMADT())->ioapic[IOAPICTarget]->Address, IORegister + 1, (uint32_t)(Value >> 32));
|
||||
}
|
||||
|
||||
void APIC::RedirectIRQ(int CPU, uint8_t IRQ, int Status)
|
||||
{
|
||||
for (uint64_t i = 0; i < ((ACPI::MADT *)PowerManager->GetMADT())->iso.size(); i++)
|
||||
if (((ACPI::MADT *)PowerManager->GetMADT())->iso[i]->IRQSource == IRQ)
|
||||
{
|
||||
debug("[ISO %d] Mapping to source IRQ%#d GSI:%#lx on CPU %d",
|
||||
i, ((ACPI::MADT *)PowerManager->GetMADT())->iso[i]->IRQSource, ((ACPI::MADT *)PowerManager->GetMADT())->iso[i]->GSI, CPU);
|
||||
|
||||
this->RawRedirectIRQ(((ACPI::MADT *)PowerManager->GetMADT())->iso[i]->IRQSource + 0x20, ((ACPI::MADT *)PowerManager->GetMADT())->iso[i]->GSI, ((ACPI::MADT *)PowerManager->GetMADT())->iso[i]->Flags, CPU, Status);
|
||||
return;
|
||||
}
|
||||
debug("Mapping IRQ%d on CPU %d", IRQ, CPU);
|
||||
this->RawRedirectIRQ(IRQ + 0x20, IRQ, 0, CPU, Status);
|
||||
}
|
||||
|
||||
void APIC::RedirectIRQs(int CPU)
|
||||
{
|
||||
SmartCriticalSection(APICLock);
|
||||
debug("Redirecting IRQs...");
|
||||
for (int i = 0; i < 16; i++)
|
||||
this->RedirectIRQ(CPU, i, 1);
|
||||
debug("Redirecting IRQs completed.");
|
||||
}
|
||||
|
||||
APIC::APIC(int Core)
|
||||
{
|
||||
SmartCriticalSection(APICLock);
|
||||
APIC_BASE BaseStruct = {.raw = rdmsr(MSR_APIC_BASE)};
|
||||
uint64_t BaseLow = BaseStruct.ApicBaseLo;
|
||||
uint64_t BaseHigh = BaseStruct.ApicBaseHi;
|
||||
this->APICBaseAddress = BaseLow << 12u | BaseHigh << 32u;
|
||||
trace("APIC Address: %#lx", this->APICBaseAddress);
|
||||
|
||||
uint32_t rcx;
|
||||
cpuid(1, 0, 0, &rcx, 0);
|
||||
if (rcx & CPUID_FEAT_RCX_x2APIC)
|
||||
{
|
||||
// this->x2APICSupported = true;
|
||||
warn("x2APIC not supported yet.");
|
||||
// wrmsr(MSR_APIC_BASE, (rdmsr(MSR_APIC_BASE) | (1 << 11)) & ~(1 << 10));
|
||||
BaseStruct.EN = 1;
|
||||
wrmsr(MSR_APIC_BASE, BaseStruct.raw);
|
||||
}
|
||||
else
|
||||
{
|
||||
BaseStruct.EN = 1;
|
||||
wrmsr(MSR_APIC_BASE, BaseStruct.raw);
|
||||
}
|
||||
|
||||
this->Write(APIC_TPR, 0x0);
|
||||
// this->Write(APIC_SVR, this->Read(APIC_SVR) | 0x100); // 0x1FF or 0x100 ? on https://wiki.osdev.org/APIC is 0x100
|
||||
|
||||
if (!this->x2APICSupported)
|
||||
{
|
||||
this->Write(APIC_DFR, 0xF0000000);
|
||||
this->Write(APIC_LDR, this->Read(APIC_ID));
|
||||
}
|
||||
|
||||
ACPI::MADT *madt = (ACPI::MADT *)PowerManager->GetMADT();
|
||||
|
||||
for (size_t i = 0; i < madt->nmi.size(); i++)
|
||||
{
|
||||
if (madt->nmi[i]->processor != 0xFF && Core != madt->nmi[i]->processor)
|
||||
return;
|
||||
|
||||
uint32_t nmi = 0x402;
|
||||
if (madt->nmi[i]->flags & 2)
|
||||
nmi |= 1 << 13;
|
||||
if (madt->nmi[i]->flags & 8)
|
||||
nmi |= 1 << 15;
|
||||
if (madt->nmi[i]->lint == 0)
|
||||
this->Write(APIC_LINT0, nmi);
|
||||
else if (madt->nmi[i]->lint == 1)
|
||||
this->Write(APIC_LINT1, nmi);
|
||||
}
|
||||
|
||||
// Setup the spurrious interrupt vector
|
||||
Spurious Spurious = {.raw = this->Read(APIC_SVR)};
|
||||
Spurious.Vector = IRQ223; // TODO: Should I map the IRQ to something?
|
||||
Spurious.Software = 1;
|
||||
this->Write(APIC_SVR, Spurious.raw);
|
||||
|
||||
static int once = 0;
|
||||
if (!once++)
|
||||
{
|
||||
// Disable PIT
|
||||
outb(0x43, 0x28);
|
||||
outb(0x40, 0x0);
|
||||
|
||||
// Disable PIC
|
||||
outb(0x21, 0xFF);
|
||||
outb(0xA1, 0xFF);
|
||||
}
|
||||
}
|
||||
|
||||
APIC::~APIC() {}
|
||||
|
||||
void Timer::OnInterruptReceived(TrapFrame *Frame) {}
|
||||
|
||||
void Timer::OneShot(uint32_t Vector, uint64_t Miliseconds)
|
||||
{
|
||||
SmartCriticalSection(APICLock);
|
||||
LVTTimer timer = {.raw = 0};
|
||||
timer.Vector = Vector;
|
||||
timer.TimerMode = 0;
|
||||
if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_TCG) != 0)
|
||||
this->lapic->Write(APIC_TDCR, DivideBy128);
|
||||
else
|
||||
this->lapic->Write(APIC_TDCR, DivideBy16);
|
||||
this->lapic->Write(APIC_TICR, Ticks * Miliseconds);
|
||||
this->lapic->Write(APIC_TIMER, timer.raw);
|
||||
}
|
||||
|
||||
Timer::Timer(APIC *apic) : Interrupts::Handler(IRQ0)
|
||||
{
|
||||
SmartCriticalSection(APICLock);
|
||||
this->lapic = apic;
|
||||
LVTTimerDivide Divider = DivideBy16;
|
||||
|
||||
trace("Initializing APIC timer on CPU %d", GetCurrentCPU()->ID);
|
||||
|
||||
this->lapic->Write(APIC_TDCR, Divider);
|
||||
this->lapic->Write(APIC_TICR, 0xFFFFFFFF);
|
||||
|
||||
TimeManager->Sleep(10);
|
||||
|
||||
// Mask the timer
|
||||
this->lapic->Write(APIC_TIMER, 0x10000 /* LVTTimer.Mask flag */);
|
||||
Ticks = 0xFFFFFFFF - this->lapic->Read(APIC_TCCR);
|
||||
|
||||
// Config for IRQ0 timer
|
||||
LVTTimer timer = {.raw = 0};
|
||||
timer.Vector = IRQ0;
|
||||
timer.Mask = Unmasked;
|
||||
timer.TimerMode = LVTTimerMode::OneShot;
|
||||
|
||||
// Initialize APIC timer
|
||||
this->lapic->Write(APIC_TDCR, Divider);
|
||||
this->lapic->Write(APIC_TICR, Ticks);
|
||||
this->lapic->Write(APIC_TIMER, timer.raw);
|
||||
trace("%d APIC Timer %d ticks in.", GetCurrentCPU()->ID, Ticks);
|
||||
KPrint("APIC Timer: \e8888FF%ld\eCCCCCC ticks.", Ticks);
|
||||
}
|
||||
|
||||
Timer::~Timer()
|
||||
{
|
||||
}
|
||||
}
|
||||
@ -1,153 +0,0 @@
|
||||
#include "gdt.hpp"
|
||||
|
||||
#include <memory.hpp>
|
||||
#include <smp.hpp>
|
||||
#include <cpu.hpp>
|
||||
#include <debug.h>
|
||||
|
||||
namespace GlobalDescriptorTable
|
||||
{
|
||||
static GlobalDescriptorTableEntries GDTEntriesTemplate = {
|
||||
// null
|
||||
{.Length = 0x0,
|
||||
.BaseLow = 0x0,
|
||||
.BaseMiddle = 0x0,
|
||||
.Access = {.Raw = 0x0},
|
||||
.Flags = {.Raw = 0x0},
|
||||
.BaseHigh = 0x0},
|
||||
|
||||
// kernel code
|
||||
{.Length = 0x0,
|
||||
.BaseLow = 0x0,
|
||||
.BaseMiddle = 0x0,
|
||||
.Access = {.A = 0,
|
||||
.RW = 1,
|
||||
.DC = 0,
|
||||
.E = 1,
|
||||
.S = 1,
|
||||
.DPL = 0,
|
||||
.P = 1},
|
||||
.Flags = {.Unknown = 0x0, .L = 1},
|
||||
.BaseHigh = 0x0},
|
||||
|
||||
// kernel data
|
||||
{.Length = 0x0,
|
||||
.BaseLow = 0x0,
|
||||
.BaseMiddle = 0x0,
|
||||
.Access = {.A = 0,
|
||||
.RW = 1,
|
||||
.DC = 0,
|
||||
.E = 0,
|
||||
.S = 1,
|
||||
.DPL = 0,
|
||||
.P = 1},
|
||||
.Flags = {.Raw = 0x0},
|
||||
.BaseHigh = 0x0},
|
||||
|
||||
// user data
|
||||
{.Length = 0x0,
|
||||
.BaseLow = 0x0,
|
||||
.BaseMiddle = 0x0,
|
||||
.Access = {.A = 0,
|
||||
.RW = 1,
|
||||
.DC = 0,
|
||||
.E = 0,
|
||||
.S = 1,
|
||||
.DPL = 3,
|
||||
.P = 1},
|
||||
.Flags = {.Raw = 0x0},
|
||||
.BaseHigh = 0x0},
|
||||
|
||||
// user code
|
||||
{.Length = 0x0,
|
||||
.BaseLow = 0x0,
|
||||
.BaseMiddle = 0x0,
|
||||
.Access = {.A = 0,
|
||||
.RW = 1,
|
||||
.DC = 0,
|
||||
.E = 1,
|
||||
.S = 1,
|
||||
.DPL = 3,
|
||||
.P = 1},
|
||||
.Flags = {.Unknown = 0x0, .L = 1},
|
||||
.BaseHigh = 0x0},
|
||||
|
||||
// tss
|
||||
{}};
|
||||
|
||||
static GlobalDescriptorTableEntries GDTEntries[MAX_CPU];
|
||||
GlobalDescriptorTableDescriptor gdt[MAX_CPU];
|
||||
|
||||
TaskStateSegment tss[MAX_CPU] = {
|
||||
0,
|
||||
{0, 0, 0},
|
||||
0,
|
||||
{0, 0, 0, 0, 0, 0, 0},
|
||||
0,
|
||||
0,
|
||||
};
|
||||
|
||||
void *CPUStackPointer[MAX_CPU];
|
||||
|
||||
SafeFunction void Init(int Core)
|
||||
{
|
||||
memcpy(&GDTEntries[Core], &GDTEntriesTemplate, sizeof(GlobalDescriptorTableEntries));
|
||||
gdt[Core] = {.Length = sizeof(GlobalDescriptorTableEntries) - 1, .Entries = &GDTEntries[Core]};
|
||||
|
||||
debug("Kernel: Code Access: %ld; Data Access: %ld", GDTEntries[Core].Code.Access.Raw, GDTEntries[Core].Data.Access.Raw);
|
||||
debug("Kernel: Code Flags: %ld; Data Flags: %ld", GDTEntries[Core].Code.Flags.Raw, GDTEntries[Core].Data.Flags.Raw);
|
||||
debug("User: Code Access: %ld; Data Access: %ld", GDTEntries[Core].UserCode.Access.Raw, GDTEntries[Core].UserData.Access.Raw);
|
||||
debug("User: Code Flags: %ld; Data Flags: %ld", GDTEntries[Core].UserCode.Flags.Raw, GDTEntries[Core].UserData.Flags.Raw);
|
||||
CPU::x64::lgdt(&gdt[Core]);
|
||||
|
||||
asmv("movq %%rsp, %%rax\n"
|
||||
"pushq $16\n"
|
||||
"pushq %%rax\n"
|
||||
"pushfq\n"
|
||||
"pushq $8\n"
|
||||
"pushq $1f\n"
|
||||
"iretq\n"
|
||||
"1:\n"
|
||||
"movw $16, %%ax\n"
|
||||
"movw %%ax, %%ds\n"
|
||||
"movw %%ax, %%es\n" ::
|
||||
: "memory", "rax");
|
||||
|
||||
CPUStackPointer[Core] = KernelAllocator.RequestPages(TO_PAGES(STACK_SIZE));
|
||||
|
||||
uint64_t Base = (uint64_t)&tss[Core];
|
||||
uint64_t Limit = Base + sizeof(TaskStateSegment);
|
||||
gdt[Core].Entries->TaskStateSegment.Length = Limit & 0xFFFF;
|
||||
gdt[Core].Entries->TaskStateSegment.BaseLow = Base & 0xFFFF;
|
||||
gdt[Core].Entries->TaskStateSegment.BaseMiddle = (Base >> 16) & 0xFF;
|
||||
gdt[Core].Entries->TaskStateSegment.BaseHigh = (Base >> 24) & 0xFF;
|
||||
gdt[Core].Entries->TaskStateSegment.BaseUpper = (Base >> 32) & 0xFFFFFFFF;
|
||||
gdt[Core].Entries->TaskStateSegment.Flags = {.A = 1, .RW = 0, .DC = 0, .E = 1, .S = 0, .DPL = 0, .P = 1};
|
||||
gdt[Core].Entries->TaskStateSegment.Granularity = (0 << 4) | ((Limit >> 16) & 0xF);
|
||||
|
||||
tss[Core].IOMapBaseAddressOffset = sizeof(TaskStateSegment);
|
||||
tss[Core].StackPointer[0] = (uint64_t)CPUStackPointer[Core] + STACK_SIZE;
|
||||
tss[Core].InterruptStackTable[0] = (uint64_t)KernelAllocator.RequestPages(TO_PAGES(STACK_SIZE)) + STACK_SIZE;
|
||||
tss[Core].InterruptStackTable[1] = (uint64_t)KernelAllocator.RequestPages(TO_PAGES(STACK_SIZE)) + STACK_SIZE;
|
||||
tss[Core].InterruptStackTable[2] = (uint64_t)KernelAllocator.RequestPages(TO_PAGES(STACK_SIZE)) + STACK_SIZE;
|
||||
|
||||
CPU::x64::ltr(GDT_TSS);
|
||||
asmv("mov %%rsp, %0"
|
||||
: "=r"(tss[Core].StackPointer[0]));
|
||||
|
||||
trace("GDT_KERNEL_CODE: %#lx", GDT_KERNEL_CODE);
|
||||
trace("GDT_KERNEL_DATA: %#lx", GDT_KERNEL_DATA);
|
||||
trace("GDT_USER_CODE: %#lx", GDT_USER_CODE);
|
||||
trace("GDT_USER_DATA: %#lx", GDT_USER_DATA);
|
||||
trace("GDT_TSS: %#lx", GDT_TSS);
|
||||
trace("Global Descriptor Table initialized");
|
||||
}
|
||||
|
||||
SafeFunction void SetKernelStack(void *Stack)
|
||||
{
|
||||
if (Stack)
|
||||
tss[GetCurrentCPU()->ID].StackPointer[0] = (uint64_t)Stack;
|
||||
else
|
||||
tss[GetCurrentCPU()->ID].StackPointer[0] = (uint64_t)CPUStackPointer[GetCurrentCPU()->ID] + STACK_SIZE;
|
||||
}
|
||||
}
|
||||
@ -1,755 +0,0 @@
|
||||
#include "idt.hpp"
|
||||
|
||||
#include <cpu.hpp>
|
||||
#include <debug.h>
|
||||
#include <io.h>
|
||||
|
||||
#include "gdt.hpp"
|
||||
|
||||
extern "C" void MainInterruptHandler(void *Data);
|
||||
extern "C" void ExceptionHandler(void *Data);
|
||||
|
||||
namespace InterruptDescriptorTable
|
||||
{
|
||||
static InterruptDescriptorTableEntry Entries[0x100];
|
||||
|
||||
InterruptDescriptorTableDescriptor idtd = {.Length = sizeof(Entries) - 1,
|
||||
.Entries = Entries};
|
||||
|
||||
void SetEntry(uint8_t Index,
|
||||
void (*Base)(),
|
||||
InterruptDescriptorTableFlags Attribute,
|
||||
uint8_t InterruptStackTable,
|
||||
InterruptDescriptorTableFlags Ring,
|
||||
uint16_t SegmentSelector)
|
||||
{
|
||||
Entries[Index].BaseLow = (uint16_t)((uint64_t)Base & 0xFFFF);
|
||||
Entries[Index].BaseHigh = (uint64_t)((uint64_t)Base >> 16 /* & 0xFFFF */);
|
||||
Entries[Index].SegmentSelector = SegmentSelector;
|
||||
Entries[Index].Flags = Attribute;
|
||||
Entries[Index].Reserved1 = 0;
|
||||
Entries[Index].Reserved2 = 0;
|
||||
Entries[Index].Reserved3 = 0;
|
||||
Entries[Index].InterruptStackTable = InterruptStackTable;
|
||||
Entries[Index].Ring = Ring;
|
||||
Entries[Index].Present = 1;
|
||||
}
|
||||
|
||||
extern "C" __attribute__((naked, used, no_stack_protector)) void ExceptionHandlerStub()
|
||||
{
|
||||
asm(
|
||||
// "cmp $0x1000, %rsp\n" // Just in case the stack is corrupted
|
||||
// "jng .skip_swap_check_1\n" /* if is not greater than */
|
||||
// "cmpw $0x8, 0x8(%rsp)\n"
|
||||
// "je .skip_swap_check_1\n"
|
||||
// "swapgs\n"
|
||||
// ".skip_swap_check_1:\n"
|
||||
|
||||
"cld\n" // clear direction flag
|
||||
|
||||
// push all registers
|
||||
"pushq %rax\n"
|
||||
"pushq %rbx\n"
|
||||
"pushq %rcx\n"
|
||||
"pushq %rdx\n"
|
||||
"pushq %rsi\n"
|
||||
"pushq %rdi\n"
|
||||
"pushq %rbp\n"
|
||||
"pushq %r8\n"
|
||||
"pushq %r9\n"
|
||||
"pushq %r10\n"
|
||||
"pushq %r11\n"
|
||||
"pushq %r12\n"
|
||||
"pushq %r13\n"
|
||||
"pushq %r14\n"
|
||||
"pushq %r15\n"
|
||||
|
||||
"movq %rsp, %rdi\n"
|
||||
"call ExceptionHandler\n"
|
||||
|
||||
// pop all registers
|
||||
"popq %r15\n"
|
||||
"popq %r14\n"
|
||||
"popq %r13\n"
|
||||
"popq %r12\n"
|
||||
"popq %r11\n"
|
||||
"popq %r10\n"
|
||||
"popq %r9\n"
|
||||
"popq %r8\n"
|
||||
"popq %rbp\n"
|
||||
"popq %rdi\n"
|
||||
"popq %rsi\n"
|
||||
"popq %rdx\n"
|
||||
"popq %rcx\n"
|
||||
"popq %rbx\n"
|
||||
"popq %rax\n"
|
||||
|
||||
"addq $16, %rsp\n"
|
||||
|
||||
// "cmp $0x1000, %rsp\n"
|
||||
// "jng .skip_swap_check_2\n"
|
||||
// "cmpw $0x8, 0x8(%rsp)\n"
|
||||
// "je .skip_swap_check_2\n"
|
||||
// "swapgs\n"
|
||||
// ".skip_swap_check_2:\n"
|
||||
|
||||
"iretq"); // pop CS RIP RFLAGS SS ESP
|
||||
}
|
||||
|
||||
extern "C" void WarnSwapgs() { warn("swapgs"); }
|
||||
|
||||
extern "C" __attribute__((naked, used, no_stack_protector)) void InterruptHandlerStub()
|
||||
{
|
||||
asm(
|
||||
// "cmp $0x1000, %rsp\n"
|
||||
// "jng .skip_swap_check__1\n"
|
||||
// "cmpw $0x8, 0x8(%rsp)\n"
|
||||
// "je .skip_swap_check__1\n"
|
||||
// "swapgs\n"
|
||||
// "call WarnSwapgs\n"
|
||||
// ".skip_swap_check__1:\n"
|
||||
|
||||
"cld\n"
|
||||
"pushq %rax\n"
|
||||
"pushq %rbx\n"
|
||||
"pushq %rcx\n"
|
||||
"pushq %rdx\n"
|
||||
"pushq %rsi\n"
|
||||
"pushq %rdi\n"
|
||||
"pushq %rbp\n"
|
||||
"pushq %r8\n"
|
||||
"pushq %r9\n"
|
||||
"pushq %r10\n"
|
||||
"pushq %r11\n"
|
||||
"pushq %r12\n"
|
||||
"pushq %r13\n"
|
||||
"pushq %r14\n"
|
||||
"pushq %r15\n"
|
||||
|
||||
"movq %rsp, %rdi\n"
|
||||
"call MainInterruptHandler\n"
|
||||
|
||||
"popq %r15\n"
|
||||
"popq %r14\n"
|
||||
"popq %r13\n"
|
||||
"popq %r12\n"
|
||||
"popq %r11\n"
|
||||
"popq %r10\n"
|
||||
"popq %r9\n"
|
||||
"popq %r8\n"
|
||||
"popq %rbp\n"
|
||||
"popq %rdi\n"
|
||||
"popq %rsi\n"
|
||||
"popq %rdx\n"
|
||||
"popq %rcx\n"
|
||||
"popq %rbx\n"
|
||||
"popq %rax\n"
|
||||
|
||||
"addq $16, %rsp\n"
|
||||
|
||||
// "cmp $0x1000, %rsp\n"
|
||||
// "jng .skip_swap_check__2\n"
|
||||
// "cmpw $0x8, 0x8(%rsp)\n"
|
||||
// "je .skip_swap_check__2\n"
|
||||
// "call WarnSwapgs\n"
|
||||
// "swapgs\n"
|
||||
// ".skip_swap_check__2:\n"
|
||||
|
||||
"iretq");
|
||||
}
|
||||
|
||||
#pragma region Exceptions
|
||||
|
||||
#define EXCEPTION_HANDLER(num) \
|
||||
__attribute__((naked, no_stack_protector)) static void InterruptHandler_##num() \
|
||||
{ \
|
||||
asm("pushq $0\npushq $" #num "\n" \
|
||||
"jmp ExceptionHandlerStub"); \
|
||||
}
|
||||
|
||||
#define EXCEPTION_ERROR_HANDLER(num) \
|
||||
__attribute__((naked, no_stack_protector)) static void InterruptHandler_##num() \
|
||||
{ \
|
||||
asm("pushq $" #num "\n" \
|
||||
"jmp ExceptionHandlerStub"); \
|
||||
}
|
||||
|
||||
#define INTERRUPT_HANDLER(num) \
|
||||
__attribute__((naked, used, no_stack_protector)) void InterruptHandler_##num() \
|
||||
{ \
|
||||
asm("pushq $0\npushq $" #num "\n" \
|
||||
"jmp InterruptHandlerStub\n"); \
|
||||
}
|
||||
|
||||
/* ISR */
|
||||
|
||||
EXCEPTION_HANDLER(0x0);
|
||||
EXCEPTION_HANDLER(0x1);
|
||||
EXCEPTION_HANDLER(0x2);
|
||||
EXCEPTION_HANDLER(0x3);
|
||||
EXCEPTION_HANDLER(0x4);
|
||||
EXCEPTION_HANDLER(0x5);
|
||||
EXCEPTION_HANDLER(0x6);
|
||||
EXCEPTION_HANDLER(0x7);
|
||||
EXCEPTION_ERROR_HANDLER(0x8);
|
||||
EXCEPTION_HANDLER(0x9);
|
||||
EXCEPTION_ERROR_HANDLER(0xa);
|
||||
EXCEPTION_ERROR_HANDLER(0xb);
|
||||
EXCEPTION_ERROR_HANDLER(0xc);
|
||||
EXCEPTION_ERROR_HANDLER(0xd);
|
||||
EXCEPTION_ERROR_HANDLER(0xe);
|
||||
EXCEPTION_HANDLER(0xf);
|
||||
EXCEPTION_ERROR_HANDLER(0x10);
|
||||
EXCEPTION_HANDLER(0x11);
|
||||
EXCEPTION_HANDLER(0x12);
|
||||
EXCEPTION_HANDLER(0x13);
|
||||
EXCEPTION_HANDLER(0x14);
|
||||
EXCEPTION_HANDLER(0x15);
|
||||
EXCEPTION_HANDLER(0x16);
|
||||
EXCEPTION_HANDLER(0x17);
|
||||
EXCEPTION_HANDLER(0x18);
|
||||
EXCEPTION_HANDLER(0x19);
|
||||
EXCEPTION_HANDLER(0x1a);
|
||||
EXCEPTION_HANDLER(0x1b);
|
||||
EXCEPTION_HANDLER(0x1c);
|
||||
EXCEPTION_HANDLER(0x1d);
|
||||
EXCEPTION_HANDLER(0x1e);
|
||||
EXCEPTION_HANDLER(0x1f);
|
||||
|
||||
/* IRQ */
|
||||
|
||||
INTERRUPT_HANDLER(0x20)
|
||||
INTERRUPT_HANDLER(0x21)
|
||||
INTERRUPT_HANDLER(0x22)
|
||||
INTERRUPT_HANDLER(0x23)
|
||||
INTERRUPT_HANDLER(0x24)
|
||||
INTERRUPT_HANDLER(0x25)
|
||||
INTERRUPT_HANDLER(0x26)
|
||||
INTERRUPT_HANDLER(0x27)
|
||||
INTERRUPT_HANDLER(0x28)
|
||||
INTERRUPT_HANDLER(0x29)
|
||||
INTERRUPT_HANDLER(0x2a)
|
||||
INTERRUPT_HANDLER(0x2b)
|
||||
INTERRUPT_HANDLER(0x2c)
|
||||
INTERRUPT_HANDLER(0x2d)
|
||||
INTERRUPT_HANDLER(0x2e)
|
||||
INTERRUPT_HANDLER(0x2f)
|
||||
|
||||
/* Reserved by OS */
|
||||
|
||||
INTERRUPT_HANDLER(0x30)
|
||||
INTERRUPT_HANDLER(0x31)
|
||||
INTERRUPT_HANDLER(0x32)
|
||||
INTERRUPT_HANDLER(0x33)
|
||||
INTERRUPT_HANDLER(0x34)
|
||||
INTERRUPT_HANDLER(0x35)
|
||||
INTERRUPT_HANDLER(0x36)
|
||||
INTERRUPT_HANDLER(0x37)
|
||||
INTERRUPT_HANDLER(0x38)
|
||||
INTERRUPT_HANDLER(0x39)
|
||||
INTERRUPT_HANDLER(0x3a)
|
||||
INTERRUPT_HANDLER(0x3b)
|
||||
INTERRUPT_HANDLER(0x3c)
|
||||
INTERRUPT_HANDLER(0x3d)
|
||||
|
||||
/* Free */
|
||||
|
||||
INTERRUPT_HANDLER(0x3e)
|
||||
INTERRUPT_HANDLER(0x3f)
|
||||
INTERRUPT_HANDLER(0x40)
|
||||
INTERRUPT_HANDLER(0x41)
|
||||
INTERRUPT_HANDLER(0x42)
|
||||
INTERRUPT_HANDLER(0x43)
|
||||
INTERRUPT_HANDLER(0x44)
|
||||
INTERRUPT_HANDLER(0x45)
|
||||
INTERRUPT_HANDLER(0x46)
|
||||
INTERRUPT_HANDLER(0x47)
|
||||
INTERRUPT_HANDLER(0x48)
|
||||
INTERRUPT_HANDLER(0x49)
|
||||
INTERRUPT_HANDLER(0x4a)
|
||||
INTERRUPT_HANDLER(0x4b)
|
||||
INTERRUPT_HANDLER(0x4c)
|
||||
INTERRUPT_HANDLER(0x4d)
|
||||
INTERRUPT_HANDLER(0x4e)
|
||||
INTERRUPT_HANDLER(0x4f)
|
||||
INTERRUPT_HANDLER(0x50)
|
||||
INTERRUPT_HANDLER(0x51)
|
||||
INTERRUPT_HANDLER(0x52)
|
||||
INTERRUPT_HANDLER(0x53)
|
||||
INTERRUPT_HANDLER(0x54)
|
||||
INTERRUPT_HANDLER(0x55)
|
||||
INTERRUPT_HANDLER(0x56)
|
||||
INTERRUPT_HANDLER(0x57)
|
||||
INTERRUPT_HANDLER(0x58)
|
||||
INTERRUPT_HANDLER(0x59)
|
||||
INTERRUPT_HANDLER(0x5a)
|
||||
INTERRUPT_HANDLER(0x5b)
|
||||
INTERRUPT_HANDLER(0x5c)
|
||||
INTERRUPT_HANDLER(0x5d)
|
||||
INTERRUPT_HANDLER(0x5e)
|
||||
INTERRUPT_HANDLER(0x5f)
|
||||
INTERRUPT_HANDLER(0x60)
|
||||
INTERRUPT_HANDLER(0x61)
|
||||
INTERRUPT_HANDLER(0x62)
|
||||
INTERRUPT_HANDLER(0x63)
|
||||
INTERRUPT_HANDLER(0x64)
|
||||
INTERRUPT_HANDLER(0x65)
|
||||
INTERRUPT_HANDLER(0x66)
|
||||
INTERRUPT_HANDLER(0x67)
|
||||
INTERRUPT_HANDLER(0x68)
|
||||
INTERRUPT_HANDLER(0x69)
|
||||
INTERRUPT_HANDLER(0x6a)
|
||||
INTERRUPT_HANDLER(0x6b)
|
||||
INTERRUPT_HANDLER(0x6c)
|
||||
INTERRUPT_HANDLER(0x6d)
|
||||
INTERRUPT_HANDLER(0x6e)
|
||||
INTERRUPT_HANDLER(0x6f)
|
||||
INTERRUPT_HANDLER(0x70)
|
||||
INTERRUPT_HANDLER(0x71)
|
||||
INTERRUPT_HANDLER(0x72)
|
||||
INTERRUPT_HANDLER(0x73)
|
||||
INTERRUPT_HANDLER(0x74)
|
||||
INTERRUPT_HANDLER(0x75)
|
||||
INTERRUPT_HANDLER(0x76)
|
||||
INTERRUPT_HANDLER(0x77)
|
||||
INTERRUPT_HANDLER(0x78)
|
||||
INTERRUPT_HANDLER(0x79)
|
||||
INTERRUPT_HANDLER(0x7a)
|
||||
INTERRUPT_HANDLER(0x7b)
|
||||
INTERRUPT_HANDLER(0x7c)
|
||||
INTERRUPT_HANDLER(0x7d)
|
||||
INTERRUPT_HANDLER(0x7e)
|
||||
INTERRUPT_HANDLER(0x7f)
|
||||
INTERRUPT_HANDLER(0x80)
|
||||
INTERRUPT_HANDLER(0x81)
|
||||
INTERRUPT_HANDLER(0x82)
|
||||
INTERRUPT_HANDLER(0x83)
|
||||
INTERRUPT_HANDLER(0x84)
|
||||
INTERRUPT_HANDLER(0x85)
|
||||
INTERRUPT_HANDLER(0x86)
|
||||
INTERRUPT_HANDLER(0x87)
|
||||
INTERRUPT_HANDLER(0x88)
|
||||
INTERRUPT_HANDLER(0x89)
|
||||
INTERRUPT_HANDLER(0x8a)
|
||||
INTERRUPT_HANDLER(0x8b)
|
||||
INTERRUPT_HANDLER(0x8c)
|
||||
INTERRUPT_HANDLER(0x8d)
|
||||
INTERRUPT_HANDLER(0x8e)
|
||||
INTERRUPT_HANDLER(0x8f)
|
||||
INTERRUPT_HANDLER(0x90)
|
||||
INTERRUPT_HANDLER(0x91)
|
||||
INTERRUPT_HANDLER(0x92)
|
||||
INTERRUPT_HANDLER(0x93)
|
||||
INTERRUPT_HANDLER(0x94)
|
||||
INTERRUPT_HANDLER(0x95)
|
||||
INTERRUPT_HANDLER(0x96)
|
||||
INTERRUPT_HANDLER(0x97)
|
||||
INTERRUPT_HANDLER(0x98)
|
||||
INTERRUPT_HANDLER(0x99)
|
||||
INTERRUPT_HANDLER(0x9a)
|
||||
INTERRUPT_HANDLER(0x9b)
|
||||
INTERRUPT_HANDLER(0x9c)
|
||||
INTERRUPT_HANDLER(0x9d)
|
||||
INTERRUPT_HANDLER(0x9e)
|
||||
INTERRUPT_HANDLER(0x9f)
|
||||
INTERRUPT_HANDLER(0xa0)
|
||||
INTERRUPT_HANDLER(0xa1)
|
||||
INTERRUPT_HANDLER(0xa2)
|
||||
INTERRUPT_HANDLER(0xa3)
|
||||
INTERRUPT_HANDLER(0xa4)
|
||||
INTERRUPT_HANDLER(0xa5)
|
||||
INTERRUPT_HANDLER(0xa6)
|
||||
INTERRUPT_HANDLER(0xa7)
|
||||
INTERRUPT_HANDLER(0xa8)
|
||||
INTERRUPT_HANDLER(0xa9)
|
||||
INTERRUPT_HANDLER(0xaa)
|
||||
INTERRUPT_HANDLER(0xab)
|
||||
INTERRUPT_HANDLER(0xac)
|
||||
INTERRUPT_HANDLER(0xad)
|
||||
INTERRUPT_HANDLER(0xae)
|
||||
INTERRUPT_HANDLER(0xaf)
|
||||
INTERRUPT_HANDLER(0xb0)
|
||||
INTERRUPT_HANDLER(0xb1)
|
||||
INTERRUPT_HANDLER(0xb2)
|
||||
INTERRUPT_HANDLER(0xb3)
|
||||
INTERRUPT_HANDLER(0xb4)
|
||||
INTERRUPT_HANDLER(0xb5)
|
||||
INTERRUPT_HANDLER(0xb6)
|
||||
INTERRUPT_HANDLER(0xb7)
|
||||
INTERRUPT_HANDLER(0xb8)
|
||||
INTERRUPT_HANDLER(0xb9)
|
||||
INTERRUPT_HANDLER(0xba)
|
||||
INTERRUPT_HANDLER(0xbb)
|
||||
INTERRUPT_HANDLER(0xbc)
|
||||
INTERRUPT_HANDLER(0xbd)
|
||||
INTERRUPT_HANDLER(0xbe)
|
||||
INTERRUPT_HANDLER(0xbf)
|
||||
INTERRUPT_HANDLER(0xc0)
|
||||
INTERRUPT_HANDLER(0xc1)
|
||||
INTERRUPT_HANDLER(0xc2)
|
||||
INTERRUPT_HANDLER(0xc3)
|
||||
INTERRUPT_HANDLER(0xc4)
|
||||
INTERRUPT_HANDLER(0xc5)
|
||||
INTERRUPT_HANDLER(0xc6)
|
||||
INTERRUPT_HANDLER(0xc7)
|
||||
INTERRUPT_HANDLER(0xc8)
|
||||
INTERRUPT_HANDLER(0xc9)
|
||||
INTERRUPT_HANDLER(0xca)
|
||||
INTERRUPT_HANDLER(0xcb)
|
||||
INTERRUPT_HANDLER(0xcc)
|
||||
INTERRUPT_HANDLER(0xcd)
|
||||
INTERRUPT_HANDLER(0xce)
|
||||
INTERRUPT_HANDLER(0xcf)
|
||||
INTERRUPT_HANDLER(0xd0)
|
||||
INTERRUPT_HANDLER(0xd1)
|
||||
INTERRUPT_HANDLER(0xd2)
|
||||
INTERRUPT_HANDLER(0xd3)
|
||||
INTERRUPT_HANDLER(0xd4)
|
||||
INTERRUPT_HANDLER(0xd5)
|
||||
INTERRUPT_HANDLER(0xd6)
|
||||
INTERRUPT_HANDLER(0xd7)
|
||||
INTERRUPT_HANDLER(0xd8)
|
||||
INTERRUPT_HANDLER(0xd9)
|
||||
INTERRUPT_HANDLER(0xda)
|
||||
INTERRUPT_HANDLER(0xdb)
|
||||
INTERRUPT_HANDLER(0xdc)
|
||||
INTERRUPT_HANDLER(0xdd)
|
||||
INTERRUPT_HANDLER(0xde)
|
||||
INTERRUPT_HANDLER(0xdf)
|
||||
INTERRUPT_HANDLER(0xe0)
|
||||
INTERRUPT_HANDLER(0xe1)
|
||||
INTERRUPT_HANDLER(0xe2)
|
||||
INTERRUPT_HANDLER(0xe3)
|
||||
INTERRUPT_HANDLER(0xe4)
|
||||
INTERRUPT_HANDLER(0xe5)
|
||||
INTERRUPT_HANDLER(0xe6)
|
||||
INTERRUPT_HANDLER(0xe7)
|
||||
INTERRUPT_HANDLER(0xe8)
|
||||
INTERRUPT_HANDLER(0xe9)
|
||||
INTERRUPT_HANDLER(0xea)
|
||||
INTERRUPT_HANDLER(0xeb)
|
||||
INTERRUPT_HANDLER(0xec)
|
||||
INTERRUPT_HANDLER(0xed)
|
||||
INTERRUPT_HANDLER(0xee)
|
||||
INTERRUPT_HANDLER(0xef)
|
||||
INTERRUPT_HANDLER(0xf0)
|
||||
INTERRUPT_HANDLER(0xf1)
|
||||
INTERRUPT_HANDLER(0xf2)
|
||||
INTERRUPT_HANDLER(0xf3)
|
||||
INTERRUPT_HANDLER(0xf4)
|
||||
INTERRUPT_HANDLER(0xf5)
|
||||
INTERRUPT_HANDLER(0xf6)
|
||||
INTERRUPT_HANDLER(0xf7)
|
||||
INTERRUPT_HANDLER(0xf8)
|
||||
INTERRUPT_HANDLER(0xf9)
|
||||
INTERRUPT_HANDLER(0xfa)
|
||||
INTERRUPT_HANDLER(0xfb)
|
||||
INTERRUPT_HANDLER(0xfc)
|
||||
INTERRUPT_HANDLER(0xfd)
|
||||
INTERRUPT_HANDLER(0xfe)
|
||||
INTERRUPT_HANDLER(0xff)
|
||||
|
||||
#pragma endregion Exceptions
|
||||
|
||||
void Init(int Core)
|
||||
{
|
||||
static int once = 0;
|
||||
if (!once++)
|
||||
{
|
||||
// PIC
|
||||
outb(0x20, 0x10 | 0x1);
|
||||
outb(0x80, 0);
|
||||
outb(0xA0, 0x10 | 0x10);
|
||||
outb(0x80, 0);
|
||||
|
||||
outb(0x21, 0x20);
|
||||
outb(0x80, 0);
|
||||
outb(0xA1, 0x28);
|
||||
outb(0x80, 0);
|
||||
|
||||
outb(0x21, 0x04);
|
||||
outb(0x80, 0);
|
||||
outb(0xA1, 0x02);
|
||||
outb(0x80, 0);
|
||||
|
||||
outb(0x21, 1);
|
||||
outb(0x80, 0);
|
||||
outb(0xA1, 1);
|
||||
outb(0x80, 0);
|
||||
|
||||
// Masking and disabling PIC
|
||||
outb(0x21, 0xff);
|
||||
outb(0x80, 0);
|
||||
outb(0xA1, 0xff);
|
||||
}
|
||||
|
||||
/* ISR */
|
||||
|
||||
SetEntry(0x0, InterruptHandler_0x0, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x1, InterruptHandler_0x1, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x2, InterruptHandler_0x2, FlagGate_32BIT_TRAP, 2, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x3, InterruptHandler_0x3, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x4, InterruptHandler_0x4, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x5, InterruptHandler_0x5, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x6, InterruptHandler_0x6, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x7, InterruptHandler_0x7, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x8, InterruptHandler_0x8, FlagGate_32BIT_TRAP, 3, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x9, InterruptHandler_0x9, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xa, InterruptHandler_0xa, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xb, InterruptHandler_0xb, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xc, InterruptHandler_0xc, FlagGate_32BIT_TRAP, 3, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xd, InterruptHandler_0xd, FlagGate_32BIT_TRAP, 3, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xe, InterruptHandler_0xe, FlagGate_32BIT_TRAP, 3, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xf, InterruptHandler_0xf, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x10, InterruptHandler_0x10, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x11, InterruptHandler_0x11, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x12, InterruptHandler_0x12, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x13, InterruptHandler_0x13, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x14, InterruptHandler_0x14, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x15, InterruptHandler_0x15, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x16, InterruptHandler_0x16, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x17, InterruptHandler_0x17, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x18, InterruptHandler_0x18, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x19, InterruptHandler_0x19, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x1a, InterruptHandler_0x1a, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x1b, InterruptHandler_0x1b, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x1c, InterruptHandler_0x1c, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x1d, InterruptHandler_0x1d, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x1e, InterruptHandler_0x1e, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x1f, InterruptHandler_0x1f, FlagGate_32BIT_TRAP, 1, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
|
||||
/* IRQ */
|
||||
|
||||
SetEntry(0x20, InterruptHandler_0x20, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x21, InterruptHandler_0x21, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x22, InterruptHandler_0x22, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x23, InterruptHandler_0x23, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x24, InterruptHandler_0x24, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x25, InterruptHandler_0x25, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x26, InterruptHandler_0x26, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x27, InterruptHandler_0x27, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x28, InterruptHandler_0x28, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x29, InterruptHandler_0x29, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x2a, InterruptHandler_0x2a, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x2b, InterruptHandler_0x2b, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x2c, InterruptHandler_0x2c, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x2d, InterruptHandler_0x2d, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x2e, InterruptHandler_0x2e, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x2f, InterruptHandler_0x2f, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
|
||||
/* Reserved by OS */
|
||||
|
||||
SetEntry(0x30, InterruptHandler_0x30, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x31, InterruptHandler_0x31, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x32, InterruptHandler_0x32, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x33, InterruptHandler_0x33, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x34, InterruptHandler_0x34, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x35, InterruptHandler_0x35, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x36, InterruptHandler_0x36, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x37, InterruptHandler_0x37, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x38, InterruptHandler_0x38, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x39, InterruptHandler_0x39, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x3a, InterruptHandler_0x3a, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x3b, InterruptHandler_0x3b, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x3c, InterruptHandler_0x3c, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x3d, InterruptHandler_0x3d, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
|
||||
/* Free */
|
||||
|
||||
SetEntry(0x3e, InterruptHandler_0x3e, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x3f, InterruptHandler_0x3f, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x40, InterruptHandler_0x40, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x41, InterruptHandler_0x41, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x42, InterruptHandler_0x42, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x43, InterruptHandler_0x43, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x44, InterruptHandler_0x44, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x45, InterruptHandler_0x45, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x46, InterruptHandler_0x46, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x47, InterruptHandler_0x47, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x48, InterruptHandler_0x48, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x49, InterruptHandler_0x49, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x4a, InterruptHandler_0x4a, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x4b, InterruptHandler_0x4b, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x4c, InterruptHandler_0x4c, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x4d, InterruptHandler_0x4d, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x4e, InterruptHandler_0x4e, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x4f, InterruptHandler_0x4f, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x50, InterruptHandler_0x50, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x51, InterruptHandler_0x51, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x52, InterruptHandler_0x52, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x53, InterruptHandler_0x53, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x54, InterruptHandler_0x54, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x55, InterruptHandler_0x55, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x56, InterruptHandler_0x56, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x57, InterruptHandler_0x57, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x58, InterruptHandler_0x58, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x59, InterruptHandler_0x59, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x5a, InterruptHandler_0x5a, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x5b, InterruptHandler_0x5b, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x5c, InterruptHandler_0x5c, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x5d, InterruptHandler_0x5d, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x5e, InterruptHandler_0x5e, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x5f, InterruptHandler_0x5f, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x60, InterruptHandler_0x60, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x61, InterruptHandler_0x61, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x62, InterruptHandler_0x62, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x63, InterruptHandler_0x63, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x64, InterruptHandler_0x64, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x65, InterruptHandler_0x65, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x66, InterruptHandler_0x66, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x67, InterruptHandler_0x67, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x68, InterruptHandler_0x68, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x69, InterruptHandler_0x69, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x6a, InterruptHandler_0x6a, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x6b, InterruptHandler_0x6b, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x6c, InterruptHandler_0x6c, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x6d, InterruptHandler_0x6d, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x6e, InterruptHandler_0x6e, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x6f, InterruptHandler_0x6f, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x70, InterruptHandler_0x70, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x71, InterruptHandler_0x71, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x72, InterruptHandler_0x72, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x73, InterruptHandler_0x73, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x74, InterruptHandler_0x74, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x75, InterruptHandler_0x75, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x76, InterruptHandler_0x76, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x77, InterruptHandler_0x77, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x78, InterruptHandler_0x78, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x79, InterruptHandler_0x79, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x7a, InterruptHandler_0x7a, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x7b, InterruptHandler_0x7b, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x7c, InterruptHandler_0x7c, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x7d, InterruptHandler_0x7d, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x7e, InterruptHandler_0x7e, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x7f, InterruptHandler_0x7f, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x80, InterruptHandler_0x80, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x81, InterruptHandler_0x81, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x82, InterruptHandler_0x82, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x83, InterruptHandler_0x83, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x84, InterruptHandler_0x84, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x85, InterruptHandler_0x85, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x86, InterruptHandler_0x86, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x87, InterruptHandler_0x87, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x88, InterruptHandler_0x88, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x89, InterruptHandler_0x89, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x8a, InterruptHandler_0x8a, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x8b, InterruptHandler_0x8b, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x8c, InterruptHandler_0x8c, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x8d, InterruptHandler_0x8d, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x8e, InterruptHandler_0x8e, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x8f, InterruptHandler_0x8f, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x90, InterruptHandler_0x90, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x91, InterruptHandler_0x91, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x92, InterruptHandler_0x92, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x93, InterruptHandler_0x93, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x94, InterruptHandler_0x94, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x95, InterruptHandler_0x95, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x96, InterruptHandler_0x96, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x97, InterruptHandler_0x97, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x98, InterruptHandler_0x98, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x99, InterruptHandler_0x99, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x9a, InterruptHandler_0x9a, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x9b, InterruptHandler_0x9b, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x9c, InterruptHandler_0x9c, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x9d, InterruptHandler_0x9d, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x9e, InterruptHandler_0x9e, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0x9f, InterruptHandler_0x9f, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xa0, InterruptHandler_0xa0, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xa1, InterruptHandler_0xa1, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xa2, InterruptHandler_0xa2, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xa3, InterruptHandler_0xa3, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xa4, InterruptHandler_0xa4, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xa5, InterruptHandler_0xa5, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xa6, InterruptHandler_0xa6, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xa7, InterruptHandler_0xa7, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xa8, InterruptHandler_0xa8, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xa9, InterruptHandler_0xa9, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xaa, InterruptHandler_0xaa, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xab, InterruptHandler_0xab, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xac, InterruptHandler_0xac, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xad, InterruptHandler_0xad, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xae, InterruptHandler_0xae, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xaf, InterruptHandler_0xaf, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xb0, InterruptHandler_0xb0, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xb1, InterruptHandler_0xb1, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xb2, InterruptHandler_0xb2, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xb3, InterruptHandler_0xb3, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xb4, InterruptHandler_0xb4, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xb5, InterruptHandler_0xb5, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xb6, InterruptHandler_0xb6, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xb7, InterruptHandler_0xb7, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xb8, InterruptHandler_0xb8, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xb9, InterruptHandler_0xb9, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xba, InterruptHandler_0xba, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xbb, InterruptHandler_0xbb, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xbc, InterruptHandler_0xbc, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xbd, InterruptHandler_0xbd, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xbe, InterruptHandler_0xbe, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xbf, InterruptHandler_0xbf, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xc0, InterruptHandler_0xc0, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xc1, InterruptHandler_0xc1, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xc2, InterruptHandler_0xc2, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xc3, InterruptHandler_0xc3, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xc4, InterruptHandler_0xc4, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xc5, InterruptHandler_0xc5, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xc6, InterruptHandler_0xc6, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xc7, InterruptHandler_0xc7, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xc8, InterruptHandler_0xc8, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xc9, InterruptHandler_0xc9, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xca, InterruptHandler_0xca, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xcb, InterruptHandler_0xcb, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xcc, InterruptHandler_0xcc, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xcd, InterruptHandler_0xcd, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xce, InterruptHandler_0xce, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xcf, InterruptHandler_0xcf, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xd0, InterruptHandler_0xd0, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xd1, InterruptHandler_0xd1, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xd2, InterruptHandler_0xd2, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xd3, InterruptHandler_0xd3, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xd4, InterruptHandler_0xd4, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xd5, InterruptHandler_0xd5, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xd6, InterruptHandler_0xd6, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xd7, InterruptHandler_0xd7, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xd8, InterruptHandler_0xd8, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xd9, InterruptHandler_0xd9, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xda, InterruptHandler_0xda, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xdb, InterruptHandler_0xdb, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xdc, InterruptHandler_0xdc, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xdd, InterruptHandler_0xdd, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xde, InterruptHandler_0xde, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xdf, InterruptHandler_0xdf, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xe0, InterruptHandler_0xe0, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xe1, InterruptHandler_0xe1, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xe2, InterruptHandler_0xe2, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xe3, InterruptHandler_0xe3, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xe4, InterruptHandler_0xe4, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xe5, InterruptHandler_0xe5, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xe6, InterruptHandler_0xe6, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xe7, InterruptHandler_0xe7, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xe8, InterruptHandler_0xe8, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xe9, InterruptHandler_0xe9, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xea, InterruptHandler_0xea, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xeb, InterruptHandler_0xeb, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xec, InterruptHandler_0xec, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xed, InterruptHandler_0xed, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xee, InterruptHandler_0xee, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xef, InterruptHandler_0xef, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xf0, InterruptHandler_0xf0, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xf1, InterruptHandler_0xf1, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xf2, InterruptHandler_0xf2, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xf3, InterruptHandler_0xf3, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xf4, InterruptHandler_0xf4, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xf5, InterruptHandler_0xf5, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xf6, InterruptHandler_0xf6, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xf7, InterruptHandler_0xf7, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xf8, InterruptHandler_0xf8, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xf9, InterruptHandler_0xf9, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xfa, InterruptHandler_0xfa, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xfb, InterruptHandler_0xfb, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xfc, InterruptHandler_0xfc, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xfd, InterruptHandler_0xfd, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xfe, InterruptHandler_0xfe, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
SetEntry(0xff, InterruptHandler_0xff, FlagGate_32BIT_TRAP, 0, FlagGate_RING0, GDT_KERNEL_CODE);
|
||||
CPU::x64::lidt(&idtd);
|
||||
}
|
||||
}
|
||||
@ -1,113 +0,0 @@
|
||||
[bits 16]
|
||||
TRAMPOLINE_BASE equ 0x2000
|
||||
|
||||
extern StartCPU
|
||||
global _trampoline_start
|
||||
_trampoline_start:
|
||||
cli
|
||||
mov ax, 0x0
|
||||
mov ds, ax
|
||||
mov es, ax
|
||||
mov fs, ax
|
||||
mov gs, ax
|
||||
mov ss, ax
|
||||
o32 lgdt [ProtectedMode_gdtr - _trampoline_start + TRAMPOLINE_BASE]
|
||||
mov eax, cr0
|
||||
or al, 0x1
|
||||
mov cr0, eax
|
||||
jmp 0x8:(Trampoline32 - _trampoline_start + TRAMPOLINE_BASE)
|
||||
|
||||
[bits 32]
|
||||
section .text
|
||||
Trampoline32:
|
||||
mov bx, 0x10
|
||||
mov ds, bx
|
||||
mov es, bx
|
||||
mov ss, bx
|
||||
mov eax, dword [0x500]
|
||||
mov cr3, eax
|
||||
mov eax, cr4
|
||||
or eax, 1 << 5 ; Set the PAE-bit, which is the 6th bit (bit 5).
|
||||
or eax, 1 << 7
|
||||
mov cr4, eax
|
||||
mov ecx, 0xc0000080
|
||||
rdmsr
|
||||
or eax,1 << 8 ; LME
|
||||
wrmsr
|
||||
mov eax, cr0
|
||||
or eax, 1 << 31
|
||||
mov cr0, eax
|
||||
lgdt [LongMode_gdtr - _trampoline_start + TRAMPOLINE_BASE]
|
||||
jmp 0x8:(Trampoline64 - _trampoline_start + TRAMPOLINE_BASE)
|
||||
|
||||
[bits 64]
|
||||
Trampoline64:
|
||||
mov ax, 0x10
|
||||
mov ds, ax
|
||||
mov es, ax
|
||||
mov ss, ax
|
||||
mov ax, 0x0
|
||||
mov fs, ax
|
||||
mov gs, ax
|
||||
lgdt [0x580]
|
||||
lidt [0x590]
|
||||
mov rsp, [0x570]
|
||||
mov rbp, 0x0 ; Terminate stack traces here.
|
||||
; Reset RFLAGS.
|
||||
push 0x0
|
||||
popf
|
||||
mov rax, qword vcode64
|
||||
call vcode64
|
||||
|
||||
vcode64:
|
||||
push rbp
|
||||
; Set up SSE
|
||||
mov rax, cr0
|
||||
; btr eax, 2
|
||||
; bts eax, 1
|
||||
; mov cr0, rax
|
||||
mov rax, cr4
|
||||
bts eax, 9
|
||||
bts eax, 10
|
||||
mov cr4, rax
|
||||
mov rax, qword TrampolineExit
|
||||
call rax
|
||||
|
||||
align 16
|
||||
LongMode_gdtr:
|
||||
dw LongModeGDTEnd - LongModeGDTStart - 1
|
||||
dq LongModeGDTStart - _trampoline_start + TRAMPOLINE_BASE
|
||||
|
||||
align 16
|
||||
LongModeGDTStart:
|
||||
dq 0 ; NULL segment
|
||||
dq 0x00AF98000000FFFF ; Code segment
|
||||
dq 0x00CF92000000FFFF ; Data segment
|
||||
LongModeGDTEnd:
|
||||
|
||||
align 16
|
||||
ProtectedMode_gdtr:
|
||||
dw ProtectedModeGDTEnd - ProtectedModeGDTStart - 1
|
||||
dd ProtectedModeGDTStart - _trampoline_start + TRAMPOLINE_BASE
|
||||
|
||||
align 16
|
||||
ProtectedModeGDTStart:
|
||||
dq 0 ; NULL segment
|
||||
dq 0x00CF9A000000FFFF ; Code segment
|
||||
dq 0x00CF92000000FFFF ; Data segment
|
||||
ProtectedModeGDTEnd:
|
||||
|
||||
align 16
|
||||
ProtectedMode_idtr:
|
||||
dw 0
|
||||
dd 0
|
||||
dd 0
|
||||
align 16
|
||||
|
||||
global _trampoline_end
|
||||
_trampoline_end:
|
||||
|
||||
TrampolineExit:
|
||||
call StartCPU
|
||||
|
||||
times 512 - ($-$$) db 0
|
||||
@ -1,129 +0,0 @@
|
||||
#include <smp.hpp>
|
||||
|
||||
#include <interrupts.hpp>
|
||||
#include <memory.hpp>
|
||||
#include <assert.h>
|
||||
#include <cpu.hpp>
|
||||
|
||||
#include "../../../kernel.h"
|
||||
#include "../acpi.hpp"
|
||||
#include "apic.hpp"
|
||||
|
||||
extern "C" uint64_t _trampoline_start, _trampoline_end;
|
||||
|
||||
enum SMPTrampolineAddress
|
||||
{
|
||||
PAGE_TABLE = 0x500,
|
||||
START_ADDR = 0x520,
|
||||
STACK = 0x570,
|
||||
GDT = 0x580,
|
||||
IDT = 0x590,
|
||||
CORE = 0x600,
|
||||
TRAMPOLINE_START = 0x2000
|
||||
};
|
||||
|
||||
volatile bool CPUEnabled = false;
|
||||
|
||||
#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
|
||||
static __attribute__((aligned(PAGE_SIZE))) CPUData CPUs[MAX_CPU] = {0};
|
||||
|
||||
CPUData *GetCPU(long id) { return &CPUs[id]; }
|
||||
CPUData *GetCurrentCPU()
|
||||
{
|
||||
CPUData *data = (CPUData *)CPU::x64::rdmsr(CPU::x64::MSR_GS_BASE);
|
||||
|
||||
if (data == nullptr && Interrupts::apic[0])
|
||||
data = &CPUs[((APIC::APIC *)Interrupts::apic[0])->Read(APIC::APIC_ID) >> 24];
|
||||
|
||||
if (data == nullptr)
|
||||
return nullptr; // The caller should handle this.
|
||||
|
||||
if (!data->IsActive)
|
||||
{
|
||||
error("CPU %d is not active!", data->ID);
|
||||
if ((&CPUs[0])->IsActive)
|
||||
return &CPUs[0];
|
||||
else
|
||||
return nullptr; // We are in trouble.
|
||||
}
|
||||
assert(data->Checksum == CPU_DATA_CHECKSUM); // This should never happen.
|
||||
return data;
|
||||
}
|
||||
|
||||
extern "C" void StartCPU()
|
||||
{
|
||||
CPU::Interrupts(CPU::Disable);
|
||||
CPU::InitializeFeatures();
|
||||
uint64_t CoreID = (int)*reinterpret_cast<int *>(CORE);
|
||||
// Initialize GDT and IDT
|
||||
Interrupts::Initialize(CoreID);
|
||||
Interrupts::Enable(CoreID);
|
||||
Interrupts::InitializeTimer(CoreID);
|
||||
|
||||
CPU::Interrupts(CPU::Enable);
|
||||
KPrint("\e058C19CPU \e8888FF%d \e058C19is online", CoreID);
|
||||
CPUEnabled = true;
|
||||
CPU::Halt(true);
|
||||
}
|
||||
|
||||
namespace SMP
|
||||
{
|
||||
int CPUCores = 0;
|
||||
|
||||
void Initialize(void *madt)
|
||||
{
|
||||
if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_VIRTUALBOX) == 0)
|
||||
{
|
||||
KPrint("VirtualBox detected, disabling SMP");
|
||||
return;
|
||||
}
|
||||
|
||||
int Cores = ((ACPI::MADT *)madt)->CPUCores + 1;
|
||||
|
||||
if (Config.Cores > ((ACPI::MADT *)madt)->CPUCores + 1)
|
||||
KPrint("More cores requested than available. Using %d cores", ((ACPI::MADT *)madt)->CPUCores + 1);
|
||||
else if (Config.Cores != 0)
|
||||
Cores = Config.Cores;
|
||||
|
||||
CPUCores = Cores;
|
||||
|
||||
for (int i = 0; i < Cores; i++)
|
||||
{
|
||||
debug("Initializing CPU %d", i);
|
||||
if ((((APIC::APIC *)Interrupts::apic[0])->Read(APIC::APIC_ID) >> 24) != ((ACPI::MADT *)madt)->lapic[i]->ACPIProcessorId)
|
||||
{
|
||||
((APIC::APIC *)Interrupts::apic[0])->Write(APIC::APIC_ICRHI, (((ACPI::MADT *)madt)->lapic[i]->APICId << 24));
|
||||
((APIC::APIC *)Interrupts::apic[0])->Write(APIC::APIC_ICRLO, 0x500);
|
||||
|
||||
Memory::Virtual().Map(0x0, 0x0, Memory::PTFlag::RW | Memory::PTFlag::US);
|
||||
|
||||
uint64_t TrampolineLength = (uintptr_t)&_trampoline_end - (uintptr_t)&_trampoline_start;
|
||||
for (uint64_t i = 0; i < (TrampolineLength / PAGE_SIZE) + 2; i++)
|
||||
Memory::Virtual().Map((void *)(TRAMPOLINE_START + (i * PAGE_SIZE)), (void *)(TRAMPOLINE_START + (i * PAGE_SIZE)), Memory::PTFlag::RW | Memory::PTFlag::US);
|
||||
|
||||
memcpy((void *)TRAMPOLINE_START, &_trampoline_start, TrampolineLength);
|
||||
|
||||
POKE(volatile uint64_t, PAGE_TABLE) = CPU::x64::readcr3().raw;
|
||||
POKE(volatile uint64_t, STACK) = (uint64_t)KernelAllocator.RequestPages(TO_PAGES(STACK_SIZE)) + STACK_SIZE;
|
||||
POKE(volatile uint64_t, CORE) = i;
|
||||
|
||||
asmv("sgdt [0x580]\n"
|
||||
"sidt [0x590]\n");
|
||||
|
||||
POKE(volatile uint64_t, START_ADDR) = (uintptr_t)&StartCPU;
|
||||
|
||||
((APIC::APIC *)Interrupts::apic[0])->SendInitIPI(((ACPI::MADT *)madt)->lapic[i]->APICId);
|
||||
((APIC::APIC *)Interrupts::apic[0])->SendStartupIPI(((ACPI::MADT *)madt)->lapic[i]->APICId, TRAMPOLINE_START);
|
||||
|
||||
while (!CPUEnabled)
|
||||
CPU::Pause();
|
||||
|
||||
trace("CPU %d loaded.", ((ACPI::MADT *)madt)->lapic[i]->APICId);
|
||||
KernelAllocator.FreePages((void *)*reinterpret_cast<long *>(STACK), TO_PAGES(STACK_SIZE));
|
||||
CPUEnabled = false;
|
||||
}
|
||||
else
|
||||
KPrint("\e058C19CPU \e8888FF%d \e058C19is the BSP", ((ACPI::MADT *)madt)->lapic[i]->APICId);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,337 +0,0 @@
|
||||
#ifndef __FENNIX_KERNEL_APIC_H__
|
||||
#define __FENNIX_KERNEL_APIC_H__
|
||||
|
||||
#include <types.h>
|
||||
|
||||
#include <interrupts.hpp>
|
||||
#include <cpu.hpp>
|
||||
|
||||
namespace APIC
|
||||
{
|
||||
enum APICRegisters
|
||||
{
|
||||
// source from: https://github.com/pdoane/osdev/blob/master/intr/local_apic.c
|
||||
APIC_ID = 0x20, // Local APIC ID
|
||||
APIC_VER = 0x30, // Local APIC Version
|
||||
APIC_TPR = 0x80, // Task Priority
|
||||
APIC_APR = 0x90, // Arbitration Priority
|
||||
APIC_PPR = 0xA0, // Processor Priority
|
||||
APIC_EOI = 0xB0, // EOI
|
||||
APIC_RRD = 0xC0, // Remote Read
|
||||
APIC_LDR = 0xD0, // Logical Destination
|
||||
APIC_DFR = 0xE0, // Destination Format
|
||||
APIC_SVR = 0xF0, // Spurious Interrupt Vector
|
||||
APIC_ISR = 0x100, // In-Service (8 registers)
|
||||
APIC_TMR = 0x180, // Trigger Mode (8 registers)
|
||||
APIC_IRR = 0x200, // Interrupt Request (8 registers)
|
||||
APIC_ESR = 0x280, // Error Status
|
||||
APIC_ICRLO = 0x300, // Interrupt Command
|
||||
APIC_ICRHI = 0x310, // Interrupt Command [63:32]
|
||||
APIC_TIMER = 0x320, // LVT Timer
|
||||
APIC_THERMAL = 0x330, // LVT Thermal Sensor
|
||||
APIC_PERF = 0x340, // LVT Performance Counter
|
||||
APIC_LINT0 = 0x350, // LVT LINT0
|
||||
APIC_LINT1 = 0x360, // LVT LINT1
|
||||
APIC_ERROR = 0x370, // LVT Error
|
||||
APIC_TICR = 0x380, // Initial Count (for Timer)
|
||||
APIC_TCCR = 0x390, // Current Count (for Timer)
|
||||
APIC_TDCR = 0x3E0, // Divide Configuration (for Timer)
|
||||
};
|
||||
|
||||
enum IOAPICRegisters
|
||||
{
|
||||
GetIOAPICVersion = 0x1
|
||||
};
|
||||
|
||||
enum IOAPICFlags
|
||||
{
|
||||
ActiveHighLow = 2,
|
||||
EdgeLevel = 8
|
||||
};
|
||||
|
||||
enum APICDeliveryMode
|
||||
{
|
||||
Fixed = 0b000,
|
||||
LowestPriority = 0b001, /* Reserved */
|
||||
SMI = 0b010,
|
||||
APIC_DELIVERY_MODE_RESERVED0 = 0b011, /* Reserved */
|
||||
NMI = 0b100,
|
||||
INIT = 0b101,
|
||||
Startup = 0b110,
|
||||
ExtINT = 0b111 /* Reserved */
|
||||
};
|
||||
|
||||
enum APICDestinationMode
|
||||
{
|
||||
Physical = 0b0,
|
||||
Logical = 0b1
|
||||
};
|
||||
|
||||
enum APICDeliveryStatus
|
||||
{
|
||||
Idle = 0b0,
|
||||
SendPending = 0b1
|
||||
};
|
||||
|
||||
enum APICLevel
|
||||
{
|
||||
DeAssert = 0b0,
|
||||
Assert = 0b1
|
||||
};
|
||||
|
||||
enum APICTriggerMode
|
||||
{
|
||||
Edge = 0b0,
|
||||
Level = 0b1
|
||||
};
|
||||
|
||||
enum APICDestinationShorthand
|
||||
{
|
||||
NoShorthand = 0b00,
|
||||
Self = 0b01,
|
||||
AllIncludingSelf = 0b10,
|
||||
AllExcludingSelf = 0b11
|
||||
};
|
||||
|
||||
enum LVTTimerDivide
|
||||
{
|
||||
DivideBy2 = 0b000,
|
||||
DivideBy4 = 0b001,
|
||||
DivideBy8 = 0b010,
|
||||
DivideBy16 = 0b011,
|
||||
DivideBy32 = 0b100,
|
||||
DivideBy64 = 0b101,
|
||||
DivideBy128 = 0b110,
|
||||
DivideBy1 = 0b111
|
||||
};
|
||||
|
||||
enum LVTTimerMask
|
||||
{
|
||||
Unmasked = 0b0,
|
||||
Masked = 0b1
|
||||
};
|
||||
|
||||
enum LVTTimerMode
|
||||
{
|
||||
OneShot = 0b00,
|
||||
Periodic = 0b01,
|
||||
TSCDeadline = 0b10
|
||||
};
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Interrupt Vector */
|
||||
uint64_t Vector : 8;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved0 : 4;
|
||||
/**
|
||||
* @brief Delivery Status
|
||||
*
|
||||
* 0: Idle
|
||||
* 1: Send Pending
|
||||
*/
|
||||
uint64_t DeliveryStatus : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved1 : 3;
|
||||
/**
|
||||
* @brief Mask
|
||||
*
|
||||
* 0: Not masked
|
||||
* 1: Masked
|
||||
*/
|
||||
uint64_t Mask : 1;
|
||||
/** @brief Timer Mode
|
||||
*
|
||||
* 0: One-shot
|
||||
* 1: Periodic
|
||||
* 2: TSC-Deadline
|
||||
*/
|
||||
uint64_t TimerMode : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved2 : 14;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __attribute__((packed)) LVTTimer;
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Spurious Vector */
|
||||
uint64_t Vector : 8;
|
||||
/** @brief Enable or disable APIC software */
|
||||
uint64_t Software : 1;
|
||||
/** @brief Focus Processor Checking */
|
||||
uint64_t FocusProcessorChecking : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved : 2;
|
||||
/** @brief Disable EOI Broadcast */
|
||||
uint64_t DisableEOIBroadcast : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved1 : 19;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __attribute__((packed)) Spurious;
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Interrupt Vector */
|
||||
uint64_t Vector : 8;
|
||||
/** @brief Delivery Mode */
|
||||
uint64_t DeliveryMode : 3;
|
||||
/** @brief Destination Mode
|
||||
*
|
||||
* 0: Physical
|
||||
* 1: Logical
|
||||
*/
|
||||
uint64_t DestinationMode : 1;
|
||||
/** @brief Delivery Status
|
||||
*
|
||||
* @note Reserved when in x2APIC mode
|
||||
*/
|
||||
uint64_t DeliveryStatus : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved0 : 1;
|
||||
/** @brief Level
|
||||
*
|
||||
* 0: Deassert
|
||||
* 1: Assert
|
||||
*/
|
||||
uint64_t Level : 1;
|
||||
/** @brief Trigger Mode
|
||||
*
|
||||
* 0: Edge
|
||||
* 1: Level
|
||||
*/
|
||||
uint64_t TriggerMode : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved1 : 2;
|
||||
/** @brief Destination Shorthand
|
||||
*
|
||||
* 0: No shorthand
|
||||
* 1: Self
|
||||
* 2: All including self
|
||||
* 3: All excluding self
|
||||
*/
|
||||
uint64_t DestinationShorthand : 2;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved2 : 12;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __attribute__((packed)) InterruptCommandRegisterLow;
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved0 : 24;
|
||||
/** @brief Destination */
|
||||
uint64_t Destination : 8;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __attribute__((packed)) InterruptCommandRegisterHigh;
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Interrupt Vector */
|
||||
uint64_t Vector : 8;
|
||||
/** @brief Delivery Mode */
|
||||
uint64_t DeliveryMode : 3;
|
||||
/** @brief Destination Mode
|
||||
*
|
||||
* 0: Physical
|
||||
* 1: Logical
|
||||
*/
|
||||
uint64_t DestinationMode : 1;
|
||||
/** @brief Delivery Status */
|
||||
uint64_t DeliveryStatus : 1;
|
||||
/** @brief Interrupt Input Pin Polarity
|
||||
*
|
||||
* 0: Active High
|
||||
* 1: Active Low
|
||||
*/
|
||||
uint64_t Polarity : 1;
|
||||
/** @brief Remote IRR */
|
||||
uint64_t RemoteIRR : 1;
|
||||
/** @brief Trigger Mode
|
||||
*
|
||||
* 0: Edge
|
||||
* 1: Level
|
||||
*/
|
||||
uint64_t TriggerMode : 1;
|
||||
/** @brief Mask */
|
||||
uint64_t Mask : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved0 : 15;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved1 : 24;
|
||||
/** @brief Destination */
|
||||
uint64_t DestinationID : 8;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint64_t Low;
|
||||
uint64_t High;
|
||||
} split;
|
||||
uint64_t raw;
|
||||
} __attribute__((packed)) IOAPICRedirectEntry;
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint64_t Version : 8;
|
||||
uint64_t Reserved : 8;
|
||||
uint64_t MaximumRedirectionEntry : 8;
|
||||
uint64_t Reserved2 : 8;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __attribute__((packed)) IOAPICVersion;
|
||||
|
||||
class APIC
|
||||
{
|
||||
private:
|
||||
bool x2APICSupported = false;
|
||||
uint64_t APICBaseAddress = 0;
|
||||
|
||||
public:
|
||||
uint32_t Read(uint32_t Register);
|
||||
void Write(uint32_t Register, uint32_t Value);
|
||||
void IOWrite(uint64_t Base, uint32_t Register, uint32_t Value);
|
||||
uint32_t IORead(uint64_t Base, uint32_t Register);
|
||||
void EOI();
|
||||
void RedirectIRQs(int CPU = 0);
|
||||
void WaitForIPI();
|
||||
void IPI(uint8_t CPU, InterruptCommandRegisterLow icr);
|
||||
void SendInitIPI(uint8_t CPU);
|
||||
void SendStartupIPI(uint8_t CPU, uint64_t StartupAddress);
|
||||
uint32_t IOGetMaxRedirect(uint32_t APICID);
|
||||
void RawRedirectIRQ(uint8_t Vector, uint32_t GSI, uint16_t Flags, int CPU, int Status);
|
||||
void RedirectIRQ(int CPU, uint8_t IRQ, int Status);
|
||||
APIC(int Core);
|
||||
~APIC();
|
||||
};
|
||||
|
||||
class Timer : public Interrupts::Handler
|
||||
{
|
||||
private:
|
||||
APIC *lapic;
|
||||
uint64_t Ticks = 0;
|
||||
void OnInterruptReceived(CPU::x64::TrapFrame *Frame);
|
||||
|
||||
public:
|
||||
uint64_t GetTicks() { return Ticks; }
|
||||
void OneShot(uint32_t Vector, uint64_t Miliseconds);
|
||||
Timer(APIC *apic);
|
||||
~Timer();
|
||||
};
|
||||
}
|
||||
|
||||
#endif // !__FENNIX_KERNEL_APIC_H__
|
||||
@ -1,11 +0,0 @@
|
||||
[bits 64]
|
||||
|
||||
[global _amd64_fxsave]
|
||||
_amd64_fxsave:
|
||||
fxsave [rdi]
|
||||
ret
|
||||
|
||||
[global _amd64_fxrstor]
|
||||
_amd64_fxrstor:
|
||||
fxrstor [rdi]
|
||||
ret
|
||||
@ -1,144 +0,0 @@
|
||||
#ifndef __FENNIX_KERNEL_GDT_H__
|
||||
#define __FENNIX_KERNEL_GDT_H__
|
||||
|
||||
#include <types.h>
|
||||
|
||||
namespace GlobalDescriptorTable
|
||||
{
|
||||
/** @brief The GDT Access Table
|
||||
* @details For more information, see https://wiki.osdev.org/Global_Descriptor_Table
|
||||
*/
|
||||
union GlobalDescriptorTableAccess
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Access bit.
|
||||
* @note The CPU sets this bit to 1 when the segment is accessed.
|
||||
*/
|
||||
uint8_t A : 1;
|
||||
|
||||
/** @brief Readable bit for code segments, writable bit for data segments.
|
||||
* @details For code segments, this bit must be 1 for the segment to be readable.
|
||||
* @details For data segments, this bit must be 1 for the segment to be writable.
|
||||
*/
|
||||
uint8_t RW : 1;
|
||||
|
||||
/** @brief Direction bit for data segments, conforming bit for code segments.
|
||||
* @details For data segments, this bit must be 1 for the segment to grow up (higher addresses).
|
||||
* @details For code segments, this bit must be 1 for code in the segment to be able to be executed from an equal or lower privilege level.
|
||||
*/
|
||||
uint8_t DC : 1;
|
||||
|
||||
/** @brief Executable bit.
|
||||
* @details This bit must be 1 for code-segment descriptors.
|
||||
* @details This bit must be 0 for data-segment and system descriptors.
|
||||
*/
|
||||
uint8_t E : 1;
|
||||
|
||||
/** @brief Descriptor type.
|
||||
* @details This bit must be 0 for system descriptors.
|
||||
* @details This bit must be 1 for code or data segment descriptor.
|
||||
*/
|
||||
uint8_t S : 1;
|
||||
|
||||
/** @brief Descriptor privilege level.
|
||||
* @details This field determines the privilege level of the segment.
|
||||
* @details 0 = kernel mode, 3 = user mode.
|
||||
*/
|
||||
uint8_t DPL : 2;
|
||||
|
||||
/** @brief Present bit.
|
||||
* @details This bit must be 1 for all valid descriptors.
|
||||
*/
|
||||
uint8_t P : 1;
|
||||
} __attribute__((packed));
|
||||
uint8_t Raw;
|
||||
};
|
||||
|
||||
union GlobalDescriptorTableFlags
|
||||
{
|
||||
// TODO: Add more flags.
|
||||
struct
|
||||
{
|
||||
/** @brief Unknown. */
|
||||
uint8_t Unknown : 5;
|
||||
|
||||
/** @brief Long mode.
|
||||
* @details If the long mode bit is clear, the segment is in 32-bit protected mode.
|
||||
* @details If the long mode bit is set, the segment is in 64-bit long mode.
|
||||
*/
|
||||
uint8_t L : 1;
|
||||
} __attribute__((packed));
|
||||
uint8_t Raw;
|
||||
};
|
||||
|
||||
typedef struct _TaskStateSegmentEntry
|
||||
{
|
||||
/* LOW */
|
||||
uint16_t Length;
|
||||
uint16_t BaseLow;
|
||||
uint8_t BaseMiddle;
|
||||
GlobalDescriptorTableAccess Flags;
|
||||
uint8_t Granularity;
|
||||
uint8_t BaseHigh;
|
||||
/* HIGH */
|
||||
uint32_t BaseUpper;
|
||||
uint32_t Reserved;
|
||||
} __attribute__((packed)) TaskStateSegmentEntry;
|
||||
|
||||
typedef struct _TaskStateSegment
|
||||
{
|
||||
uint32_t Reserved0 __attribute__((aligned(16)));
|
||||
uint64_t StackPointer[3];
|
||||
uint64_t Reserved1;
|
||||
uint64_t InterruptStackTable[7];
|
||||
uint16_t Reserved2;
|
||||
uint16_t IOMapBaseAddressOffset;
|
||||
} __attribute__((packed)) TaskStateSegment;
|
||||
|
||||
typedef struct _GlobalDescriptorTableEntry
|
||||
{
|
||||
/** @brief Length */
|
||||
uint16_t Length;
|
||||
/** @brief Low Base */
|
||||
uint16_t BaseLow;
|
||||
/** @brief Middle Base */
|
||||
uint8_t BaseMiddle;
|
||||
/** @brief Access */
|
||||
GlobalDescriptorTableAccess Access;
|
||||
/** @brief Flags */
|
||||
GlobalDescriptorTableFlags Flags;
|
||||
/** @brief High Base */
|
||||
uint8_t BaseHigh;
|
||||
} __attribute__((packed)) GlobalDescriptorTableEntry;
|
||||
|
||||
typedef struct _GlobalDescriptorTableEntries
|
||||
{
|
||||
GlobalDescriptorTableEntry Null;
|
||||
GlobalDescriptorTableEntry Code;
|
||||
GlobalDescriptorTableEntry Data;
|
||||
GlobalDescriptorTableEntry UserData;
|
||||
GlobalDescriptorTableEntry UserCode;
|
||||
TaskStateSegmentEntry TaskStateSegment;
|
||||
} __attribute__((packed)) GlobalDescriptorTableEntries;
|
||||
|
||||
typedef struct _GlobalDescriptorTableDescriptor
|
||||
{
|
||||
/** @brief GDT entries length */
|
||||
uint16_t Length;
|
||||
/** @brief GDT entries address */
|
||||
GlobalDescriptorTableEntries *Entries;
|
||||
} __attribute__((packed)) GlobalDescriptorTableDescriptor;
|
||||
|
||||
extern void *CPUStackPointer[];
|
||||
void Init(int Core);
|
||||
void SetKernelStack(void *Stack);
|
||||
}
|
||||
|
||||
#define GDT_KERNEL_CODE offsetof(GlobalDescriptorTable::GlobalDescriptorTableEntries, Code)
|
||||
#define GDT_KERNEL_DATA offsetof(GlobalDescriptorTable::GlobalDescriptorTableEntries, Data)
|
||||
#define GDT_USER_CODE (offsetof(GlobalDescriptorTable::GlobalDescriptorTableEntries, UserCode) | 3)
|
||||
#define GDT_USER_DATA (offsetof(GlobalDescriptorTable::GlobalDescriptorTableEntries, UserData) | 3)
|
||||
#define GDT_TSS (offsetof(GlobalDescriptorTable::GlobalDescriptorTableEntries, TaskStateSegment) | 3)
|
||||
|
||||
#endif // !__FENNIX_KERNEL_GDT_H__
|
||||
@ -1,46 +0,0 @@
|
||||
#ifndef __FENNIX_KERNEL_IDT_H__
|
||||
#define __FENNIX_KERNEL_IDT_H__
|
||||
|
||||
#include <types.h>
|
||||
|
||||
namespace InterruptDescriptorTable
|
||||
{
|
||||
typedef enum _InterruptDescriptorTableFlags
|
||||
{
|
||||
FlagGate_TASK = 0b101,
|
||||
FlagGate_16BIT_INT = 0b110,
|
||||
FlagGate_16BIT_TRAP = 0b111,
|
||||
FlagGate_32BIT_INT = 0b1110,
|
||||
FlagGate_32BIT_TRAP = 0b1111,
|
||||
FlagGate_RING0 = 0b0,
|
||||
FlagGate_RING1 = 0b1,
|
||||
FlagGate_RING2 = 0b10,
|
||||
FlagGate_RING3 = 0b11,
|
||||
FlagGate_PRESENT = 0b1, // Not sure if this is correct.
|
||||
} InterruptDescriptorTableFlags;
|
||||
|
||||
typedef struct _InterruptDescriptorTableEntry
|
||||
{
|
||||
uint64_t BaseLow : 16;
|
||||
uint64_t SegmentSelector : 16;
|
||||
uint64_t InterruptStackTable : 3;
|
||||
uint64_t Reserved1 : 5;
|
||||
InterruptDescriptorTableFlags Flags : 4;
|
||||
uint64_t Reserved2 : 1;
|
||||
uint64_t Ring : 2;
|
||||
uint64_t Present : 1;
|
||||
uint64_t BaseHigh : 48;
|
||||
uint64_t Reserved3 : 32;
|
||||
} __attribute__((packed)) InterruptDescriptorTableEntry;
|
||||
|
||||
typedef struct _InterruptDescriptorTableDescriptor
|
||||
{
|
||||
uint16_t Length;
|
||||
InterruptDescriptorTableEntry *Entries;
|
||||
} __attribute__((packed)) InterruptDescriptorTableDescriptor;
|
||||
|
||||
void SetEntry(uint8_t Index, void (*Base)(), InterruptDescriptorTableFlags Attribute, uint8_t InterruptStackTable, InterruptDescriptorTableFlags Ring, uint16_t SegmentSelector);
|
||||
void Init(int Core);
|
||||
}
|
||||
|
||||
#endif // !__FENNIX_KERNEL_IDT_H__
|
||||
@ -1,63 +0,0 @@
|
||||
OUTPUT_FORMAT(elf64-x86-64)
|
||||
OUTPUT_ARCH(i386:x86-64)
|
||||
|
||||
ENTRY(_start)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = 0xffffffff80000000;
|
||||
|
||||
_kernel_start = .;
|
||||
.text :
|
||||
{
|
||||
*(.text .text.*)
|
||||
}
|
||||
_kernel_text_end = ALIGN(CONSTANT(MAXPAGESIZE));
|
||||
. += CONSTANT(MAXPAGESIZE);
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data .data.*)
|
||||
}
|
||||
_kernel_data_end = ALIGN(CONSTANT(MAXPAGESIZE));
|
||||
. += CONSTANT(MAXPAGESIZE);
|
||||
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata .rodata.*)
|
||||
}
|
||||
_kernel_rodata_end = ALIGN(CONSTANT(MAXPAGESIZE));
|
||||
. += CONSTANT(MAXPAGESIZE);
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN(__init_array_start = .);
|
||||
KEEP(*(.init_array .ctors))
|
||||
KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
}
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN(__fini_array_start = .);
|
||||
KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP(*(.fini_array .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
}
|
||||
. += CONSTANT(MAXPAGESIZE);
|
||||
|
||||
|
||||
.bss :
|
||||
{
|
||||
*(COMMON)
|
||||
*(.bss .bss.*)
|
||||
}
|
||||
. += CONSTANT(MAXPAGESIZE);
|
||||
_kernel_end = ALIGN(CONSTANT(MAXPAGESIZE));
|
||||
|
||||
/DISCARD/ :
|
||||
{
|
||||
*(.comment*)
|
||||
*(.note*)
|
||||
}
|
||||
}
|
||||
@ -1,15 +0,0 @@
|
||||
// #include <types.h>
|
||||
|
||||
// #include <debug.h>
|
||||
|
||||
// int Entry(void *Info);
|
||||
|
||||
// void _start(void *Raw)
|
||||
// {
|
||||
// error("Todo");
|
||||
// while (1)
|
||||
// asmv("hlt");
|
||||
// Entry(NULL);
|
||||
// return;
|
||||
// }
|
||||
// C stuff
|
||||
@ -1,15 +0,0 @@
|
||||
#include <types.h>
|
||||
|
||||
#include <debug.h>
|
||||
|
||||
int Entry(void *Info);
|
||||
|
||||
void _start(void *Raw)
|
||||
{
|
||||
error("ERROR! INVALID BOOT PROTOCOL!");
|
||||
while (1)
|
||||
asmv("hlt");
|
||||
Entry(NULL);
|
||||
return;
|
||||
}
|
||||
// C stuff
|
||||
@ -1 +0,0 @@
|
||||
// C++ constructor/destructor stuff
|
||||
@ -1 +0,0 @@
|
||||
// C++ constructor/destructor stuff
|
||||
@ -1,13 +0,0 @@
|
||||
.section .init
|
||||
.global _init
|
||||
.type _init, @function
|
||||
_init:
|
||||
push %rbp
|
||||
movq %rsp, %rbp
|
||||
|
||||
.section .fini
|
||||
.global _fini
|
||||
.type _fini, @function
|
||||
_fini:
|
||||
push %rbp
|
||||
movq %rsp, %rbp
|
||||
@ -1,7 +0,0 @@
|
||||
.section .init
|
||||
popq %rbp
|
||||
ret
|
||||
|
||||
.section .fini
|
||||
popq %rbp
|
||||
ret
|
||||
@ -1,21 +0,0 @@
|
||||
{
|
||||
"llvm-target": "x86_64-unknown-none",
|
||||
"data-layout": "e-m:e-i64:64-f80:128-n8:16:32:64-S128",
|
||||
"cpu": "x86-64",
|
||||
"arch": "x86_64",
|
||||
"features": "-mmx,-sse,+soft-float",
|
||||
"target-endian": "little",
|
||||
"target-pointer-width": "64",
|
||||
"target-c-int-width": "32",
|
||||
"os": "none",
|
||||
"linker-flavor": "ld",
|
||||
"pre-link-args": {
|
||||
"ld": [
|
||||
"-m64"
|
||||
]
|
||||
},
|
||||
"no-compiler-rt": true,
|
||||
"disable-redzone": true,
|
||||
"eliminate-frame-pointer": false,
|
||||
"morestack": false
|
||||
}
|
||||
@ -1,285 +0,0 @@
|
||||
/* Source: https://github.com/glitchub/arith64 */
|
||||
#define arith64_u64 unsigned long long int
|
||||
#define arith64_s64 signed long long int
|
||||
#define arith64_u32 unsigned int
|
||||
#define arith64_s32 int
|
||||
|
||||
typedef union
|
||||
{
|
||||
arith64_u64 u64;
|
||||
arith64_s64 s64;
|
||||
struct
|
||||
{
|
||||
#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
|
||||
arith64_u32 hi;
|
||||
arith64_u32 lo;
|
||||
#else
|
||||
arith64_u32 lo;
|
||||
arith64_u32 hi;
|
||||
#endif
|
||||
} u32;
|
||||
struct
|
||||
{
|
||||
#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
|
||||
arith64_s32 hi;
|
||||
arith64_s32 lo;
|
||||
#else
|
||||
arith64_s32 lo;
|
||||
arith64_s32 hi;
|
||||
#endif
|
||||
} s32;
|
||||
} arith64_word;
|
||||
|
||||
#define arith64_hi(n) (arith64_word){.u64 = n}.u32.hi
|
||||
#define arith64_lo(n) (arith64_word){.u64 = n}.u32.lo
|
||||
#define arith64_neg(a, b) (((a) ^ ((((arith64_s64)(b)) >= 0) - 1)) + (((arith64_s64)(b)) < 0))
|
||||
#define arith64_abs(a) arith64_neg(a, a)
|
||||
|
||||
arith64_s64 __absvdi2(arith64_s64 a)
|
||||
{
|
||||
return arith64_abs(a);
|
||||
}
|
||||
|
||||
arith64_s64 __ashldi3(arith64_s64 a, int b)
|
||||
{
|
||||
arith64_word w = {.s64 = a};
|
||||
|
||||
b &= 63;
|
||||
|
||||
if (b >= 32)
|
||||
{
|
||||
w.u32.hi = w.u32.lo << (b - 32);
|
||||
w.u32.lo = 0;
|
||||
}
|
||||
else if (b)
|
||||
{
|
||||
w.u32.hi = (w.u32.lo >> (32 - b)) | (w.u32.hi << b);
|
||||
w.u32.lo <<= b;
|
||||
}
|
||||
return w.s64;
|
||||
}
|
||||
|
||||
arith64_s64 __ashrdi3(arith64_s64 a, int b)
|
||||
{
|
||||
arith64_word w = {.s64 = a};
|
||||
|
||||
b &= 63;
|
||||
|
||||
if (b >= 32)
|
||||
{
|
||||
w.s32.lo = w.s32.hi >> (b - 32);
|
||||
w.s32.hi >>= 31; // 0xFFFFFFFF or 0
|
||||
}
|
||||
else if (b)
|
||||
{
|
||||
w.u32.lo = (w.u32.hi << (32 - b)) | (w.u32.lo >> b);
|
||||
w.s32.hi >>= b;
|
||||
}
|
||||
return w.s64;
|
||||
}
|
||||
|
||||
int __clzsi2(arith64_u32 a)
|
||||
{
|
||||
int b, n = 0;
|
||||
b = !(a & 0xffff0000) << 4;
|
||||
n += b;
|
||||
a <<= b;
|
||||
b = !(a & 0xff000000) << 3;
|
||||
n += b;
|
||||
a <<= b;
|
||||
b = !(a & 0xf0000000) << 2;
|
||||
n += b;
|
||||
a <<= b;
|
||||
b = !(a & 0xc0000000) << 1;
|
||||
n += b;
|
||||
a <<= b;
|
||||
return n + !(a & 0x80000000);
|
||||
}
|
||||
|
||||
int __clzdi2(arith64_u64 a)
|
||||
{
|
||||
int b, n = 0;
|
||||
b = !(a & 0xffffffff00000000ULL) << 5;
|
||||
n += b;
|
||||
a <<= b;
|
||||
b = !(a & 0xffff000000000000ULL) << 4;
|
||||
n += b;
|
||||
a <<= b;
|
||||
b = !(a & 0xff00000000000000ULL) << 3;
|
||||
n += b;
|
||||
a <<= b;
|
||||
b = !(a & 0xf000000000000000ULL) << 2;
|
||||
n += b;
|
||||
a <<= b;
|
||||
b = !(a & 0xc000000000000000ULL) << 1;
|
||||
n += b;
|
||||
a <<= b;
|
||||
return n + !(a & 0x8000000000000000ULL);
|
||||
}
|
||||
|
||||
int __ctzsi2(arith64_u32 a)
|
||||
{
|
||||
int b, n = 0;
|
||||
b = !(a & 0x0000ffff) << 4;
|
||||
n += b;
|
||||
a >>= b;
|
||||
b = !(a & 0x000000ff) << 3;
|
||||
n += b;
|
||||
a >>= b;
|
||||
b = !(a & 0x0000000f) << 2;
|
||||
n += b;
|
||||
a >>= b;
|
||||
b = !(a & 0x00000003) << 1;
|
||||
n += b;
|
||||
a >>= b;
|
||||
return n + !(a & 0x00000001);
|
||||
}
|
||||
|
||||
int __ctzdi2(arith64_u64 a)
|
||||
{
|
||||
int b, n = 0;
|
||||
b = !(a & 0x00000000ffffffffULL) << 5;
|
||||
n += b;
|
||||
a >>= b;
|
||||
b = !(a & 0x000000000000ffffULL) << 4;
|
||||
n += b;
|
||||
a >>= b;
|
||||
b = !(a & 0x00000000000000ffULL) << 3;
|
||||
n += b;
|
||||
a >>= b;
|
||||
b = !(a & 0x000000000000000fULL) << 2;
|
||||
n += b;
|
||||
a >>= b;
|
||||
b = !(a & 0x0000000000000003ULL) << 1;
|
||||
n += b;
|
||||
a >>= b;
|
||||
return n + !(a & 0x0000000000000001ULL);
|
||||
}
|
||||
|
||||
arith64_u64 __divmoddi4(arith64_u64 a, arith64_u64 b, arith64_u64 *c)
|
||||
{
|
||||
if (b > a) //
|
||||
{
|
||||
if (c)
|
||||
*c = a;
|
||||
return 0;
|
||||
}
|
||||
if (!arith64_hi(b))
|
||||
{
|
||||
if (b == 0)
|
||||
{
|
||||
volatile char x = 0;
|
||||
x = 1 / x;
|
||||
}
|
||||
if (b == 1)
|
||||
{
|
||||
if (c)
|
||||
*c = 0;
|
||||
return a;
|
||||
}
|
||||
if (!arith64_hi(a))
|
||||
{
|
||||
if (c)
|
||||
*c = arith64_lo(a) % arith64_lo(b);
|
||||
return arith64_lo(a) / arith64_lo(b);
|
||||
}
|
||||
}
|
||||
|
||||
char bits = __clzdi2(b) - __clzdi2(a) + 1;
|
||||
arith64_u64 rem = a >> bits;
|
||||
a <<= 64 - bits;
|
||||
arith64_u64 wrap = 0;
|
||||
while (bits-- > 0)
|
||||
{
|
||||
rem = (rem << 1) | (a >> 63);
|
||||
a = (a << 1) | (wrap & 1);
|
||||
wrap = ((arith64_s64)(b - rem - 1) >> 63);
|
||||
rem -= b & wrap;
|
||||
}
|
||||
if (c)
|
||||
*c = rem;
|
||||
return (a << 1) | (wrap & 1);
|
||||
}
|
||||
|
||||
arith64_s64 __divdi3(arith64_s64 a, arith64_s64 b)
|
||||
{
|
||||
arith64_u64 q = __divmoddi4(arith64_abs(a), arith64_abs(b), (void *)0);
|
||||
return arith64_neg(q, a ^ b);
|
||||
}
|
||||
|
||||
int __ffsdi2(arith64_u64 a) { return a ? __ctzdi2(a) + 1 : 0; }
|
||||
|
||||
arith64_u64 __lshrdi3(arith64_u64 a, int b)
|
||||
{
|
||||
arith64_word w = {.u64 = a};
|
||||
|
||||
b &= 63;
|
||||
|
||||
if (b >= 32)
|
||||
{
|
||||
w.u32.lo = w.u32.hi >> (b - 32);
|
||||
w.u32.hi = 0;
|
||||
}
|
||||
else if (b)
|
||||
{
|
||||
w.u32.lo = (w.u32.hi << (32 - b)) | (w.u32.lo >> b);
|
||||
w.u32.hi >>= b;
|
||||
}
|
||||
return w.u64;
|
||||
}
|
||||
|
||||
arith64_s64 __moddi3(arith64_s64 a, arith64_s64 b)
|
||||
{
|
||||
arith64_u64 r;
|
||||
__divmoddi4(arith64_abs(a), arith64_abs(b), &r);
|
||||
return arith64_neg(r, a);
|
||||
}
|
||||
|
||||
int __popcountsi2(arith64_u32 a)
|
||||
{
|
||||
|
||||
a = a - ((a >> 1) & 0x55555555);
|
||||
a = ((a >> 2) & 0x33333333) + (a & 0x33333333);
|
||||
a = (a + (a >> 4)) & 0x0F0F0F0F;
|
||||
a = (a + (a >> 16));
|
||||
|
||||
return (a + (a >> 8)) & 63;
|
||||
}
|
||||
|
||||
int __popcountdi2(arith64_u64 a)
|
||||
{
|
||||
|
||||
a = a - ((a >> 1) & 0x5555555555555555ULL);
|
||||
a = ((a >> 2) & 0x3333333333333333ULL) + (a & 0x3333333333333333ULL);
|
||||
a = (a + (a >> 4)) & 0x0F0F0F0F0F0F0F0FULL;
|
||||
a = (a + (a >> 32));
|
||||
a = (a + (a >> 16));
|
||||
|
||||
return (a + (a >> 8)) & 127;
|
||||
}
|
||||
|
||||
arith64_u64 __udivdi3(arith64_u64 a, arith64_u64 b) { return __divmoddi4(a, b, (void *)0); }
|
||||
|
||||
arith64_u64 __umoddi3(arith64_u64 a, arith64_u64 b)
|
||||
{
|
||||
arith64_u64 r;
|
||||
__divmoddi4(a, b, &r);
|
||||
return r;
|
||||
}
|
||||
|
||||
/* Good documentation: https://splichal.eu/scripts/sphinx/gccint/_build/html/the-gcc-low-level-runtime-library/routines-for-floating-point-emulation.html */
|
||||
|
||||
double __adddf3(double a, double b) { return a + b; }
|
||||
double __muldf3(double a, double b) { return a * b; }
|
||||
double __floatsidf(int i) { return (double)i; }
|
||||
int __ltdf2(double a, double b) { return a < b; }
|
||||
int __gtdf2(double a, double b) { return a > b; }
|
||||
int __nedf2(double a, double b) { return a != b; }
|
||||
int __eqdf2(double a, double b) { return a == b; }
|
||||
double __floatdidf(long i) { return (double)i; }
|
||||
double __divdf3(double a, double b) { return a / b; }
|
||||
double __subdf3(double a, double b) { return a - b; }
|
||||
int __gedf2(double a, double b) { return a >= b; }
|
||||
int __fixdfsi(double a) { return (int)a; }
|
||||
long __fixdfdi(double a) { return (long)a; }
|
||||
int __ledf2(double a, double b) { return a <= b; }
|
||||
@ -1,123 +0,0 @@
|
||||
#include "pic.hpp"
|
||||
|
||||
#include <io.h>
|
||||
|
||||
namespace PIC
|
||||
{
|
||||
PIC::PIC(uint8_t MasterCommandPort, uint8_t MasterDataPort, uint8_t SlaveCommandPort, uint8_t SlaveDataPort, uint8_t MasterOffset, uint8_t SlaveOffset)
|
||||
{
|
||||
this->MasterCommandPort = MasterCommandPort;
|
||||
this->MasterDataPort = MasterDataPort;
|
||||
this->SlaveCommandPort = SlaveCommandPort;
|
||||
this->SlaveDataPort = SlaveDataPort;
|
||||
this->MasterOffset = MasterOffset;
|
||||
this->SlaveOffset = SlaveOffset;
|
||||
|
||||
MasterMask = 0xFF;
|
||||
SlaveMask = 0xFF;
|
||||
|
||||
// ICW1
|
||||
outb(MasterCommandPort, 0x11);
|
||||
outb(SlaveCommandPort, 0x11);
|
||||
|
||||
// ICW2
|
||||
outb(MasterDataPort, MasterOffset);
|
||||
outb(SlaveDataPort, SlaveOffset);
|
||||
|
||||
// ICW3
|
||||
outb(MasterDataPort, 0x04);
|
||||
outb(SlaveDataPort, 0x02);
|
||||
|
||||
// ICW4
|
||||
outb(MasterDataPort, 0x01);
|
||||
outb(SlaveDataPort, 0x01);
|
||||
|
||||
// OCW1
|
||||
outb(MasterDataPort, MasterMask);
|
||||
outb(SlaveDataPort, SlaveMask);
|
||||
}
|
||||
|
||||
PIC::~PIC()
|
||||
{
|
||||
outb(MasterDataPort, 0xFF);
|
||||
outb(SlaveDataPort, 0xFF);
|
||||
}
|
||||
|
||||
void PIC::Mask(uint8_t IRQ)
|
||||
{
|
||||
uint16_t Port;
|
||||
uint8_t Value;
|
||||
|
||||
if (IRQ < 8)
|
||||
{
|
||||
Port = MasterDataPort;
|
||||
Value = MasterMask & ~(1 << IRQ);
|
||||
MasterMask = Value;
|
||||
}
|
||||
else
|
||||
{
|
||||
Port = SlaveDataPort;
|
||||
Value = SlaveMask & ~(1 << (IRQ - 8));
|
||||
SlaveMask = Value;
|
||||
}
|
||||
|
||||
outb(Port, Value);
|
||||
}
|
||||
|
||||
void PIC::Unmask(uint8_t IRQ)
|
||||
{
|
||||
uint16_t Port;
|
||||
uint8_t Value;
|
||||
|
||||
if (IRQ < 8)
|
||||
{
|
||||
Port = MasterDataPort;
|
||||
Value = MasterMask | (1 << IRQ);
|
||||
MasterMask = Value;
|
||||
}
|
||||
else
|
||||
{
|
||||
Port = SlaveDataPort;
|
||||
Value = SlaveMask | (1 << (IRQ - 8));
|
||||
SlaveMask = Value;
|
||||
}
|
||||
|
||||
outb(Port, Value);
|
||||
}
|
||||
|
||||
void PIC::SendEOI(uint8_t IRQ)
|
||||
{
|
||||
if (IRQ >= 8)
|
||||
outb(SlaveCommandPort, 0x20);
|
||||
|
||||
outb(MasterCommandPort, 0x20);
|
||||
}
|
||||
|
||||
PIT::PIT(uint16_t Port, uint16_t Frequency)
|
||||
{
|
||||
this->Port = Port;
|
||||
this->Frequency = Frequency;
|
||||
}
|
||||
|
||||
PIT::~PIT()
|
||||
{
|
||||
}
|
||||
|
||||
void PIT::PrepareSleep(uint32_t Milliseconds)
|
||||
{
|
||||
uint16_t Divisor = 1193182 / Frequency;
|
||||
uint8_t Low = (uint8_t)(Divisor & 0xFF);
|
||||
uint8_t High = (uint8_t)((Divisor >> 8) & 0xFF);
|
||||
|
||||
outb(Port + 3, 0x36);
|
||||
outb(Port + 0, Low);
|
||||
outb(Port + 1, High);
|
||||
}
|
||||
|
||||
void PIT::PerformSleep()
|
||||
{
|
||||
uint8_t Value = inb(Port + 0);
|
||||
while (Value != 0)
|
||||
Value = inb(Port + 0);
|
||||
}
|
||||
}
|
||||
@ -1,42 +0,0 @@
|
||||
#ifndef __FENNIX_KERNEL_8259PIC_H__
|
||||
#define __FENNIX_KERNEL_8259PIC_H__
|
||||
|
||||
#include <types.h>
|
||||
|
||||
namespace PIC
|
||||
{
|
||||
class PIC
|
||||
{
|
||||
private:
|
||||
uint8_t MasterCommandPort;
|
||||
uint8_t MasterDataPort;
|
||||
uint8_t SlaveCommandPort;
|
||||
uint8_t SlaveDataPort;
|
||||
uint8_t MasterOffset;
|
||||
uint8_t SlaveOffset;
|
||||
uint8_t MasterMask;
|
||||
uint8_t SlaveMask;
|
||||
|
||||
public:
|
||||
PIC(uint8_t MasterCommandPort, uint8_t MasterDataPort, uint8_t SlaveCommandPort, uint8_t SlaveDataPort, uint8_t MasterOffset, uint8_t SlaveOffset);
|
||||
~PIC();
|
||||
void Mask(uint8_t IRQ);
|
||||
void Unmask(uint8_t IRQ);
|
||||
void SendEOI(uint8_t IRQ);
|
||||
};
|
||||
|
||||
class PIT
|
||||
{
|
||||
private:
|
||||
uint16_t Port;
|
||||
uint16_t Frequency;
|
||||
|
||||
public:
|
||||
PIT(uint16_t Port, uint16_t Frequency);
|
||||
~PIT();
|
||||
void PrepareSleep(uint32_t Milliseconds);
|
||||
void PerformSleep();
|
||||
};
|
||||
}
|
||||
|
||||
#endif // !__FENNIX_KERNEL_8259PIC_H__
|
||||
@ -1,343 +0,0 @@
|
||||
#include <types.h>
|
||||
|
||||
#include <boot/protocols/multiboot2.h>
|
||||
#include <io.h>
|
||||
|
||||
#include "../../kernel.h"
|
||||
|
||||
enum VideoType
|
||||
{
|
||||
VIDEO_TYPE_NONE = 0x00,
|
||||
VIDEO_TYPE_COLOUR = 0x20,
|
||||
VIDEO_TYPE_MONOCHROME = 0x30,
|
||||
};
|
||||
|
||||
uint16_t GetBiosAreaHardware()
|
||||
{
|
||||
const uint16_t *BIOSDataAreaDetectedHardware = (const uint16_t *)0x410;
|
||||
return *BIOSDataAreaDetectedHardware;
|
||||
}
|
||||
|
||||
enum VideoType GetVideoType() { return (enum VideoType)(GetBiosAreaHardware() & 0x30); }
|
||||
|
||||
void GetSMBIOS()
|
||||
{
|
||||
unsigned char *SMBIOSAddress = (unsigned char *)0xF0000;
|
||||
while ((unsigned int)(unsigned long)SMBIOSAddress < 0x100000)
|
||||
{
|
||||
if (SMBIOSAddress[0] == '_' &&
|
||||
SMBIOSAddress[1] == 'S' &&
|
||||
SMBIOSAddress[2] == 'M' &&
|
||||
SMBIOSAddress[3] == '_')
|
||||
{
|
||||
unsigned char Checksum = 0;
|
||||
int Length = SMBIOSAddress[5];
|
||||
for (int i = 0; i < Length; i++)
|
||||
Checksum += SMBIOSAddress[i];
|
||||
|
||||
if (Checksum == 0)
|
||||
break;
|
||||
}
|
||||
SMBIOSAddress += 16;
|
||||
}
|
||||
|
||||
if ((unsigned int)(unsigned long)SMBIOSAddress == 0x100000)
|
||||
{
|
||||
// No SMBIOS found
|
||||
}
|
||||
}
|
||||
|
||||
struct multiboot_info
|
||||
{
|
||||
multiboot_uint32_t Size;
|
||||
multiboot_uint32_t Reserved;
|
||||
struct multiboot_tag *Tag;
|
||||
};
|
||||
|
||||
EXTERNC void x32Multiboot2Entry(multiboot_info *Info, unsigned int Magic)
|
||||
{
|
||||
if (Info == NULL || Magic == NULL)
|
||||
{
|
||||
if (Magic == NULL)
|
||||
error("Multiboot magic is NULL");
|
||||
if (Info == NULL)
|
||||
error("Multiboot info is NULL");
|
||||
CPU::Stop();
|
||||
}
|
||||
else if (Magic != MULTIBOOT2_BOOTLOADER_MAGIC)
|
||||
{
|
||||
error("Multiboot magic is invalid (%#x != %#x)", Magic, MULTIBOOT2_BOOTLOADER_MAGIC);
|
||||
trace("Hello, World!");
|
||||
CPU::Stop();
|
||||
}
|
||||
|
||||
uint64_t div = 1193180 / 1000;
|
||||
outb(0x43, 0xB6);
|
||||
outb(0x42, (uint8_t)div);
|
||||
outb(0x42, (uint8_t)(div >> 8));
|
||||
uint8_t tmp = inb(0x61);
|
||||
if (tmp != (tmp | 3))
|
||||
outb(0x61, tmp | 3);
|
||||
|
||||
BootInfo binfo;
|
||||
uint32_t Itr = 0;
|
||||
|
||||
for (uint32_t i = 8; i < Info->Size; i += Itr)
|
||||
{
|
||||
multiboot_tag *Tag = (multiboot_tag *)((uint8_t *)Info + i);
|
||||
if (Tag->type == MULTIBOOT_TAG_TYPE_END)
|
||||
break;
|
||||
|
||||
switch (Tag->type)
|
||||
{
|
||||
case MULTIBOOT_TAG_TYPE_CMDLINE:
|
||||
{
|
||||
strncpy(binfo.Kernel.CommandLine,
|
||||
((multiboot_tag_string *)Tag)->string,
|
||||
strlen(((multiboot_tag_string *)Tag)->string));
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_BOOT_LOADER_NAME:
|
||||
{
|
||||
strncpy(binfo.Bootloader.Name,
|
||||
((multiboot_tag_string *)Tag)->string,
|
||||
strlen(((multiboot_tag_string *)Tag)->string));
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_MODULE:
|
||||
{
|
||||
multiboot_tag_module *module = (multiboot_tag_module *)Tag;
|
||||
static int module_count = 0;
|
||||
binfo.Modules[module_count++].Address = (void *)module->mod_start;
|
||||
binfo.Modules[module_count++].Size = module->size;
|
||||
strncpy(binfo.Modules[module_count++].Path, "(null)", 6);
|
||||
strncpy(binfo.Modules[module_count++].CommandLine, module->cmdline,
|
||||
strlen(module->cmdline));
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_BASIC_MEMINFO:
|
||||
{
|
||||
multiboot_tag_basic_meminfo *meminfo = (multiboot_tag_basic_meminfo *)Tag;
|
||||
fixme("basic_meminfo->[mem_lower: %#x, mem_upper: %#x]",
|
||||
meminfo->mem_lower, meminfo->mem_upper);
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_BOOTDEV:
|
||||
{
|
||||
multiboot_tag_bootdev *bootdev = (multiboot_tag_bootdev *)Tag;
|
||||
fixme("bootdev->[biosdev: %#x, slice: %#x, part: %#x]",
|
||||
bootdev->biosdev, bootdev->slice, bootdev->part);
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_MMAP:
|
||||
{
|
||||
multiboot_tag_mmap *mmap = (multiboot_tag_mmap *)Tag;
|
||||
uint32_t EntryCount = mmap->size / sizeof(multiboot_mmap_entry);
|
||||
|
||||
binfo.Memory.Entries = EntryCount;
|
||||
for (uint32_t i = 0; i < EntryCount; i++)
|
||||
{
|
||||
if (EntryCount > MAX_MEMORY_ENTRIES)
|
||||
{
|
||||
warn("Too many memory entries, skipping the rest...");
|
||||
break;
|
||||
}
|
||||
|
||||
multiboot_mmap_entry entry = mmap->entries[i];
|
||||
binfo.Memory.Size += entry.len;
|
||||
switch (entry.type)
|
||||
{
|
||||
case MULTIBOOT_MEMORY_AVAILABLE:
|
||||
binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
|
||||
binfo.Memory.Entry[i].Length = entry.len;
|
||||
binfo.Memory.Entry[i].Type = Usable;
|
||||
break;
|
||||
case MULTIBOOT_MEMORY_RESERVED:
|
||||
binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
|
||||
binfo.Memory.Entry[i].Length = entry.len;
|
||||
binfo.Memory.Entry[i].Type = Reserved;
|
||||
break;
|
||||
case MULTIBOOT_MEMORY_ACPI_RECLAIMABLE:
|
||||
binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
|
||||
binfo.Memory.Entry[i].Length = entry.len;
|
||||
binfo.Memory.Entry[i].Type = ACPIReclaimable;
|
||||
break;
|
||||
case MULTIBOOT_MEMORY_NVS:
|
||||
binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
|
||||
binfo.Memory.Entry[i].Length = entry.len;
|
||||
binfo.Memory.Entry[i].Type = ACPINVS;
|
||||
break;
|
||||
case MULTIBOOT_MEMORY_BADRAM:
|
||||
binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
|
||||
binfo.Memory.Entry[i].Length = entry.len;
|
||||
binfo.Memory.Entry[i].Type = BadMemory;
|
||||
break;
|
||||
default:
|
||||
binfo.Memory.Entry[i].BaseAddress = (void *)entry.addr;
|
||||
binfo.Memory.Entry[i].Length = entry.len;
|
||||
binfo.Memory.Entry[i].Type = Unknown;
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_VBE:
|
||||
{
|
||||
multiboot_tag_vbe *vbe = (multiboot_tag_vbe *)Tag;
|
||||
fixme("vbe->[vbe_mode: %#x, vbe_interface_seg: %#x, vbe_interface_off: %#x, vbe_interface_len: %#x]",
|
||||
vbe->vbe_mode, vbe->vbe_interface_seg, vbe->vbe_interface_off, vbe->vbe_interface_len);
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_FRAMEBUFFER:
|
||||
{
|
||||
multiboot_tag_framebuffer *fb = (multiboot_tag_framebuffer *)Tag;
|
||||
static int fb_count = 0;
|
||||
|
||||
binfo.Framebuffer[fb_count].BaseAddress = (void *)fb->common.framebuffer_addr;
|
||||
binfo.Framebuffer[fb_count].Width = fb->common.framebuffer_width;
|
||||
binfo.Framebuffer[fb_count].Height = fb->common.framebuffer_height;
|
||||
binfo.Framebuffer[fb_count].Pitch = fb->common.framebuffer_pitch;
|
||||
binfo.Framebuffer[fb_count].BitsPerPixel = fb->common.framebuffer_bpp;
|
||||
binfo.Framebuffer[fb_count].MemoryModel = fb->common.framebuffer_type;
|
||||
|
||||
switch (fb->common.framebuffer_type)
|
||||
{
|
||||
case MULTIBOOT_FRAMEBUFFER_TYPE_INDEXED:
|
||||
{
|
||||
fixme("indexed");
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_FRAMEBUFFER_TYPE_RGB:
|
||||
{
|
||||
binfo.Framebuffer[fb_count].RedMaskSize = fb->framebuffer_red_mask_size;
|
||||
binfo.Framebuffer[fb_count].RedMaskShift = fb->framebuffer_red_field_position;
|
||||
binfo.Framebuffer[fb_count].GreenMaskSize = fb->framebuffer_green_mask_size;
|
||||
binfo.Framebuffer[fb_count].GreenMaskShift = fb->framebuffer_green_field_position;
|
||||
binfo.Framebuffer[fb_count].BlueMaskSize = fb->framebuffer_blue_mask_size;
|
||||
binfo.Framebuffer[fb_count].BlueMaskShift = fb->framebuffer_blue_field_position;
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_FRAMEBUFFER_TYPE_EGA_TEXT:
|
||||
{
|
||||
fixme("ega_text");
|
||||
break;
|
||||
}
|
||||
}
|
||||
debug("Framebuffer %d: %dx%d %d bpp", i, fb->common.framebuffer_width, fb->common.framebuffer_height, fb->common.framebuffer_bpp);
|
||||
debug("More info:\nAddress: %p\nPitch: %lld\nMemoryModel: %d\nRedMaskSize: %d\nRedMaskShift: %d\nGreenMaskSize: %d\nGreenMaskShift: %d\nBlueMaskSize: %d\nBlueMaskShift: %d",
|
||||
fb->common.framebuffer_addr, fb->common.framebuffer_pitch, fb->common.framebuffer_type,
|
||||
fb->framebuffer_red_mask_size, fb->framebuffer_red_field_position, fb->framebuffer_green_mask_size,
|
||||
fb->framebuffer_green_field_position, fb->framebuffer_blue_mask_size, fb->framebuffer_blue_field_position);
|
||||
|
||||
fb_count++;
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_ELF_SECTIONS:
|
||||
{
|
||||
multiboot_tag_elf_sections *elf = (multiboot_tag_elf_sections *)Tag;
|
||||
fixme("elf_sections->[num=%d, size=%d, entsize=%d, shndx=%d]",
|
||||
elf->num, elf->size, elf->entsize, elf->shndx);
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_APM:
|
||||
{
|
||||
multiboot_tag_apm *apm = (multiboot_tag_apm *)Tag;
|
||||
fixme("apm->[version: %d, cseg: %d, offset: %d, cseg_16: %d, dseg: %d, flags: %d, cseg_len: %d, cseg_16_len: %d, dseg_len: %d]",
|
||||
apm->version, apm->cseg, apm->offset, apm->cseg_16, apm->dseg, apm->flags, apm->cseg_len, apm->cseg_16_len, apm->dseg_len);
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_EFI32:
|
||||
{
|
||||
multiboot_tag_efi32 *efi32 = (multiboot_tag_efi32 *)Tag;
|
||||
fixme("efi32->[pointer: %p, size: %d]", efi32->pointer, efi32->size);
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_EFI64:
|
||||
{
|
||||
multiboot_tag_efi64 *efi64 = (multiboot_tag_efi64 *)Tag;
|
||||
fixme("efi64->[pointer: %p, size: %d]", efi64->pointer, efi64->size);
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_SMBIOS:
|
||||
{
|
||||
multiboot_tag_smbios *smbios = (multiboot_tag_smbios *)Tag;
|
||||
fixme("smbios->[major: %d, minor: %d]", smbios->major, smbios->minor);
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_ACPI_OLD:
|
||||
{
|
||||
binfo.RSDP = (BootInfo::RSDPInfo *)((multiboot_tag_old_acpi *)Tag)->rsdp;
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_ACPI_NEW:
|
||||
{
|
||||
binfo.RSDP = (BootInfo::RSDPInfo *)((multiboot_tag_new_acpi *)Tag)->rsdp;
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_NETWORK:
|
||||
{
|
||||
multiboot_tag_network *net = (multiboot_tag_network *)Tag;
|
||||
fixme("network->[dhcpack: %p]", net->dhcpack);
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_EFI_MMAP:
|
||||
{
|
||||
multiboot_tag_efi_mmap *efi_mmap = (multiboot_tag_efi_mmap *)Tag;
|
||||
fixme("efi_mmap->[descr_size: %d, descr_vers: %d, efi_mmap: %p]",
|
||||
efi_mmap->descr_size, efi_mmap->descr_vers, efi_mmap->efi_mmap);
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_EFI_BS:
|
||||
{
|
||||
fixme("efi_bs->[%p] (unknown structure)", Tag);
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_EFI32_IH:
|
||||
{
|
||||
multiboot_tag_efi32_ih *efi32_ih = (multiboot_tag_efi32_ih *)Tag;
|
||||
fixme("efi32_ih->[pointer: %p]", efi32_ih->pointer);
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_EFI64_IH:
|
||||
{
|
||||
multiboot_tag_efi64_ih *efi64_ih = (multiboot_tag_efi64_ih *)Tag;
|
||||
fixme("efi64_ih->[pointer: %p]", efi64_ih->pointer);
|
||||
break;
|
||||
}
|
||||
case MULTIBOOT_TAG_TYPE_LOAD_BASE_ADDR:
|
||||
{
|
||||
multiboot_tag_load_base_addr *load_base_addr = (multiboot_tag_load_base_addr *)Tag;
|
||||
binfo.Kernel.PhysicalBase = (void *)load_base_addr->load_base_addr;
|
||||
binfo.Kernel.VirtualBase = (void *)(load_base_addr->load_base_addr + 0xC0000000);
|
||||
break;
|
||||
}
|
||||
}
|
||||
Itr = Tag->size;
|
||||
if ((Itr % 8) != 0)
|
||||
Itr += (8 - Itr % 8);
|
||||
}
|
||||
|
||||
tmp = inb(0x61) & 0xFC;
|
||||
outb(0x61, tmp);
|
||||
|
||||
int *vm = (int *)0xb8000;
|
||||
// "Not supported yet"
|
||||
vm[0] = 0x054E;
|
||||
vm[1] = 0x056F;
|
||||
vm[2] = 0x0574;
|
||||
vm[3] = 0x0520;
|
||||
vm[4] = 0x0573;
|
||||
vm[5] = 0x0575;
|
||||
vm[6] = 0x0570;
|
||||
vm[7] = 0x0570;
|
||||
vm[8] = 0x0572;
|
||||
vm[9] = 0x056F;
|
||||
vm[10] = 0x0574;
|
||||
vm[11] = 0x0520;
|
||||
vm[12] = 0x0579;
|
||||
vm[13] = 0x0565;
|
||||
vm[14] = 0x0574;
|
||||
|
||||
CPU::Stop();
|
||||
// Entry(&binfo);
|
||||
}
|
||||
@ -1,13 +0,0 @@
|
||||
#include <syscalls.hpp>
|
||||
|
||||
#include <cpu.hpp>
|
||||
|
||||
#include "cpu/gdt.hpp"
|
||||
|
||||
using namespace CPU::x32;
|
||||
|
||||
extern "C" uint32_t SystemCallsHandler(SyscallsFrame *regs);
|
||||
|
||||
void InitializeSystemCalls()
|
||||
{
|
||||
}
|
||||
@ -1,37 +0,0 @@
|
||||
#include <smp.hpp>
|
||||
|
||||
#include <interrupts.hpp>
|
||||
#include <memory.hpp>
|
||||
#include <assert.h>
|
||||
#include <cpu.hpp>
|
||||
|
||||
#include "../../../kernel.h"
|
||||
|
||||
volatile bool CPUEnabled = false;
|
||||
|
||||
#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
|
||||
static __attribute__((aligned(PAGE_SIZE))) CPUData CPUs[MAX_CPU] = {0};
|
||||
|
||||
CPUData *GetCPU(uint64_t id) { return &CPUs[id]; }
|
||||
|
||||
CPUData *GetCurrentCPU()
|
||||
{
|
||||
uint64_t ret = 0;
|
||||
if (!(&CPUs[ret])->IsActive)
|
||||
{
|
||||
error("CPU %d is not active!", ret);
|
||||
return &CPUs[0];
|
||||
}
|
||||
assert((&CPUs[ret])->Checksum == CPU_DATA_CHECKSUM);
|
||||
return &CPUs[ret];
|
||||
}
|
||||
|
||||
namespace SMP
|
||||
{
|
||||
int CPUCores = 0;
|
||||
|
||||
void Initialize(void *madt)
|
||||
{
|
||||
fixme("SMP::Initialize() is not implemented!");
|
||||
}
|
||||
}
|
||||
@ -1,337 +0,0 @@
|
||||
#ifndef __FENNIX_KERNEL_APIC_H__
|
||||
#define __FENNIX_KERNEL_APIC_H__
|
||||
|
||||
#include <types.h>
|
||||
|
||||
#include <interrupts.hpp>
|
||||
#include <cpu.hpp>
|
||||
|
||||
namespace APIC
|
||||
{
|
||||
enum APICRegisters
|
||||
{
|
||||
// source from: https://github.com/pdoane/osdev/blob/master/intr/local_apic.c
|
||||
APIC_ID = 0x20, // Local APIC ID
|
||||
APIC_VER = 0x30, // Local APIC Version
|
||||
APIC_TPR = 0x80, // Task Priority
|
||||
APIC_APR = 0x90, // Arbitration Priority
|
||||
APIC_PPR = 0xA0, // Processor Priority
|
||||
APIC_EOI = 0xB0, // EOI
|
||||
APIC_RRD = 0xC0, // Remote Read
|
||||
APIC_LDR = 0xD0, // Logical Destination
|
||||
APIC_DFR = 0xE0, // Destination Format
|
||||
APIC_SVR = 0xF0, // Spurious Interrupt Vector
|
||||
APIC_ISR = 0x100, // In-Service (8 registers)
|
||||
APIC_TMR = 0x180, // Trigger Mode (8 registers)
|
||||
APIC_IRR = 0x200, // Interrupt Request (8 registers)
|
||||
APIC_ESR = 0x280, // Error Status
|
||||
APIC_ICRLO = 0x300, // Interrupt Command
|
||||
APIC_ICRHI = 0x310, // Interrupt Command [63:32]
|
||||
APIC_TIMER = 0x320, // LVT Timer
|
||||
APIC_THERMAL = 0x330, // LVT Thermal Sensor
|
||||
APIC_PERF = 0x340, // LVT Performance Counter
|
||||
APIC_LINT0 = 0x350, // LVT LINT0
|
||||
APIC_LINT1 = 0x360, // LVT LINT1
|
||||
APIC_ERROR = 0x370, // LVT Error
|
||||
APIC_TICR = 0x380, // Initial Count (for Timer)
|
||||
APIC_TCCR = 0x390, // Current Count (for Timer)
|
||||
APIC_TDCR = 0x3E0, // Divide Configuration (for Timer)
|
||||
};
|
||||
|
||||
enum IOAPICRegisters
|
||||
{
|
||||
GetIOAPICVersion = 0x1
|
||||
};
|
||||
|
||||
enum IOAPICFlags
|
||||
{
|
||||
ActiveHighLow = 2,
|
||||
EdgeLevel = 8
|
||||
};
|
||||
|
||||
enum APICDeliveryMode
|
||||
{
|
||||
Fixed = 0b000,
|
||||
LowestPriority = 0b001, /* Reserved */
|
||||
SMI = 0b010,
|
||||
APIC_DELIVERY_MODE_RESERVED0 = 0b011, /* Reserved */
|
||||
NMI = 0b100,
|
||||
INIT = 0b101,
|
||||
Startup = 0b110,
|
||||
ExtINT = 0b111 /* Reserved */
|
||||
};
|
||||
|
||||
enum APICDestinationMode
|
||||
{
|
||||
Physical = 0b0,
|
||||
Logical = 0b1
|
||||
};
|
||||
|
||||
enum APICDeliveryStatus
|
||||
{
|
||||
Idle = 0b0,
|
||||
SendPending = 0b1
|
||||
};
|
||||
|
||||
enum APICLevel
|
||||
{
|
||||
DeAssert = 0b0,
|
||||
Assert = 0b1
|
||||
};
|
||||
|
||||
enum APICTriggerMode
|
||||
{
|
||||
Edge = 0b0,
|
||||
Level = 0b1
|
||||
};
|
||||
|
||||
enum APICDestinationShorthand
|
||||
{
|
||||
NoShorthand = 0b00,
|
||||
Self = 0b01,
|
||||
AllIncludingSelf = 0b10,
|
||||
AllExcludingSelf = 0b11
|
||||
};
|
||||
|
||||
enum LVTTimerDivide
|
||||
{
|
||||
DivideBy2 = 0b000,
|
||||
DivideBy4 = 0b001,
|
||||
DivideBy8 = 0b010,
|
||||
DivideBy16 = 0b011,
|
||||
DivideBy32 = 0b100,
|
||||
DivideBy64 = 0b101,
|
||||
DivideBy128 = 0b110,
|
||||
DivideBy1 = 0b111
|
||||
};
|
||||
|
||||
enum LVTTimerMask
|
||||
{
|
||||
Unmasked = 0b0,
|
||||
Masked = 0b1
|
||||
};
|
||||
|
||||
enum LVTTimerMode
|
||||
{
|
||||
OneShot = 0b00,
|
||||
Periodic = 0b01,
|
||||
TSCDeadline = 0b10
|
||||
};
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Interrupt Vector */
|
||||
uint64_t Vector : 8;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved0 : 4;
|
||||
/**
|
||||
* @brief Delivery Status
|
||||
*
|
||||
* 0: Idle
|
||||
* 1: Send Pending
|
||||
*/
|
||||
uint64_t DeliveryStatus : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved1 : 3;
|
||||
/**
|
||||
* @brief Mask
|
||||
*
|
||||
* 0: Not masked
|
||||
* 1: Masked
|
||||
*/
|
||||
uint64_t Mask : 1;
|
||||
/** @brief Timer Mode
|
||||
*
|
||||
* 0: One-shot
|
||||
* 1: Periodic
|
||||
* 2: TSC-Deadline
|
||||
*/
|
||||
uint64_t TimerMode : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved2 : 14;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __attribute__((packed)) LVTTimer;
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Spurious Vector */
|
||||
uint64_t Vector : 8;
|
||||
/** @brief Enable or disable APIC software */
|
||||
uint64_t Software : 1;
|
||||
/** @brief Focus Processor Checking */
|
||||
uint64_t FocusProcessorChecking : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved : 2;
|
||||
/** @brief Disable EOI Broadcast */
|
||||
uint64_t DisableEOIBroadcast : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved1 : 19;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __attribute__((packed)) Spurious;
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Interrupt Vector */
|
||||
uint64_t Vector : 8;
|
||||
/** @brief Delivery Mode */
|
||||
uint64_t DeliveryMode : 3;
|
||||
/** @brief Destination Mode
|
||||
*
|
||||
* 0: Physical
|
||||
* 1: Logical
|
||||
*/
|
||||
uint64_t DestinationMode : 1;
|
||||
/** @brief Delivery Status
|
||||
*
|
||||
* @note Reserved when in x2APIC mode
|
||||
*/
|
||||
uint64_t DeliveryStatus : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved0 : 1;
|
||||
/** @brief Level
|
||||
*
|
||||
* 0: Deassert
|
||||
* 1: Assert
|
||||
*/
|
||||
uint64_t Level : 1;
|
||||
/** @brief Trigger Mode
|
||||
*
|
||||
* 0: Edge
|
||||
* 1: Level
|
||||
*/
|
||||
uint64_t TriggerMode : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved1 : 2;
|
||||
/** @brief Destination Shorthand
|
||||
*
|
||||
* 0: No shorthand
|
||||
* 1: Self
|
||||
* 2: All including self
|
||||
* 3: All excluding self
|
||||
*/
|
||||
uint64_t DestinationShorthand : 2;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved2 : 12;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __attribute__((packed)) InterruptCommandRegisterLow;
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved0 : 24;
|
||||
/** @brief Destination */
|
||||
uint64_t Destination : 8;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __attribute__((packed)) InterruptCommandRegisterHigh;
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** @brief Interrupt Vector */
|
||||
uint64_t Vector : 8;
|
||||
/** @brief Delivery Mode */
|
||||
uint64_t DeliveryMode : 3;
|
||||
/** @brief Destination Mode
|
||||
*
|
||||
* 0: Physical
|
||||
* 1: Logical
|
||||
*/
|
||||
uint64_t DestinationMode : 1;
|
||||
/** @brief Delivery Status */
|
||||
uint64_t DeliveryStatus : 1;
|
||||
/** @brief Interrupt Input Pin Polarity
|
||||
*
|
||||
* 0: Active High
|
||||
* 1: Active Low
|
||||
*/
|
||||
uint64_t Polarity : 1;
|
||||
/** @brief Remote IRR */
|
||||
uint64_t RemoteIRR : 1;
|
||||
/** @brief Trigger Mode
|
||||
*
|
||||
* 0: Edge
|
||||
* 1: Level
|
||||
*/
|
||||
uint64_t TriggerMode : 1;
|
||||
/** @brief Mask */
|
||||
uint64_t Mask : 1;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved0 : 15;
|
||||
/** @brief Reserved */
|
||||
uint64_t Reserved1 : 24;
|
||||
/** @brief Destination */
|
||||
uint64_t DestinationID : 8;
|
||||
};
|
||||
struct
|
||||
{
|
||||
uint64_t Low;
|
||||
uint64_t High;
|
||||
} split;
|
||||
uint64_t raw;
|
||||
} __attribute__((packed)) IOAPICRedirectEntry;
|
||||
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint64_t Version : 8;
|
||||
uint64_t Reserved : 8;
|
||||
uint64_t MaximumRedirectionEntry : 8;
|
||||
uint64_t Reserved2 : 8;
|
||||
};
|
||||
uint64_t raw;
|
||||
} __attribute__((packed)) IOAPICVersion;
|
||||
|
||||
class APIC
|
||||
{
|
||||
private:
|
||||
bool x2APICSupported = false;
|
||||
uint64_t APICBaseAddress = 0;
|
||||
|
||||
public:
|
||||
uint32_t Read(uint32_t Register);
|
||||
void Write(uint32_t Register, uint32_t Value);
|
||||
void IOWrite(uint64_t Base, uint32_t Register, uint32_t Value);
|
||||
uint32_t IORead(uint64_t Base, uint32_t Register);
|
||||
void EOI();
|
||||
void RedirectIRQs(int CPU = 0);
|
||||
void WaitForIPI();
|
||||
void IPI(uint8_t CPU, InterruptCommandRegisterLow icr);
|
||||
void SendInitIPI(uint8_t CPU);
|
||||
void SendStartupIPI(uint8_t CPU, uint64_t StartupAddress);
|
||||
uint32_t IOGetMaxRedirect(uint32_t APICID);
|
||||
void RawRedirectIRQ(uint8_t Vector, uint32_t GSI, uint16_t Flags, int CPU, int Status);
|
||||
void RedirectIRQ(int CPU, uint8_t IRQ, int Status);
|
||||
APIC(int Core);
|
||||
~APIC();
|
||||
};
|
||||
|
||||
class Timer : public Interrupts::Handler
|
||||
{
|
||||
private:
|
||||
APIC *lapic;
|
||||
uint64_t Ticks = 0;
|
||||
void OnInterruptReceived(CPU::x64::TrapFrame *Frame);
|
||||
|
||||
public:
|
||||
uint64_t GetTicks() { return Ticks; }
|
||||
void OneShot(uint32_t Vector, uint64_t Miliseconds);
|
||||
Timer(APIC *apic);
|
||||
~Timer();
|
||||
};
|
||||
}
|
||||
|
||||
#endif // !__FENNIX_KERNEL_APIC_H__
|
||||
@ -1,11 +0,0 @@
|
||||
[bits 64]
|
||||
|
||||
[global _i386_fxsave]
|
||||
_i386_fxsave:
|
||||
fxsave [edi]
|
||||
ret
|
||||
|
||||
[global _i386_fxrstor]
|
||||
_i386_fxrstor:
|
||||
fxrstor [edi]
|
||||
ret
|
||||
@ -1,11 +0,0 @@
|
||||
#ifndef __FENNIX_KERNEL_GDT_H__
|
||||
#define __FENNIX_KERNEL_GDT_H__
|
||||
|
||||
#include <types.h>
|
||||
|
||||
namespace GlobalDescriptorTable
|
||||
{
|
||||
void Init(int Core);
|
||||
}
|
||||
|
||||
#endif // !__FENNIX_KERNEL_GDT_H__
|
||||
@ -1,11 +0,0 @@
|
||||
#ifndef __FENNIX_KERNEL_IDT_H__
|
||||
#define __FENNIX_KERNEL_IDT_H__
|
||||
|
||||
#include <types.h>
|
||||
|
||||
namespace InterruptDescriptorTable
|
||||
{
|
||||
void Init(int Core);
|
||||
}
|
||||
|
||||
#endif // !__FENNIX_KERNEL_IDT_H__
|
||||
@ -1,42 +0,0 @@
|
||||
OUTPUT_FORMAT(elf32-i386)
|
||||
OUTPUT_ARCH(i386)
|
||||
|
||||
ENTRY(_start)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = 0xC0100000;
|
||||
_kernel_start = .;
|
||||
|
||||
.text ALIGN(4096) : AT(ADDR(.text) - 0xC0000000)
|
||||
{
|
||||
*(.multiboot2)
|
||||
*(.text .text.*)
|
||||
}
|
||||
_kernel_text_end = .;
|
||||
|
||||
.data ALIGN (4096) : AT(ADDR(.data) - 0xC0000000)
|
||||
{
|
||||
*(.data .data.*)
|
||||
}
|
||||
_kernel_data_end = .;
|
||||
|
||||
.rodata ALIGN (4096) : AT(ADDR(.rodata) - 0xC0000000)
|
||||
{
|
||||
*(.rodata .rodata.*)
|
||||
}
|
||||
_kernel_rodata_end = .;
|
||||
|
||||
.bss ALIGN (4096) : AT(ADDR(.bss) - 0xC0000000)
|
||||
{
|
||||
*(COMMON)
|
||||
*(.bss .bss.*)
|
||||
}
|
||||
_kernel_end = .;
|
||||
|
||||
/DISCARD/ :
|
||||
{
|
||||
*(.comment*)
|
||||
*(.note*)
|
||||
}
|
||||
}
|
||||
@ -1,15 +0,0 @@
|
||||
// #include <types.h>
|
||||
|
||||
// #include <debug.h>
|
||||
|
||||
// int Entry(void *Info);
|
||||
|
||||
// void _start(void *Raw)
|
||||
// {
|
||||
// error("Todo");
|
||||
// while (1)
|
||||
// asmv("hlt");
|
||||
// Entry(NULL);
|
||||
// return;
|
||||
// }
|
||||
// C stuff
|
||||
@ -1,69 +0,0 @@
|
||||
; Inspired From: https://github.com/MQuy/mos/blob/master/src/kernel/boot.asm
|
||||
section .multiboot2
|
||||
align 4096
|
||||
HEADER_START:
|
||||
dd 0xE85250D6
|
||||
dd 0
|
||||
dd (HEADER_END - HEADER_START)
|
||||
dd 0x100000000 - (HEADER_END - HEADER_START) - 0 - 0xE85250D6
|
||||
align 8
|
||||
MB2_TAG_START:
|
||||
dw 0
|
||||
dw 0
|
||||
dd MB2_TAG_END - MB2_TAG_START
|
||||
MB2_TAG_END:
|
||||
HEADER_END:
|
||||
|
||||
KERNEL_VIRTUAL_BASE equ 0xC0000000 ; 3GB
|
||||
KERNEL_PAGE_NUMBER equ (KERNEL_VIRTUAL_BASE >> 22) ; 768
|
||||
KERNEL_STACK_SIZE equ 0x4000 ; 16KB
|
||||
|
||||
extern x32Multiboot2Entry
|
||||
global _start
|
||||
|
||||
section .data
|
||||
align 0x1000
|
||||
BootPageTable:
|
||||
dd 0x00000083
|
||||
times ((KERNEL_PAGE_NUMBER) - 1) dd 0
|
||||
dd 0x00000083
|
||||
times (1024 - KERNEL_PAGE_NUMBER - 1) dd 0
|
||||
|
||||
section .text
|
||||
_start:
|
||||
mov word [0xb8000], 0x074C ; L
|
||||
mov word [0xb8002], 0x076F ; o
|
||||
mov word [0xb8004], 0x0761 ; a
|
||||
mov word [0xb8006], 0x0764 ; d
|
||||
mov word [0xb8008], 0x0769 ; i
|
||||
mov word [0xb800a], 0x076E ; n
|
||||
mov word [0xb800c], 0x0767 ; g
|
||||
mov word [0xb800e], 0x072E ; .
|
||||
mov word [0xb8010], 0x072E ; .
|
||||
mov word [0xb8012], 0x072E ; .
|
||||
mov ecx, (BootPageTable - KERNEL_VIRTUAL_BASE)
|
||||
mov cr3, ecx
|
||||
mov ecx, cr4
|
||||
or ecx, 0x00000010 ; Set PSE in CR4
|
||||
mov cr4, ecx
|
||||
mov ecx, cr0
|
||||
or ecx, 0x80000000 ; Set PG in CR0
|
||||
mov cr0, ecx
|
||||
lea ecx, [HigherHalfStart]
|
||||
jmp ecx
|
||||
|
||||
HigherHalfStart:
|
||||
mov esp, KernelStack + KERNEL_STACK_SIZE
|
||||
|
||||
push eax ; Multiboot2 Magic
|
||||
add ebx, KERNEL_VIRTUAL_BASE
|
||||
push ebx ; Multiboot2 Header
|
||||
call x32Multiboot2Entry
|
||||
Loop:
|
||||
hlt
|
||||
jmp Loop
|
||||
|
||||
section .bss
|
||||
align 16
|
||||
KernelStack :
|
||||
resb KERNEL_STACK_SIZE
|
||||
@ -1 +0,0 @@
|
||||
// C++ constructor/destructor stuff
|
||||
@ -1 +0,0 @@
|
||||
// C++ constructor/destructor stuff
|
||||
@ -1,13 +0,0 @@
|
||||
.section .init
|
||||
.global _init
|
||||
.type _init, @function
|
||||
_init:
|
||||
push %ebp
|
||||
mov %esp, %ebp
|
||||
|
||||
.section .fini
|
||||
.global _fini
|
||||
.type _fini, @function
|
||||
_fini:
|
||||
push %ebp
|
||||
mov %esp, %ebp
|
||||
@ -1,7 +0,0 @@
|
||||
.section .init
|
||||
pop %ebp
|
||||
ret
|
||||
|
||||
.section .fini
|
||||
pop %ebp
|
||||
ret
|
||||
Reference in New Issue
Block a user