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184
Drivers/include/pci.h
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184
Drivers/include/pci.h
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/*
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This file is part of Fennix Drivers.
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Fennix Drivers is free software: you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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Fennix Drivers is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Fennix Drivers. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef __FENNIX_API_PCI_H__
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#define __FENNIX_API_PCI_H__
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#include <types.h>
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/* https://sites.uclouvain.be/SystInfo/usr/include/linux/pci_regs.h.html */
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typedef enum
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{
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/** @brief Enable response in I/O space */
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PCI_COMMAND_IO = 0x1,
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/** @brief Enable response in Memory space */
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PCI_COMMAND_MEMORY = 0x2,
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/** @brief Enable bus mastering */
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PCI_COMMAND_MASTER = 0x4,
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/** @brief Enable response to special cycles */
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PCI_COMMAND_SPECIAL = 0x8,
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/** @brief Use memory write and invalidate */
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PCI_COMMAND_INVALIDATE = 0x10,
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/** @brief Enable palette snooping */
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PCI_COMMAND_VGA_PALETTE = 0x20,
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/** @brief Enable parity checking */
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PCI_COMMAND_PARITY = 0x40,
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/** @brief Enable address/data stepping */
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PCI_COMMAND_WAIT = 0x80,
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/** @brief Enable SERR */
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PCI_COMMAND_SERR = 0x100,
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/** @brief Enable back-to-back writes */
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PCI_COMMAND_FAST_BACK = 0x200,
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/** @brief INTx Emulation Disable */
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PCI_COMMAND_INTX_DISABLE = 0x400
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} PCI_COMMANDS;
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typedef struct
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{
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uint16_t VendorID;
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uint16_t DeviceID;
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uint16_t Command;
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uint16_t Status;
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uint8_t RevisionID;
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uint8_t ProgIF;
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uint8_t Subclass;
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uint8_t Class;
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uint8_t CacheLineSize;
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uint8_t LatencyTimer;
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uint8_t HeaderType;
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uint8_t BIST;
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} __attribute__((packed)) PCIDeviceHeader;
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typedef struct
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{
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PCIDeviceHeader Header;
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uint32_t BAR0;
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uint32_t BAR1;
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uint32_t BAR2;
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uint32_t BAR3;
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uint32_t BAR4;
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uint32_t BAR5;
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uint32_t CardbusCISPointer;
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uint16_t SubsystemVendorID;
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uint16_t SubsystemID;
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uint32_t ExpansionROMBaseAddress;
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uint8_t CapabilitiesPointer;
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uint8_t Reserved0;
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uint16_t Reserved1;
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uint32_t Reserved2;
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uint8_t InterruptLine;
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uint8_t InterruptPin;
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uint8_t MinGrant;
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uint8_t MaxLatency;
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} __attribute__((packed)) PCIHeader0;
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typedef struct
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{
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PCIDeviceHeader Header;
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uint32_t BAR0;
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uint32_t BAR1;
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uint8_t PrimaryBusNumber;
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uint8_t SecondaryBusNumber;
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uint8_t SubordinateBusNumber;
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uint8_t SecondaryLatencyTimer;
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uint8_t IOBase;
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uint8_t IOLimit;
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uint16_t SecondaryStatus;
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uint16_t MemoryBase;
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uint16_t MemoryLimit;
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uint16_t PrefetchableMemoryBase;
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uint16_t PrefetchableMemoryLimit;
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uint32_t PrefetchableMemoryBaseUpper32;
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uint32_t PrefetchableMemoryLimitUpper32;
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uint16_t IOBaseUpper16;
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uint16_t IOLimitUpper16;
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uint8_t CapabilitiesPointer;
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uint8_t Reserved0;
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uint16_t Reserved1;
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uint32_t ExpansionROMBaseAddress;
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uint8_t InterruptLine;
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uint8_t InterruptPin;
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uint16_t BridgeControl;
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} __attribute__((packed)) PCIHeader1;
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typedef struct
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{
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PCIDeviceHeader Header;
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uint32_t CardbusSocketRegistersBaseAddress;
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uint8_t CapabilitiesPointer;
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uint8_t Reserved0;
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uint16_t SecondaryStatus;
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uint8_t PCIbusNumber;
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uint8_t CardbusBusNumber;
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uint8_t SubordinateBusNumber;
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uint8_t CardbusLatencyTimer;
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uint32_t MemoryBase0;
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uint32_t MemoryLimit0;
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uint32_t MemoryBase1;
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uint32_t MemoryLimit1;
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uint32_t IOBase0;
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uint32_t IOLimit0;
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uint32_t IOBase1;
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uint32_t IOLimit1;
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uint8_t InterruptLine;
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uint8_t InterruptPin;
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uint16_t BridgeControl;
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uint16_t SubsystemVendorID;
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uint16_t SubsystemID;
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uint32_t LegacyBaseAddress;
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} __attribute__((packed)) PCIHeader2;
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typedef struct
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{
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uint64_t BaseAddress;
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uint16_t PCISegGroup;
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uint8_t StartBus;
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uint8_t EndBus;
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uint32_t Reserved;
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} __attribute__((packed)) DeviceConfig;
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typedef struct
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{
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PCIDeviceHeader *Header;
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DeviceConfig *Config;
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uint32_t Bus;
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uint32_t Device;
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uint32_t Function;
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} __attribute__((packed)) PCIDevice;
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typedef struct
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{
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PCIDevice *Device;
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/* PCIArray */ void *Next;
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} __attribute__((packed)) PCIArray;
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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PCIArray *GetPCIDevices(uint16_t Vendors[], uint16_t Devices[]);
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void InitializePCI(PCIDevice *Device);
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uint32_t GetBAR(uint8_t Index, PCIDevice *Device);
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uint8_t iLine(PCIDevice *Device);
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uint8_t iPin(PCIDevice *Device);
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#ifdef __cplusplus
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}
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#endif
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#endif // !__FENNIX_API_PCI_H__
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