mirror of
https://github.com/EnderIce2/Fennix.git
synced 2025-07-02 19:09:16 +00:00
feat(kernel/drivers): migrate drivers to the kernel
make the drivers builtin Signed-off-by: EnderIce2 <enderice2@protonmail.com>
This commit is contained in:
210
Kernel/drivers/audio/hda/hda.cpp
Normal file
210
Kernel/drivers/audio/hda/hda.cpp
Normal file
@ -0,0 +1,210 @@
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/*
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This file is part of Fennix Kernel.
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Fennix Kernel is free software: you can redistribute it and/or
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||||
modify it under the terms of the GNU General Public License as
|
||||
published by the Free Software Foundation, either version 3 of
|
||||
the License, or (at your option) any later version.
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||||
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||||
Fennix Kernel is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
GNU General Public License for more details.
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||||
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You should have received a copy of the GNU General Public License
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||||
along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <driver.hpp>
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#include <cpu.hpp>
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#include <pci.hpp>
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#include "hda.hpp"
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extern Driver::Manager *DriverManager;
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extern PCI::Manager *PCIManager;
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namespace Driver::HighDefinitionAudio
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{
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dev_t DriverID;
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class HDADevice
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{
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private:
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PCI::PCIHeader0 *Header;
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bool Initialized = false;
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ControllerRegisters *CTL;
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uint32_t *CORB;
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uint64_t *RIRB;
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public:
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bool IsInitialized() { return Initialized; }
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size_t write(uint8_t *, size_t Size)
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{
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return Size;
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}
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int ioctl(AudioIoctl, void *)
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{
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return 0;
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}
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void OnInterruptReceived(CPU::TrapFrame *)
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{
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}
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void Panic()
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{
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}
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HDADevice(PCI::PCIHeader0 *_Header)
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: Header(_Header),
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CORB((uint32_t *)(uintptr_t)DriverManager->AllocateMemory(DriverID, 1)),
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RIRB((uint64_t *)DriverManager->AllocateMemory(DriverID, 1))
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{
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CTL = (ControllerRegisters *)(uintptr_t)Header->BAR0;
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fixme("Unimplemented HDA driver");
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return;
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Initialized = true;
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}
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~HDADevice()
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{
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if (!Initialized)
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return;
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}
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};
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std::unordered_map<dev_t, HDADevice *> Drivers;
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int Ioctl(struct Inode *Node, unsigned long Request, void *Argp)
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{
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return Drivers[Node->GetMinor()]->ioctl((AudioIoctl)Request, Argp);
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}
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ssize_t Write(struct Inode *Node, const void *Buffer, size_t Size, off_t Offset)
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{
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return Drivers[Node->GetMinor()]->write((uint8_t *)Buffer, Size);
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}
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const struct InodeOperations ops = {
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.Lookup = nullptr,
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.Create = nullptr,
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.Remove = nullptr,
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.Rename = nullptr,
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.Read = nullptr,
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.Write = Write,
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.Truncate = nullptr,
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.Open = nullptr,
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.Close = nullptr,
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.Ioctl = Ioctl,
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.ReadDir = nullptr,
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.MkDir = nullptr,
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.RmDir = nullptr,
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.SymLink = nullptr,
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.ReadLink = nullptr,
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.Seek = nullptr,
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.Stat = nullptr,
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};
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std::list<PCI::PCIDevice> Devices;
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int Entry()
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{
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for (auto &&dev : Devices)
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{
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PCI::PCIHeader0 *hdr0 = (PCI::PCIHeader0 *)dev.Header;
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uint8_t type = hdr0->BAR0 & 1;
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if (type == 1)
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{
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debug("Device %x:%x.%d BAR0 is I/O.",
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hdr0->Header.VendorID,
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hdr0->Header.DeviceID,
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hdr0->Header.ProgIF);
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continue;
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}
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PCIManager->InitializeDevice(dev, KernelPageTable);
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HDADevice *driver = new HDADevice((PCI::PCIHeader0 *)dev.Header);
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if (driver->IsInitialized())
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{
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dev_t ret = v0::RegisterDevice(DriverID, AUDIO_TYPE_PCM, &ops);
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Drivers[ret] = driver;
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}
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}
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if (Drivers.empty())
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{
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debug("No valid HDA device found.");
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return -EINVAL;
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}
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return 0;
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}
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int Final()
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{
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for (auto &&dev : Drivers)
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{
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dev_t ret = dev.first;
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v0::UnregisterDevice(DriverID, ret);
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delete dev.second;
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}
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return 0;
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}
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int Panic()
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{
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for (auto &&i : Drivers)
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i.second->Panic();
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return 0;
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}
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int Probe()
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{
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Devices = PCIManager->FindPCIDevice(
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{
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0x8086, /* Intel */
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0x15AD, /* VMware */
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},
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{
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0x9D71, /* Sunrise Point-LP HD Audio */
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0x2668, /* ICH6 */
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0x293E, /* ICH9 */
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});
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if (Devices.empty())
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{
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trace("No HDA device found.");
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return -ENODEV;
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}
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for (auto &&dev : Devices)
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{
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PCI::PCIHeader0 *PCIBaseAddress = (PCI::PCIHeader0 *)dev.Header;
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uint32_t PCIBAR0 = PCIBaseAddress->BAR0;
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uint8_t Type = PCIBAR0 & 1;
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if (Type == 1)
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{
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debug("Device %x:%x.%d BAR0 is I/O.",
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PCIBaseAddress->Header.VendorID,
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PCIBaseAddress->Header.DeviceID,
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PCIBaseAddress->Header.ProgIF);
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continue;
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}
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}
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return 0;
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}
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REGISTER_BUILTIN_DRIVER(hda,
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"Intel High Definition Audio Driver",
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"enderice2",
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1, 0, 0,
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Entry,
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Final,
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Panic,
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Probe);
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}
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627
Kernel/drivers/audio/hda/hda.hpp
Normal file
627
Kernel/drivers/audio/hda/hda.hpp
Normal file
@ -0,0 +1,627 @@
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/*
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This file is part of Fennix Kernel.
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||||
|
||||
Fennix Kernel is free software: you can redistribute it and/or
|
||||
modify it under the terms of the GNU General Public License as
|
||||
published by the Free Software Foundation, either version 3 of
|
||||
the License, or (at your option) any later version.
|
||||
|
||||
Fennix Kernel is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <types.h>
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struct StreamDescriptor
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{
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/** Control */
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uint32_t CTL : 24;
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/** Status */
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uint8_t STS;
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/** Link Position in Current Buffer */
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uint32_t LPIB;
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/** Cyclic Buffer Length */
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uint32_t CBL;
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/** Last Valid Index */
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uint16_t LVI;
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/** Reserved */
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uint8_t Rsvd0[2];
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/** FIFO Size */
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uint16_t FIFOD;
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/** Format */
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uint16_t FMT;
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/** Reserved */
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uint8_t Rsvd1[4];
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/** Buffer Descriptor List Pointer - Lower */
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uint32_t BDPL;
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/** Buffer Descriptor List Pointer - Upper */
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uint32_t BDPU;
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} __attribute__((packed));
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struct ControllerRegisters
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{
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uint16_t GCAP;
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uint8_t VMIN;
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uint8_t VMJ;
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uint16_t OUTPAY;
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uint16_t INPAY;
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uint32_t GCTL;
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uint16_t WAKEEN;
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uint16_t WAKESTS;
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uint16_t GSTS;
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uint8_t Rsvd0[6];
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uint16_t OUTSTRMPAY;
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uint16_t INSTRMPAY;
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uint8_t Rsvd1[4];
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uint32_t INTCTL;
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uint32_t INTSTS;
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uint8_t Rsvd2[8];
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uint32_t WALCLK;
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uint8_t Rsvd3[4];
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uint32_t SSYNC;
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uint8_t Rsvd4[4];
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uint32_t CORBLBASE;
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uint32_t CORBUBASE;
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uint16_t CORBWP;
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uint16_t CORBRP;
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uint8_t CORBCTL;
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uint8_t CORBSTS;
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uint8_t CORBSIZE;
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uint8_t Rsvd5;
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uint32_t RIRBLBASE;
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uint32_t RIRBUBASE;
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uint16_t RIRBWP;
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uint16_t RINTCNT;
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uint8_t RIRBCTL;
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uint8_t RIRBSTS;
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uint8_t RIRBSIZE;
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uint8_t Rsvd6;
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uint32_t ICOI;
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uint32_t ICII;
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uint16_t ICIS;
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uint8_t Rsvd7[6];
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uint32_t DPIBLBASE;
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uint32_t DPIBUBASE;
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uint8_t Rsvd8[8];
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StreamDescriptor SD[];
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} __attribute__((packed));
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/* Not working as expected */
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struct __ControllerRegisters
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{
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/** Global Capabilities */
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union
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{
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struct
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{
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/** 64 Bit Address Supported
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*
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* 0 = 32-bit addressing
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* 1 = 64-bit addressing
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*/
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uint16_t _64OK : 1;
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/** Number of Serial Data Out Signals
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*
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* 00 = 1 SDO
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* 01 = 2 SDOs
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* 10 = 4 SDOs
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* 11 = Reserved
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*/
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uint16_t NSDO : 2;
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/** Number of Bidirectional Streams Supported
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*
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* 00000b = No bidirectional streams supported
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* 00001b = 1 bidirectional stream supported
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* ...
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* 11110b = 30 bidirectional streams supported
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*/
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uint16_t BSS : 5;
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/** Number of Input Streams Supported
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*
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* 0000b = No input streams supported
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* 0001b = 1 input stream supported
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* ...
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* 1111b = 15 input streams supported
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*/
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uint16_t ISS : 4;
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/** Number of Output Streams Supported
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*
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* 0000b = No output streams supported
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* 0001b = 1 output stream supported
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* ...
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* 1111b = 15 output streams supported
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*/
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uint16_t OSS : 4;
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} __attribute__((packed));
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uint16_t Raw;
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} GCAP;
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/** Minor Version */
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uint8_t VMIN;
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/** Major Version */
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uint8_t VMJ;
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||||
|
||||
/** Output Payload Capability
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||||
*
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||||
* 00h = 0 Words
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||||
* 01h = 1 Word payload
|
||||
* ...
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||||
* FFh = 255h Word payload
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||||
*/
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||||
uint16_t OUTPAY;
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||||
|
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/** Input Payload Capability
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||||
*
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||||
* 00h = 0 Words
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||||
* 01h = 1 Word payload
|
||||
* ...
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||||
* FFh = 255h Word payload
|
||||
*/
|
||||
uint16_t INPAY;
|
||||
|
||||
/** Global Control */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** Controller Reset
|
||||
*
|
||||
* 0 = Reset
|
||||
* 1 = Normal Operation
|
||||
*/
|
||||
uint32_t CRST : 1;
|
||||
|
||||
/** Flush Control
|
||||
*
|
||||
* 0 = Idle
|
||||
* 1 = Flush
|
||||
*/
|
||||
uint32_t FCNTRL : 1;
|
||||
|
||||
/** Reserved */
|
||||
uint32_t RsvdP0 : 6;
|
||||
|
||||
/** Accept Unsolicited Response Enable
|
||||
*
|
||||
* 0 = Disabled
|
||||
* 1 = Enabled
|
||||
*/
|
||||
uint32_t UNSOL : 1;
|
||||
|
||||
/** Reserved */
|
||||
uint32_t RsvdP1 : 23;
|
||||
} __attribute__((packed));
|
||||
uint32_t Raw;
|
||||
} GCTL;
|
||||
|
||||
/** Wake Enable */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** SDIN Wake Enable Flags */
|
||||
uint16_t SDIWEN : 15;
|
||||
|
||||
/** Reserved */
|
||||
uint16_t RsvdP0 : 1;
|
||||
} __attribute__((packed));
|
||||
uint16_t Raw;
|
||||
} WAKEEN;
|
||||
|
||||
/** Wake Status */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** SDIN State Change Status Flags */
|
||||
uint16_t SDIWAKE : 15;
|
||||
|
||||
/** Reserved */
|
||||
uint16_t RsvdZ0 : 1;
|
||||
} __attribute__((packed));
|
||||
uint16_t Raw;
|
||||
} WAKESTS;
|
||||
|
||||
/** Global Status */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint16_t RsvdZ0 : 1;
|
||||
uint16_t FSTS : 1;
|
||||
uint16_t RsvdZ1 : 14;
|
||||
} __attribute__((packed));
|
||||
uint16_t Raw;
|
||||
} GSTS;
|
||||
|
||||
/** Reserved */
|
||||
uint8_t Rsvd0[6];
|
||||
|
||||
/** Output Stream Payload Capability */
|
||||
uint16_t OUTSTRMPAY;
|
||||
|
||||
/** Input Stream Payload Capability */
|
||||
uint16_t INSTRMPAY;
|
||||
|
||||
/** Reserved */
|
||||
uint8_t Rsvd1[4];
|
||||
|
||||
/** Interrupt Control */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** Stream Interrupt Enable
|
||||
*
|
||||
* Bit 0 = Input Stream 0
|
||||
* Bit 1 = Input Stream 1
|
||||
* Bit 2 = Output Stream 0
|
||||
* Bit 3 = Output Stream 1
|
||||
* Bit 4 = Output Stream 2
|
||||
* Bit 5 = Bidirectional Stream 0
|
||||
* Bits 6-28 = Reserved
|
||||
*/
|
||||
uint32_t SIE : 30;
|
||||
|
||||
/** Controller Interrupt Enable */
|
||||
uint32_t CIE : 1;
|
||||
|
||||
/** Global Interrupt Enable */
|
||||
uint32_t GIE : 1;
|
||||
} __attribute__((packed));
|
||||
uint32_t Raw;
|
||||
} INTCTL;
|
||||
|
||||
/** Interrupt Status */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** Stream Interrupt Status */
|
||||
uint32_t SIS : 30;
|
||||
|
||||
/** Controller Interrupt Status */
|
||||
uint32_t CIS : 1;
|
||||
|
||||
/** Global Interrupt Status */
|
||||
uint32_t GIS : 1;
|
||||
} __attribute__((packed));
|
||||
uint32_t Raw;
|
||||
} INTSTS;
|
||||
|
||||
/** Reserved */
|
||||
uint8_t Rsvd2[8];
|
||||
|
||||
/** Wall Clock Counter */
|
||||
uint32_t WALCLK;
|
||||
|
||||
/** Reserved */
|
||||
uint8_t Rsvd3[4];
|
||||
|
||||
/** Stream Synchronization */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** Stream Synchronization Bits */
|
||||
uint32_t SSYNC : 30;
|
||||
|
||||
/** Reserved */
|
||||
uint32_t RsvdP0 : 2;
|
||||
} __attribute__((packed));
|
||||
uint32_t Raw;
|
||||
} SSYNC;
|
||||
|
||||
/** Reserved */
|
||||
uint8_t Rsvd4[4];
|
||||
|
||||
/** CORB Lower Base Address */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** CORB Lower Base Unimplemented Bits */
|
||||
uint32_t Unimplemented : 7;
|
||||
|
||||
/** CORB Lower Base Address */
|
||||
uint32_t CORBLBASE : 25;
|
||||
} __attribute__((packed));
|
||||
uint32_t Raw;
|
||||
} CORBLBASE;
|
||||
|
||||
/** CORB Upper Base Address */
|
||||
uint32_t CORBUBASE;
|
||||
|
||||
/** CORB Write Pointer */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** CORB Write Pointer */
|
||||
uint16_t CORBWP : 8;
|
||||
|
||||
/** Reserved */
|
||||
uint16_t RsvdP0 : 8;
|
||||
} __attribute__((packed));
|
||||
uint16_t Raw;
|
||||
} CORBWP;
|
||||
|
||||
/** CORB Read Pointer */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** CORB Read Pointer */
|
||||
uint16_t CORBRP : 8;
|
||||
|
||||
/** Reserved */
|
||||
uint16_t RsvdP0 : 7;
|
||||
|
||||
/** CORB Read Pointer Reset */
|
||||
uint16_t CORBRPRST : 1;
|
||||
} __attribute__((packed));
|
||||
uint16_t Raw;
|
||||
} CORBRP;
|
||||
|
||||
/** CORB Control */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** CORB Memory Error Interrupt Enable */
|
||||
uint8_t CMEIE : 1;
|
||||
|
||||
/** Enable CORB DMA Engine
|
||||
*
|
||||
* 0 = DMA Stop
|
||||
* 1 = DMA Run
|
||||
*
|
||||
* @note Must read the value back.
|
||||
*/
|
||||
uint8_t CORBRUN : 1;
|
||||
|
||||
/** Reserved */
|
||||
uint8_t RsvdP0 : 6;
|
||||
} __attribute__((packed));
|
||||
uint8_t Raw;
|
||||
} CORBCTL;
|
||||
|
||||
/** CORB Status */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** CORB Memory Error Indication */
|
||||
uint8_t CMEI : 1;
|
||||
|
||||
/** Reserved */
|
||||
uint8_t RsvdZ0 : 7;
|
||||
} __attribute__((packed));
|
||||
uint8_t Raw;
|
||||
} CORBSTS;
|
||||
|
||||
/** CORB Size */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** CORB Size
|
||||
*
|
||||
* 00b = 2 entries
|
||||
* 01b = 16 entries
|
||||
* 10b = 256 entries
|
||||
* 11b = Reserved
|
||||
*/
|
||||
uint8_t CORBSIZE : 2;
|
||||
|
||||
/** Reserved */
|
||||
uint8_t RsvdP0 : 2;
|
||||
|
||||
/** CORB Size Capability
|
||||
*
|
||||
* 0001b = 2 entries
|
||||
* 0010b = 16 entries
|
||||
* 0100b = 256 entries
|
||||
* 1000b = Reserved
|
||||
*/
|
||||
uint8_t CORBSZCAP : 4;
|
||||
} __attribute__((packed));
|
||||
uint8_t Raw;
|
||||
} CORBSIZE;
|
||||
|
||||
/** Reserved */
|
||||
uint8_t Rsvd5;
|
||||
|
||||
/** RIRB Lower Base Address */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** RIRB Lower Base Unimplemented Bits */
|
||||
uint32_t Unimplemented : 7;
|
||||
|
||||
/** RIRB Lower Base Address */
|
||||
uint32_t RIRBLBASE : 25;
|
||||
} __attribute__((packed));
|
||||
uint32_t Raw;
|
||||
} RIRBLBASE;
|
||||
|
||||
/** RIRB Upper Base Address */
|
||||
uint32_t RIRBUBASE;
|
||||
|
||||
/** RIRB Write Pointer */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** RIRB Write Pointer */
|
||||
uint16_t RIRBWP : 8;
|
||||
|
||||
/** Reserved */
|
||||
uint16_t RsvdP0 : 7;
|
||||
|
||||
/** RIRB Write Pointer Reset */
|
||||
uint16_t RIRBWPRST : 1;
|
||||
} __attribute__((packed));
|
||||
uint16_t Raw;
|
||||
} RIRBWP;
|
||||
|
||||
/** Response Interrupt Count */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** N Response Interrupt Count
|
||||
*
|
||||
* 00000001b = 1 Response sent to RIRB
|
||||
* ...
|
||||
* 11111111b = 255 Responses sent to RIRB
|
||||
* 00000000b = 256 Response sent to RIRB
|
||||
*/
|
||||
uint16_t RINTCNT : 8;
|
||||
|
||||
/** Reserved */
|
||||
uint16_t RsvdP0 : 8;
|
||||
} __attribute__((packed));
|
||||
uint16_t Raw;
|
||||
} RINTCNT;
|
||||
|
||||
/** RIRB Control */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** Response Interrupt Control
|
||||
*
|
||||
* 0 = Disable Interrupt
|
||||
* 1 = Generate an interrupt after N responses are sent to the RIRB
|
||||
*/
|
||||
uint8_t RINTCTL : 1;
|
||||
|
||||
/** RIRB DMA Enable
|
||||
*
|
||||
* 0 = DMA Stop
|
||||
* 1 = DMA Run
|
||||
*/
|
||||
uint8_t RIRBDMAEN : 1;
|
||||
|
||||
/** Response Overrun Interrupt Control */
|
||||
uint8_t RIRBOIC : 1;
|
||||
|
||||
/** Reserved */
|
||||
uint8_t RsvdP0 : 5;
|
||||
} __attribute__((packed));
|
||||
uint8_t Raw;
|
||||
} RIRBCTL;
|
||||
|
||||
/** RIRB Status */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** Response Interrupt */
|
||||
uint8_t RINTFL : 1;
|
||||
|
||||
/** Reserved */
|
||||
uint8_t RsvdZ0 : 1;
|
||||
|
||||
/** Response Overrun Interrupt Status */
|
||||
uint8_t RIRBOIS : 1;
|
||||
|
||||
/** Reserved */
|
||||
uint8_t RsvdZ1 : 5;
|
||||
} __attribute__((packed));
|
||||
uint8_t Raw;
|
||||
} RIRBSTS;
|
||||
|
||||
/** RIRB Size */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** RIRB Size
|
||||
*
|
||||
* 00b = 2 entries
|
||||
* 01b = 16 entries
|
||||
* 10b = 256 entries
|
||||
* 11b = Reserved
|
||||
*/
|
||||
uint8_t RIRBSIZE : 2;
|
||||
|
||||
/** Reserved */
|
||||
uint8_t RsvdP0 : 2;
|
||||
|
||||
/** RIRB Size Capability
|
||||
*
|
||||
* 0001b = 2 entries
|
||||
* 0010b = 16 entries
|
||||
* 0100b = 256 entries
|
||||
* 1000b = Reserved
|
||||
*/
|
||||
uint8_t RIRBSZCAP : 4;
|
||||
} __attribute__((packed));
|
||||
uint8_t Raw;
|
||||
} RIRBSIZE;
|
||||
|
||||
/** Reserved */
|
||||
uint8_t Rsvd6;
|
||||
|
||||
/** Immediate Command Output Interface */
|
||||
uint32_t ICOI;
|
||||
|
||||
/** Immediate Command Input Interface */
|
||||
uint32_t ICII;
|
||||
|
||||
/** Immediate Command Status */
|
||||
uint16_t ICIS;
|
||||
|
||||
/** Reserved */
|
||||
uint8_t Rsvd7[6];
|
||||
|
||||
/** DMA Position Buffer Lower Base */
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
/** DMA Position Buffer Enable */
|
||||
uint32_t DPBEN : 1;
|
||||
|
||||
/** Reserved */
|
||||
uint32_t RsvdZ0 : 6;
|
||||
|
||||
/** DMA Position Lower Base Address */
|
||||
uint32_t DPLBASE : 25;
|
||||
} __attribute__((packed));
|
||||
uint32_t Raw;
|
||||
} DPIBLBASE;
|
||||
|
||||
/** DMA Position Buffer Upper Base */
|
||||
uint32_t DPIBUBASE;
|
||||
|
||||
/** Reserved */
|
||||
uint8_t Rsvd8[8];
|
||||
|
||||
StreamDescriptor SD[];
|
||||
} __attribute__((packed));
|
||||
Reference in New Issue
Block a user