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Merge remote-tracking branch 'Kernel/memory-test' into Kernel-memory-test
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EnderIce2
274
Kernel/Core/CPU.cpp
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274
Kernel/Core/CPU.cpp
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#include <cpu.hpp>
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#include <memory.hpp>
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#include <convert.h>
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#include <debug.h>
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#include "../kernel.h"
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namespace CPU
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{
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char *Vendor()
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{
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static char Vendor[13];
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#if defined(__amd64__)
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uint32_t rax, rbx, rcx, rdx;
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x64::cpuid(0x0, &rax, &rbx, &rcx, &rdx);
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memcpy(Vendor + 0, &rbx, 4);
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memcpy(Vendor + 4, &rdx, 4);
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memcpy(Vendor + 8, &rcx, 4);
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#elif defined(__i386__)
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uint32_t rax, rbx, rcx, rdx;
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x32::cpuid(0x0, &rax, &rbx, &rcx, &rdx);
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memcpy(Vendor + 0, &rbx, 4);
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memcpy(Vendor + 4, &rdx, 4);
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memcpy(Vendor + 8, &rcx, 4);
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#elif defined(__aarch64__)
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asmv("mrs %0, MIDR_EL1"
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: "=r"(Vendor[0]));
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#endif
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return Vendor;
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}
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char *Name()
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{
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static char Name[49];
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#if defined(__amd64__)
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uint32_t rax, rbx, rcx, rdx;
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x64::cpuid(0x80000002, &rax, &rbx, &rcx, &rdx);
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memcpy(Name + 0, &rax, 4);
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memcpy(Name + 4, &rbx, 4);
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memcpy(Name + 8, &rcx, 4);
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memcpy(Name + 12, &rdx, 4);
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x64::cpuid(0x80000003, &rax, &rbx, &rcx, &rdx);
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memcpy(Name + 16, &rax, 4);
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memcpy(Name + 20, &rbx, 4);
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memcpy(Name + 24, &rcx, 4);
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memcpy(Name + 28, &rdx, 4);
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x64::cpuid(0x80000004, &rax, &rbx, &rcx, &rdx);
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memcpy(Name + 32, &rax, 4);
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memcpy(Name + 36, &rbx, 4);
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memcpy(Name + 40, &rcx, 4);
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memcpy(Name + 44, &rdx, 4);
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#elif defined(__i386__)
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uint32_t rax, rbx, rcx, rdx;
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x32::cpuid(0x80000002, &rax, &rbx, &rcx, &rdx);
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memcpy(Name + 0, &rax, 4);
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memcpy(Name + 4, &rbx, 4);
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memcpy(Name + 8, &rcx, 4);
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memcpy(Name + 12, &rdx, 4);
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x32::cpuid(0x80000003, &rax, &rbx, &rcx, &rdx);
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memcpy(Name + 16, &rax, 4);
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memcpy(Name + 20, &rbx, 4);
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memcpy(Name + 24, &rcx, 4);
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memcpy(Name + 28, &rdx, 4);
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x32::cpuid(0x80000004, &rax, &rbx, &rcx, &rdx);
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memcpy(Name + 32, &rax, 4);
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memcpy(Name + 36, &rbx, 4);
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memcpy(Name + 40, &rcx, 4);
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memcpy(Name + 44, &rdx, 4);
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#elif defined(__aarch64__)
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asmv("mrs %0, MIDR_EL1"
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: "=r"(Name[0]));
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#endif
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return Name;
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}
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char *Hypervisor()
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{
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static char Hypervisor[13];
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#if defined(__amd64__)
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uint32_t rax, rbx, rcx, rdx;
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x64::cpuid(0x40000000, &rax, &rbx, &rcx, &rdx);
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memcpy(Hypervisor + 0, &rbx, 4);
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memcpy(Hypervisor + 4, &rcx, 4);
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memcpy(Hypervisor + 8, &rdx, 4);
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#elif defined(__i386__)
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uint32_t rax, rbx, rcx, rdx;
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x64::cpuid(0x40000000, &rax, &rbx, &rcx, &rdx);
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memcpy(Hypervisor + 0, &rbx, 4);
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memcpy(Hypervisor + 4, &rcx, 4);
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memcpy(Hypervisor + 8, &rdx, 4);
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#elif defined(__aarch64__)
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asmv("mrs %0, MIDR_EL1"
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: "=r"(Hypervisor[0]));
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#endif
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return Hypervisor;
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}
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bool Interrupts(InterruptsType Type)
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{
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switch (Type)
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{
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case Check:
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{
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#if defined(__amd64__)
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uint64_t rflags;
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asmv("pushfq");
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asmv("popq %0"
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: "=r"(rflags));
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return rflags & (1 << 9);
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#elif defined(__i386__)
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uint32_t rflags;
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asmv("pushfl");
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asmv("popl %0"
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: "=r"(rflags));
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return rflags & (1 << 9);
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#elif defined(__aarch64__)
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uint64_t daif;
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asmv("mrs %0, daif"
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: "=r"(daif));
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return !(daif & (1 << 2));
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#endif
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}
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case Enable:
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("sti");
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#elif defined(__aarch64__)
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asmv("msr daifclr, #2");
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#endif
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return true;
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}
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case Disable:
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("cli");
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#elif defined(__aarch64__)
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asmv("msr daifset, #2");
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#endif
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return true;
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}
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}
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return false;
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}
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void *PageTable(void *PT)
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{
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#if defined(__amd64__)
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if (PT)
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asmv("movq %0, %%cr3"
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:
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: "r"(PT));
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else
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asmv("movq %%cr3, %0"
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: "=r"(PT));
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#elif defined(__i386__)
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if (PT)
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asmv("movl %0, %%cr3"
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:
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: "r"(PT));
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else
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asmv("movl %%cr3, %0"
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: "=r"(PT));
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#elif defined(__aarch64__)
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if (PT)
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asmv("msr ttbr0_el1, %0"
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:
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: "r"(PT));
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else
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asmv("mrs %0, ttbr0_el1"
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: "=r"(PT));
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#endif
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return PT;
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}
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void InitializeFeatures()
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{
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#if defined(__amd64__)
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static int BSP = 0;
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x64::CR0 cr0 = x64::readcr0();
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x64::CR4 cr4 = x64::readcr4();
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uint32_t rax, rbx, rcx, rdx;
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x64::cpuid(0x1, &rax, &rbx, &rcx, &rdx);
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if (rdx & x64::CPUID_FEAT_RDX_PGE)
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{
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debug("Enabling global pages support...");
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if (!BSP)
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KPrint("Global Pages is supported.");
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cr4.PGE = 1;
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}
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if (rdx & x64::CPUID_FEAT_RDX_SSE)
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{
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debug("Enabling SSE support...");
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if (!BSP)
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KPrint("SSE is supported.");
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cr0.EM = 0;
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cr0.MP = 1;
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cr4.OSFXSR = 1;
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cr4.OSXMMEXCPT = 1;
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}
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if (!BSP)
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KPrint("Enabling CPU cache.");
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cr0.NW = 0;
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cr0.CD = 0;
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cr0.WP = 1;
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x64::writecr0(cr0);
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debug("Enabling UMIP, SMEP & SMAP support...");
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x64::cpuid(0x1, &rax, &rbx, &rcx, &rdx);
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if (rdx & x64::CPUID_FEAT_RDX_UMIP)
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{
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if (!BSP)
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KPrint("UMIP is supported.");
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fixme("Not going to enable UMIP.");
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// cr4.UMIP = 1;
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}
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if (rdx & x64::CPUID_FEAT_RDX_SMEP)
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{
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if (!BSP)
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KPrint("SMEP is supported.");
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fixme("Not going to enable SMEP.");
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// cr4.SMEP = 1;
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}
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if (rdx & x64::CPUID_FEAT_RDX_SMAP)
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{
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if (!BSP)
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KPrint("SMAP is supported.");
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fixme("Not going to enable SMAP.");
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// cr4.SMAP = 1;
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}
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if (strcmp(Hypervisor(), x86_CPUID_VENDOR_VIRTUALBOX) != 0 &&
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strcmp(Hypervisor(), x86_CPUID_VENDOR_TCG) != 0)
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x64::writecr4(cr4);
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else
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{
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if (!BSP)
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{
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if (strcmp(Hypervisor(), x86_CPUID_VENDOR_VIRTUALBOX) != 0)
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KPrint("VirtualBox detected. Not using UMIP, SMEP & SMAP");
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else if (strcmp(Hypervisor(), x86_CPUID_VENDOR_TCG) != 0)
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KPrint("QEMU (TCG) detected. Not using UMIP, SMEP & SMAP");
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}
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}
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debug("Enabling PAT support...");
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x64::wrmsr(x64::MSR_CR_PAT, 0x6 | (0x0 << 8) | (0x1 << 16));
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if (!BSP++)
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trace("Features for BSP initialized.");
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#elif defined(__i386__)
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#elif defined(__aarch64__)
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#endif
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}
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uint64_t Counter()
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{
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// TODO: Get the counter from the x2APIC or any other timer that is available. (TSC is not available on all CPUs)
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#if defined(__amd64__)
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uint64_t counter;
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asmv("rdtsc"
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: "=A"(counter));
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return counter;
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#elif defined(__i386__)
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return 0;
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#elif defined(__aarch64__)
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uint64_t counter;
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asmv("mrs %0, cntvct_el0"
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: "=r"(counter));
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return counter;
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#endif
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}
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}
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