From aa6b6d0285aad9c64d2c6729f09cafc5f2c93a56 Mon Sep 17 00:00:00 2001
From: Alex <enderice2@users.noreply.github.com>
Date: Wed, 8 Mar 2023 05:47:40 +0200
Subject: [PATCH] Updated PCI header

---
 include/pci.h | 68 ++++++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 62 insertions(+), 6 deletions(-)

diff --git a/include/pci.h b/include/pci.h
index b0e711e1..07512592 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -55,18 +55,74 @@ struct PCIHeader0
     uint32_t BAR3;
     uint32_t BAR4;
     uint32_t BAR5;
-    uint32_t CardbusCISPtr;
+    uint32_t CardbusCISPointer;
     uint16_t SubsystemVendorID;
     uint16_t SubsystemID;
-    uint32_t ExpansionROMBaseAddr;
-    uint8_t CapabilitiesPtr;
-    uint8_t Rsv0;
-    uint16_t Rsv1;
-    uint32_t Rsv2;
+    uint32_t ExpansionROMBaseAddress;
+    uint8_t CapabilitiesPointer;
+    uint8_t Reserved0;
+    uint16_t Reserved1;
+    uint32_t Reserved2;
     uint8_t InterruptLine;
     uint8_t InterruptPin;
     uint8_t MinGrant;
     uint8_t MaxLatency;
 };
 
+struct PCIHeader1
+{
+    PCIDeviceHeader Header;
+    uint32_t BAR0;
+    uint32_t BAR1;
+    uint8_t PrimaryBusNumber;
+    uint8_t SecondaryBusNumber;
+    uint8_t SubordinateBusNumber;
+    uint8_t SecondaryLatencyTimer;
+    uint8_t IOBase;
+    uint8_t IOLimit;
+    uint16_t SecondaryStatus;
+    uint16_t MemoryBase;
+    uint16_t MemoryLimit;
+    uint16_t PrefetchableMemoryBase;
+    uint16_t PrefetchableMemoryLimit;
+    uint32_t PrefetchableMemoryBaseUpper32;
+    uint32_t PrefetchableMemoryLimitUpper32;
+    uint16_t IOBaseUpper16;
+    uint16_t IOLimitUpper16;
+    uint8_t CapabilitiesPointer;
+    uint8_t Reserved0;
+    uint16_t Reserved1;
+    uint32_t ExpansionROMBaseAddress;
+    uint8_t InterruptLine;
+    uint8_t InterruptPin;
+    uint16_t BridgeControl;
+};
+
+struct PCIHeader2
+{
+    PCIDeviceHeader Header;
+    uint32_t CardbusSocketRegistersBaseAddress;
+    uint8_t CapabilitiesPointer;
+    uint8_t Reserved0;
+    uint16_t SecondaryStatus;
+    uint8_t PCIbusNumber;
+    uint8_t CardbusBusNumber;
+    uint8_t SubordinateBusNumber;
+    uint8_t CardbusLatencyTimer;
+    uint32_t MemoryBase0;
+    uint32_t MemoryLimit0;
+    uint32_t MemoryBase1;
+    uint32_t MemoryLimit1;
+    uint32_t IOBase0;
+    uint32_t IOLimit0;
+    uint32_t IOBase1;
+    uint32_t IOLimit1;
+    uint8_t InterruptLine;
+    uint8_t InterruptPin;
+    uint16_t BridgeControl;
+    uint16_t SubsystemVendorID;
+    uint16_t SubsystemID;
+    uint32_t LegacyBaseAddress;
+};
+
 #endif // !__FENNIX_API_PCI_H__