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356
Kernel/arch/i386/cpu/apic.hpp
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356
Kernel/arch/i386/cpu/apic.hpp
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/*
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This file is part of Fennix Kernel.
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Fennix Kernel is free software: you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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Fennix Kernel is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef __FENNIX_KERNEL_APIC_H__
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#define __FENNIX_KERNEL_APIC_H__
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#include <types.h>
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#include <ints.hpp>
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#include <cpu.hpp>
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namespace APIC
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{
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enum APICRegisters
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{
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// source from: https://github.com/pdoane/osdev/blob/master/intr/local_apic.c
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APIC_ID = 0x20, // Local APIC ID
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APIC_VER = 0x30, // Local APIC Version
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APIC_TPR = 0x80, // Task Priority
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APIC_APR = 0x90, // Arbitration Priority
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APIC_PPR = 0xA0, // Processor Priority
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APIC_EOI = 0xB0, // EOI
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APIC_RRD = 0xC0, // Remote Read
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APIC_LDR = 0xD0, // Logical Destination
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APIC_DFR = 0xE0, // Destination Format
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APIC_SVR = 0xF0, // Spurious Interrupt Vector
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APIC_ISR = 0x100, // In-Service (8 registers)
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APIC_TMR = 0x180, // Trigger Mode (8 registers)
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APIC_IRR = 0x200, // Interrupt Request (8 registers)
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APIC_ESR = 0x280, // Error Status
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APIC_ICRLO = 0x300, // Interrupt Command
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APIC_ICRHI = 0x310, // Interrupt Command [63:32]
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APIC_TIMER = 0x320, // LVT Timer
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APIC_THERMAL = 0x330, // LVT Thermal Sensor
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APIC_PERF = 0x340, // LVT Performance Counter
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APIC_LINT0 = 0x350, // LVT LINT0
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APIC_LINT1 = 0x360, // LVT LINT1
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APIC_ERROR = 0x370, // LVT Error
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APIC_TICR = 0x380, // Initial Count (for Timer)
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APIC_TCCR = 0x390, // Current Count (for Timer)
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APIC_TDCR = 0x3E0, // Divide Configuration (for Timer)
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};
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enum IOAPICRegisters
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{
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GetIOAPICVersion = 0x1
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};
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enum IOAPICFlags
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{
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ActiveHighLow = 2,
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EdgeLevel = 8
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};
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enum APICDeliveryMode
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{
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Fixed = 0b000,
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LowestPriority = 0b001, /* Reserved */
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SMI = 0b010,
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APIC_DELIVERY_MODE_RESERVED0 = 0b011, /* Reserved */
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NMI = 0b100,
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INIT = 0b101,
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Startup = 0b110,
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ExtINT = 0b111 /* Reserved */
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};
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enum APICDestinationMode
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{
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Physical = 0b0,
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Logical = 0b1
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};
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enum APICDeliveryStatus
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{
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Idle = 0b0,
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SendPending = 0b1
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};
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enum APICLevel
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{
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DeAssert = 0b0,
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Assert = 0b1
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};
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enum APICTriggerMode
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{
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Edge = 0b0,
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Level = 0b1
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};
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enum APICDestinationShorthand
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{
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NoShorthand = 0b00,
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Self = 0b01,
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AllIncludingSelf = 0b10,
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AllExcludingSelf = 0b11
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};
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enum LVTTimerDivide
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{
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DivideBy2 = 0b000,
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DivideBy4 = 0b001,
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DivideBy8 = 0b010,
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DivideBy16 = 0b011,
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DivideBy32 = 0b100,
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DivideBy64 = 0b101,
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DivideBy128 = 0b110,
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DivideBy1 = 0b111
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};
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enum LVTTimerMask
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{
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Unmasked = 0b0,
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Masked = 0b1
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};
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enum LVTTimerMode
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{
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OneShot = 0b00,
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Periodic = 0b01,
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TSCDeadline = 0b10
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};
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typedef union
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{
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struct
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{
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/** @brief Interrupt Vector */
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uint64_t Vector : 8;
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/** @brief Reserved */
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uint64_t Reserved0 : 4;
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/**
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* @brief Delivery Status
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*
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* 0: Idle
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* 1: Send Pending
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*/
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uint64_t DeliveryStatus : 1;
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/** @brief Reserved */
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uint64_t Reserved1 : 3;
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/**
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* @brief Mask
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*
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* 0: Not masked
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* 1: Masked
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*/
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uint64_t Mask : 1;
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/** @brief Timer Mode
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*
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* 0: One-shot
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* 1: Periodic
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* 2: TSC-Deadline
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*/
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uint64_t TimerMode : 1;
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/** @brief Reserved */
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uint64_t Reserved2 : 14;
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};
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uint64_t raw;
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} __packed LVTTimer;
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typedef union
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{
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struct
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{
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/** @brief Spurious Vector */
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uint64_t Vector : 8;
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/** @brief Enable or disable APIC software */
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uint64_t Software : 1;
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/** @brief Focus Processor Checking */
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uint64_t FocusProcessorChecking : 1;
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/** @brief Reserved */
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uint64_t Reserved : 2;
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/** @brief Disable EOI Broadcast */
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uint64_t DisableEOIBroadcast : 1;
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/** @brief Reserved */
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uint64_t Reserved1 : 19;
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};
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uint64_t raw;
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} __packed Spurious;
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typedef union
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{
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struct
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{
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/** @brief Interrupt Vector */
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uint64_t Vector : 8;
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/** @brief Delivery Mode */
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uint64_t DeliveryMode : 3;
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/** @brief Destination Mode
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*
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* 0: Physical
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* 1: Logical
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*/
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uint64_t DestinationMode : 1;
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/** @brief Delivery Status
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*
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* @note Reserved when in x2APIC mode
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*/
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uint64_t DeliveryStatus : 1;
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/** @brief Reserved */
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uint64_t Reserved0 : 1;
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/** @brief Level
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*
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* 0: Deassert
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* 1: Assert
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*/
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uint64_t Level : 1;
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/** @brief Trigger Mode
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*
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* 0: Edge
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* 1: Level
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*/
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uint64_t TriggerMode : 1;
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/** @brief Reserved */
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uint64_t Reserved1 : 2;
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/** @brief Destination Shorthand
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*
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* 0: No shorthand
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* 1: Self
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* 2: All including self
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* 3: All excluding self
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*/
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uint64_t DestinationShorthand : 2;
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/** @brief Reserved */
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uint64_t Reserved2 : 12;
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};
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uint64_t raw;
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} __packed InterruptCommandRegisterLow;
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typedef union
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{
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struct
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{
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/** @brief Reserved */
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uint64_t Reserved0 : 24;
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/** @brief Destination */
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uint64_t Destination : 8;
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};
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uint64_t raw;
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} __packed InterruptCommandRegisterHigh;
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typedef union
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{
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struct
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{
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/** @brief Interrupt Vector */
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uint64_t Vector : 8;
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/** @brief Delivery Mode */
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uint64_t DeliveryMode : 3;
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/** @brief Destination Mode
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*
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* 0: Physical
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* 1: Logical
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*/
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uint64_t DestinationMode : 1;
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/** @brief Delivery Status */
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uint64_t DeliveryStatus : 1;
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/** @brief Interrupt Input Pin Polarity
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*
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* 0: Active High
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* 1: Active Low
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*/
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uint64_t Polarity : 1;
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/** @brief Remote IRR */
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uint64_t RemoteIRR : 1;
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/** @brief Trigger Mode
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*
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* 0: Edge
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* 1: Level
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*/
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uint64_t TriggerMode : 1;
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/** @brief Mask */
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uint64_t Mask : 1;
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/** @brief Reserved */
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uint64_t Reserved0 : 15;
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/** @brief Reserved */
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uint64_t Reserved1 : 24;
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/** @brief Destination */
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uint64_t DestinationID : 8;
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};
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struct
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{
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uint64_t Low;
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uint64_t High;
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} split;
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uint64_t raw;
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} __packed IOAPICRedirectEntry;
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typedef union
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{
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struct
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{
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uint64_t Version : 8;
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uint64_t Reserved : 8;
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uint64_t MaximumRedirectionEntry : 8;
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uint64_t Reserved2 : 8;
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};
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uint64_t raw;
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} __packed IOAPICVersion;
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class APIC
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{
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private:
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bool x2APICSupported = false;
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uint64_t APICBaseAddress = 0;
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public:
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decltype(x2APICSupported) &x2APIC = x2APICSupported;
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uint32_t Read(uint32_t Register);
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void Write(uint32_t Register, uint32_t Value);
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void IOWrite(uint64_t Base, uint32_t Register, uint32_t Value);
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uint32_t IORead(uint64_t Base, uint32_t Register);
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void EOI();
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void RedirectIRQs(int CPU = 0);
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void WaitForIPI();
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void IPI(uint8_t CPU, InterruptCommandRegisterLow icr);
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void SendInitIPI(uint8_t CPU);
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void SendStartupIPI(uint8_t CPU, uint64_t StartupAddress);
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uint32_t IOGetMaxRedirect(uint32_t APICID);
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void RawRedirectIRQ(uint16_t Vector, uint32_t GSI, uint16_t Flags, int CPU, int Status);
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void RedirectIRQ(int CPU, uint16_t IRQ, int Status);
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APIC(int Core);
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~APIC();
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};
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class Timer : public Interrupts::Handler
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{
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private:
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APIC *lapic;
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uint64_t Ticks = 0;
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void OnInterruptReceived(CPU::TrapFrame *Frame);
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public:
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uint64_t GetTicks() { return Ticks; }
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void OneShot(uint32_t Vector, uint64_t Miliseconds);
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Timer(APIC *apic);
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~Timer();
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};
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}
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#endif // !__FENNIX_KERNEL_APIC_H__
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