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Merge remote-tracking branch 'Kernel/master'
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386
Kernel/arch/amd64/cpu/apic.hpp
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386
Kernel/arch/amd64/cpu/apic.hpp
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/*
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This file is part of Fennix Kernel.
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Fennix Kernel is free software: you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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Fennix Kernel is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
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*/
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#ifndef __FENNIX_KERNEL_APIC_H__
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#define __FENNIX_KERNEL_APIC_H__
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#include <types.h>
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#include <ints.hpp>
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#include <cpu.hpp>
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namespace APIC
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{
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enum APICRegisters
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{
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/* APIC ID Register */
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APIC_ID = 0x20,
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/* APIC Version Register */
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APIC_VER = 0x30,
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/* Task Priority Register (TPR) */
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APIC_TPR = 0x80,
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/* Arbitration Priority Register (APR) */
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APIC_APR = 0x90,
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/* Processor Priority Register (PPR) */
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APIC_PPR = 0xA0,
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/* End of Interrupt Register (EOI) */
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APIC_EOI = 0xB0,
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/* Remote Read Register */
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APIC_RRD = 0xC0,
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/* Logical Destination Register (LDR) */
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APIC_LDR = 0xD0,
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/* Destination Format Register (DFR) */
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APIC_DFR = 0xE0,
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/* Spurious Interrupt Vector Register */
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APIC_SVR = 0xF0,
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/* In-Service Register (ISR) */
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APIC_ISR = 0x100,
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/* Trigger Mode Register (TMR) */
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APIC_TMR = 0x180,
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/* Interrupt Request Register (IRR) */
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APIC_IRR = 0x200,
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/* Error Status Register (ESR) */
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APIC_ESR = 0x280,
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/* Interrupt Command Register Low (bits 31:0) */
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APIC_ICRLO = 0x300,
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/* Interrupt Command Register High (bits 63:32) */
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APIC_ICRHI = 0x310,
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/* Timer Local Vector Table Entry */
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APIC_TIMER = 0x320,
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/* Thermal Local Vector Table Entry */
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APIC_THERMAL = 0x330,
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/* Performance Counter Local Vector Table Entry */
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APIC_PERF = 0x340,
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/* Local Interrupt 0 Vector Table Entry */
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APIC_LINT0 = 0x350,
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/* Local Interrupt 1 Vector Table Entry */
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APIC_LINT1 = 0x360,
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/* Error Vector Table Entry */
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APIC_ERROR = 0x370,
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/* Timer Initial Count Register */
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APIC_TICR = 0x380,
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/* Timer Current Count Register */
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APIC_TCCR = 0x390,
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/* Timer Divide Configuration Register */
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APIC_TDCR = 0x3E0,
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/* Extended APIC Feature Register */
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APIC_EFR = 0x400,
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/* Extended APIC Control Register */
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APIC_ECR = 0x410,
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/* Specific End of Interrupt Register (SEOI) */
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APIC_SEOI = 0x420,
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/* Interrupt Enable Registers (IER) */
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APIC_IER0 = 0x480,
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/* Extended Interrupt [3:0] Local Vector Table Registers */
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APIC_EILVT0 = 0x500,
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};
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enum IOAPICRegisters
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{
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GetIOAPICVersion = 0x1
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};
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enum IOAPICFlags
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{
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ActiveHighLow = 2,
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EdgeLevel = 8
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};
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enum APICMessageType
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{
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Fixed = 0b000,
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LowestPriority = 0b001, /* Reserved */
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SMI = 0b010,
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DeliveryMode = 0b011, /* Reserved */
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NMI = 0b100,
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INIT = 0b101,
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Startup = 0b110,
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ExtINT = 0b111 /* Reserved */
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};
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enum APICDestinationMode
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{
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Physical = 0b0,
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Logical = 0b1
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};
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enum APICDeliveryStatus
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{
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Idle = 0b0,
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SendPending = 0b1
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};
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enum APICLevel
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{
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DeAssert = 0b0,
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Assert = 0b1
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};
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enum APICTriggerMode
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{
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Edge = 0b0,
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Level = 0b1
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};
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enum APICDestinationShorthand
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{
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NoShorthand = 0b00,
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Self = 0b01,
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AllIncludingSelf = 0b10,
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AllExcludingSelf = 0b11
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};
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enum LVTTimerDivide
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{
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DivideBy2 = 0b000,
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DivideBy4 = 0b001,
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DivideBy8 = 0b010,
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DivideBy16 = 0b011,
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DivideBy32 = 0b100,
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DivideBy64 = 0b101,
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DivideBy128 = 0b110,
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DivideBy1 = 0b111
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};
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enum LVTTimerMask
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{
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Unmasked = 0b0,
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Masked = 0b1
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};
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enum LVTTimerMode
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{
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OneShot = 0b00,
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Periodic = 0b01,
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TSCDeadline = 0b10
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};
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typedef union
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{
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struct
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{
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/** Vector */
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uint64_t VEC : 8;
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/** Reserved */
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uint64_t Reserved0 : 4;
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/** Delivery Status */
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uint64_t DS : 1;
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/** Reserved */
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uint64_t Reserved1 : 3;
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/** Mask */
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uint64_t M : 1;
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/** Timer Mode */
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uint64_t TMM : 1;
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/** Reserved */
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uint64_t Reserved2 : 14;
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};
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uint32_t raw;
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} __packed LVTTimer;
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typedef union
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{
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struct
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{
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/** Vector */
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uint64_t VEC : 8;
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/** APIC Software Enable */
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uint64_t ASE : 1;
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/** Focus CPU Core Checking */
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uint64_t FCC : 1;
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/** Reserved */
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uint64_t Reserved0 : 22;
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};
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uint32_t raw;
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} __packed Spurious;
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typedef union
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{
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struct
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{
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/** Vector */
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uint64_t VEC : 8;
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/** Message Type */
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uint64_t MT : 3;
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/** Destination Mode */
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uint64_t DM : 1;
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/** Delivery Status */
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uint64_t DS : 1;
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/** Reserved */
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uint64_t Reserved0 : 1;
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/** Level */
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uint64_t L : 1;
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/** Trigger Mode */
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uint64_t TGM : 1;
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/** Remote Read Status */
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uint64_t RSS : 2;
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/** Destination Shorthand */
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uint64_t DSH : 2;
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/** Reserved */
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uint64_t Reserved2 : 36;
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/** Destination */
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uint64_t DES : 8;
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};
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struct
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{
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/** Vector */
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uint64_t VEC : 8;
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/** Message Type */
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uint64_t MT : 3;
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/** Destination Mode */
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uint64_t DM : 1;
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/** Reserved */
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uint64_t Reserved0 : 2;
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/** Level */
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uint64_t L : 1;
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/** Trigger Mode */
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uint64_t TGM : 1;
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/** Reserved */
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uint64_t Reserved1 : 2;
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/** Destination Shorthand */
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uint64_t DSH : 2;
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/** Reserved */
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uint64_t Reserved2 : 12;
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/** Destination */
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uint64_t DES : 32;
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} x2;
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struct
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{
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uint32_t Low;
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uint32_t High;
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} split;
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uint64_t raw;
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} __packed InterruptCommandRegister;
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typedef union
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{
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struct
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{
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/** Reserved */
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uint64_t Reserved0 : 2;
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/** Sent Accept Error */
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uint64_t SAE : 1;
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/** Receive Accept Error */
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uint64_t RAE : 1;
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/** Reserved */
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uint64_t Reserved1 : 1;
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/** Sent Illegal Vector */
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uint64_t SIV : 1;
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/** Received Illegal Vector */
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uint64_t RIV : 1;
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/** Illegal Register Address */
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uint64_t IRA : 1;
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/** Reserved */
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uint64_t Reserved2 : 24;
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};
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uint32_t raw;
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} ErrorStatusRegister;
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typedef union
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{
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struct
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{
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/** Interrupt Vector */
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uint64_t VEC : 8;
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/** Delivery Mode */
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uint64_t MT : 3;
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/** Destination Mode */
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uint64_t DM : 1;
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/** Delivery Status */
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uint64_t DS : 1;
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/** Interrupt Input Pin Polarity */
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uint64_t IPP : 1;
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/** Remote IRR */
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uint64_t RIR : 1;
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/** Trigger Mode */
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uint64_t TGM : 1;
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/** Mask */
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uint64_t M : 1;
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/** Reserved */
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uint64_t Reserved0 : 15;
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/** Reserved */
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uint64_t Reserved1 : 24;
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/** Destination */
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uint64_t DES : 8;
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};
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struct
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{
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uint32_t Low;
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uint32_t High;
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} split;
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uint64_t raw;
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} __packed IOAPICRedirectEntry;
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typedef union
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{
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struct
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{
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/** Version */
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uint64_t VER : 8;
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/** Reserved */
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uint64_t Reserved0 : 8;
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/** Max LVT Entries */
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uint64_t MLE : 8;
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/** Reserved */
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uint64_t Reserved1 : 7;
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/** Extended APIC Register Space Present */
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uint64_t EAS : 1;
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};
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uint32_t raw;
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} __packed IOAPICVersion;
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class APIC
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{
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private:
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bool x2APICSupported = false;
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uint64_t APICBaseAddress = 0;
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public:
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decltype(x2APICSupported) &x2APIC = x2APICSupported;
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uint32_t Read(uint32_t Register);
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void Write(uint32_t Register, uint32_t Value);
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void IOWrite(uint64_t Base, uint32_t Register, uint32_t Value);
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uint32_t IORead(uint64_t Base, uint32_t Register);
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void EOI();
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void RedirectIRQs(uint8_t CPU = 0);
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void WaitForIPI();
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void ICR(InterruptCommandRegister icr);
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void SendInitIPI(int CPU);
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void SendStartupIPI(int CPU, uint64_t StartupAddress);
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uint32_t IOGetMaxRedirect(uint32_t APICID);
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void RawRedirectIRQ(uint8_t Vector, uint32_t GSI, uint16_t Flags, uint8_t CPU, int Status);
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void RedirectIRQ(uint8_t CPU, uint8_t IRQ, int Status);
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APIC(int Core);
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~APIC();
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};
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class Timer : public Interrupts::Handler
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{
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private:
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APIC *lapic;
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uint64_t Ticks = 0;
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void OnInterruptReceived(CPU::TrapFrame *Frame);
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public:
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uint64_t GetTicks() { return Ticks; }
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void OneShot(uint32_t Vector, uint64_t Miliseconds);
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Timer(APIC *apic);
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~Timer();
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};
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}
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#endif // !__FENNIX_KERNEL_APIC_H__
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