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Kernel/memory-test
This commit is contained in:
EnderIce2
@ -1,492 +0,0 @@
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/*
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This file is part of Fennix Kernel.
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Fennix Kernel is free software: you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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Fennix Kernel is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <cpu.hpp>
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#include <memory.hpp>
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#include <convert.h>
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#include <debug.h>
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#include <smp.hpp>
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#include "../kernel.h"
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namespace CPU
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{
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static bool SSEEnabled = false;
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char *Vendor()
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{
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static char Vendor[13] = {0};
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if (Vendor[0] != 0)
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return Vendor;
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#if defined(a64)
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uint32_t eax, ebx, ecx, edx;
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x64::cpuid(0x0, &eax, &ebx, &ecx, &edx);
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memcpy(Vendor + 0, &ebx, 4);
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memcpy(Vendor + 4, &edx, 4);
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memcpy(Vendor + 8, &ecx, 4);
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#elif defined(a32)
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uint32_t eax, ebx, ecx, edx;
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x32::cpuid(0x0, &eax, &ebx, &ecx, &edx);
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memcpy(Vendor + 0, &ebx, 4);
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memcpy(Vendor + 4, &edx, 4);
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memcpy(Vendor + 8, &ecx, 4);
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#elif defined(aa64)
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asmv("mrs %0, MIDR_EL1"
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: "=r"(Vendor[0]));
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#endif
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return Vendor;
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}
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char *Name()
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{
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static char Name[49] = {0};
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if (Name[0] != 0)
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return Name;
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#if defined(a64)
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uint32_t eax, ebx, ecx, edx;
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x64::cpuid(0x80000002, &eax, &ebx, &ecx, &edx);
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memcpy(Name + 0, &eax, 4);
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memcpy(Name + 4, &ebx, 4);
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memcpy(Name + 8, &ecx, 4);
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memcpy(Name + 12, &edx, 4);
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x64::cpuid(0x80000003, &eax, &ebx, &ecx, &edx);
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memcpy(Name + 16, &eax, 4);
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memcpy(Name + 20, &ebx, 4);
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memcpy(Name + 24, &ecx, 4);
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memcpy(Name + 28, &edx, 4);
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x64::cpuid(0x80000004, &eax, &ebx, &ecx, &edx);
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memcpy(Name + 32, &eax, 4);
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memcpy(Name + 36, &ebx, 4);
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memcpy(Name + 40, &ecx, 4);
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memcpy(Name + 44, &edx, 4);
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#elif defined(a32)
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uint32_t eax, ebx, ecx, edx;
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x32::cpuid(0x80000002, &eax, &ebx, &ecx, &edx);
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memcpy(Name + 0, &eax, 4);
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memcpy(Name + 4, &ebx, 4);
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memcpy(Name + 8, &ecx, 4);
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memcpy(Name + 12, &edx, 4);
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x32::cpuid(0x80000003, &eax, &ebx, &ecx, &edx);
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memcpy(Name + 16, &eax, 4);
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memcpy(Name + 20, &ebx, 4);
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memcpy(Name + 24, &ecx, 4);
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memcpy(Name + 28, &edx, 4);
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x32::cpuid(0x80000004, &eax, &ebx, &ecx, &edx);
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memcpy(Name + 32, &eax, 4);
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memcpy(Name + 36, &ebx, 4);
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memcpy(Name + 40, &ecx, 4);
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memcpy(Name + 44, &edx, 4);
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#elif defined(aa64)
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asmv("mrs %0, MIDR_EL1"
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: "=r"(Name[0]));
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#endif
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return Name;
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}
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char *Hypervisor()
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{
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static char Hypervisor[13] = {0};
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if (Hypervisor[0] != 0)
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return Hypervisor;
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#if defined(a64)
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uint32_t eax, ebx, ecx, edx;
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x64::cpuid(0x40000000, &eax, &ebx, &ecx, &edx);
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memcpy(Hypervisor + 0, &ebx, 4);
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memcpy(Hypervisor + 4, &ecx, 4);
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memcpy(Hypervisor + 8, &edx, 4);
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#elif defined(a32)
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uint32_t eax, ebx, ecx, edx;
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x64::cpuid(0x40000000, &eax, &ebx, &ecx, &edx);
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memcpy(Hypervisor + 0, &ebx, 4);
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memcpy(Hypervisor + 4, &ecx, 4);
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memcpy(Hypervisor + 8, &edx, 4);
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#elif defined(aa64)
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asmv("mrs %0, MIDR_EL1"
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: "=r"(Hypervisor[0]));
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#endif
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return Hypervisor;
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}
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bool Interrupts(InterruptsType Type)
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{
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switch (Type)
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{
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case Check:
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{
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uintptr_t Flags;
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#if defined(a64)
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asmv("pushfq");
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asmv("popq %0"
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: "=r"(Flags));
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return Flags & (1 << 9);
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#elif defined(a32)
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asmv("pushfl");
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asmv("popl %0"
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: "=r"(Flags));
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return Flags & (1 << 9);
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#elif defined(aa64)
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asmv("mrs %0, daif"
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: "=r"(Flags));
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return !(Flags & (1 << 2));
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#endif
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}
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case Enable:
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{
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#if defined(a86)
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asmv("sti");
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#elif defined(aa64)
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asmv("msr daifclr, #2");
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#endif
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return true;
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}
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case Disable:
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{
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#if defined(a86)
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asmv("cli");
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#elif defined(aa64)
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asmv("msr daifset, #2");
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#endif
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return true;
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}
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default:
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break;
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}
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return false;
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}
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void *PageTable(void *PT)
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{
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#if defined(a64)
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if (PT)
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asmv("movq %0, %%cr3"
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:
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: "r"(PT));
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else
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asmv("movq %%cr3, %0"
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: "=r"(PT));
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#elif defined(a32)
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if (PT)
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asmv("movl %0, %%cr3"
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:
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: "r"(PT));
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else
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asmv("movl %%cr3, %0"
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: "=r"(PT));
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#elif defined(aa64)
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if (PT)
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asmv("msr ttbr0_el1, %0"
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:
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: "r"(PT));
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else
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asmv("mrs %0, ttbr0_el1"
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: "=r"(PT));
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#endif
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return PT;
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}
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void InitializeFeatures(long Core)
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{
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#if defined(a64)
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bool PGESupport = false;
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bool SSESupport = false;
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bool UMIPSupport = false;
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bool SMEPSupport = false;
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bool SMAPSupport = false;
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static int BSP = 0;
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x64::CR0 cr0 = x64::readcr0();
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x64::CR4 cr4 = x64::readcr4();
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if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
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{
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CPU::x86::AMD::CPUID0x00000001 cpuid1;
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CPU::x86::AMD::CPUID0x00000007 cpuid7;
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cpuid1.Get();
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cpuid7.Get();
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PGESupport = cpuid1.EDX.PGE;
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SSESupport = cpuid1.EDX.SSE;
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SMEPSupport = cpuid7.EBX.SMEP;
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SMAPSupport = cpuid7.EBX.SMAP;
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UMIPSupport = cpuid7.ECX.UMIP;
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}
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else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
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{
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CPU::x86::Intel::CPUID0x00000001 cpuid1;
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CPU::x86::Intel::CPUID0x00000007_0 cpuid7_0;
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cpuid1.Get();
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cpuid7_0.Get();
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PGESupport = cpuid1.EDX.PGE;
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SSESupport = cpuid1.EDX.SSE;
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SMEPSupport = cpuid7_0.EBX.SMEP;
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SMAPSupport = cpuid7_0.EBX.SMAP;
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UMIPSupport = cpuid7_0.ECX.UMIP;
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}
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if (Config.SIMD == false)
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{
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debug("Disabling SSE support...");
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SSESupport = false;
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}
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if (PGESupport)
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{
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debug("Enabling global pages support...");
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if (!BSP)
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KPrint("Global Pages is supported.");
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cr4.PGE = 1;
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}
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bool SSEEnableAfter = false;
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/* Not sure if my code is not working properly or something else is the issue. */
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if ((strcmp(Hypervisor(), x86_CPUID_VENDOR_TCG) != 0 &&
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strcmp(Hypervisor(), x86_CPUID_VENDOR_VIRTUALBOX) != 0) &&
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SSESupport)
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{
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debug("Enabling SSE support...");
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if (!BSP)
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KPrint("SSE is supported.");
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cr0.EM = 0;
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cr0.MP = 1;
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cr4.OSFXSR = 1;
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cr4.OSXMMEXCPT = 1;
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CPUData *CoreData = GetCPU(Core);
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CoreData->Data.FPU = (CPU::x64::FXState *)KernelAllocator.RequestPages(TO_PAGES(sizeof(CPU::x64::FXState) + 1));
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memset(CoreData->Data.FPU, 0, FROM_PAGES(TO_PAGES(sizeof(CPU::x64::FXState))));
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CoreData->Data.FPU->mxcsr = 0b0001111110000000;
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CoreData->Data.FPU->mxcsrmask = 0b1111111110111111;
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CoreData->Data.FPU->fcw = 0b0000001100111111;
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CPU::x64::fxrstor(CoreData->Data.FPU);
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SSEEnableAfter = true;
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}
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cr0.NW = 0;
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cr0.CD = 0;
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cr0.WP = 1;
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x64::writecr0(cr0);
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if (strcmp(Hypervisor(), x86_CPUID_VENDOR_VIRTUALBOX) != 0 &&
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strcmp(Hypervisor(), x86_CPUID_VENDOR_TCG) != 0)
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{
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// FIXME: I don't think this is reporting correctly. This has to be fixed asap.
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debug("Enabling UMIP, SMEP & SMAP support...");
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if (UMIPSupport)
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{
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if (!BSP)
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KPrint("UMIP is supported.");
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debug("UMIP is supported.");
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// cr4.UMIP = 1;
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}
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if (SMEPSupport)
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{
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if (!BSP)
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KPrint("SMEP is supported.");
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debug("SMEP is supported.");
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// cr4.SMEP = 1;
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}
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if (SMAPSupport)
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{
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if (!BSP)
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KPrint("SMAP is supported.");
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debug("SMAP is supported.");
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// cr4.SMAP = 1;
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}
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}
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else
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{
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if (!BSP)
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{
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if (strcmp(Hypervisor(), x86_CPUID_VENDOR_VIRTUALBOX) == 0)
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KPrint("VirtualBox detected. Not using UMIP, SMEP & SMAP");
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else if (strcmp(Hypervisor(), x86_CPUID_VENDOR_TCG) == 0)
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KPrint("QEMU (TCG) detected. Not using UMIP, SMEP & SMAP");
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}
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}
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debug("Writing CR4...");
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x64::writecr4(cr4);
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debug("Wrote CR4.");
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debug("Enabling PAT support...");
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x64::wrmsr(x64::MSR_CR_PAT, 0x6 | (0x0 << 8) | (0x1 << 16));
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if (!BSP++)
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trace("Features for BSP initialized.");
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if (SSEEnableAfter)
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SSEEnabled = true;
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#elif defined(a32)
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#elif defined(aa64)
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#endif
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}
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uintptr_t Counter()
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{
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// TODO: Get the counter from the x2APIC or any other timer that is available. (TSC is not available on all CPUs)
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uintptr_t Counter;
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#if defined(a64)
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asmv("rdtsc"
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: "=A"(Counter));
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#elif defined(a32)
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asmv("rdtsc"
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: "=A"(Counter));
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#elif defined(aa64)
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asmv("mrs %0, cntvct_el0"
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: "=r"(Counter));
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#endif
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return Counter;
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}
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uint64_t CheckSIMD()
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||||
{
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#if defined(a32)
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return SIMD_NONE; /* TODO: Support x86 SIMD on x32 */
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#endif
|
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|
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if (unlikely(!SSEEnabled))
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return SIMD_NONE;
|
||||
|
||||
// return SIMD_SSE;
|
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|
||||
#if defined(a86)
|
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static uint64_t SIMDType = SIMD_NONE;
|
||||
|
||||
if (likely(SIMDType != SIMD_NONE))
|
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return SIMDType;
|
||||
|
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if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
|
||||
{
|
||||
CPU::x86::AMD::CPUID0x00000001 cpuid;
|
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asmv("cpuid"
|
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: "=a"(cpuid.EAX.raw), "=b"(cpuid.EBX.raw), "=c"(cpuid.ECX.raw), "=d"(cpuid.EDX.raw)
|
||||
: "a"(0x1));
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||||
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if (cpuid.ECX.SSE42)
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SIMDType |= SIMD_SSE42;
|
||||
else if (cpuid.ECX.SSE41)
|
||||
SIMDType |= SIMD_SSE41;
|
||||
else if (cpuid.ECX.SSE3)
|
||||
SIMDType |= SIMD_SSE3;
|
||||
else if (cpuid.EDX.SSE2)
|
||||
SIMDType |= SIMD_SSE2;
|
||||
else if (cpuid.EDX.SSE)
|
||||
SIMDType |= SIMD_SSE;
|
||||
|
||||
#ifdef DEBUG
|
||||
if (cpuid.ECX.SSE42)
|
||||
debug("SSE4.2 is supported.");
|
||||
if (cpuid.ECX.SSE41)
|
||||
debug("SSE4.1 is supported.");
|
||||
if (cpuid.ECX.SSE3)
|
||||
debug("SSE3 is supported.");
|
||||
if (cpuid.EDX.SSE2)
|
||||
debug("SSE2 is supported.");
|
||||
if (cpuid.EDX.SSE)
|
||||
debug("SSE is supported.");
|
||||
#endif
|
||||
|
||||
return SIMDType;
|
||||
}
|
||||
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
|
||||
{
|
||||
CPU::x86::Intel::CPUID0x00000001 cpuid;
|
||||
asmv("cpuid"
|
||||
: "=a"(cpuid.EAX.raw), "=b"(cpuid.EBX.raw), "=c"(cpuid.ECX.raw), "=d"(cpuid.EDX.raw)
|
||||
: "a"(0x1));
|
||||
|
||||
if (cpuid.ECX.SSE4_2)
|
||||
SIMDType |= SIMD_SSE42;
|
||||
else if (cpuid.ECX.SSE4_1)
|
||||
SIMDType |= SIMD_SSE41;
|
||||
else if (cpuid.ECX.SSE3)
|
||||
SIMDType |= SIMD_SSE3;
|
||||
else if (cpuid.EDX.SSE2)
|
||||
SIMDType |= SIMD_SSE2;
|
||||
else if (cpuid.EDX.SSE)
|
||||
SIMDType |= SIMD_SSE;
|
||||
|
||||
#ifdef DEBUG
|
||||
if (cpuid.ECX.SSE4_2)
|
||||
debug("SSE4.2 is supported.");
|
||||
if (cpuid.ECX.SSE4_1)
|
||||
debug("SSE4.1 is supported.");
|
||||
if (cpuid.ECX.SSE3)
|
||||
debug("SSE3 is supported.");
|
||||
if (cpuid.EDX.SSE2)
|
||||
debug("SSE2 is supported.");
|
||||
if (cpuid.EDX.SSE)
|
||||
debug("SSE is supported.");
|
||||
#endif
|
||||
return SIMDType;
|
||||
}
|
||||
|
||||
debug("No SIMD support.");
|
||||
#endif // a64 || a32
|
||||
return SIMD_NONE;
|
||||
}
|
||||
|
||||
bool CheckSIMD(x86SIMDType Type)
|
||||
{
|
||||
if (unlikely(!SSEEnabled))
|
||||
return false;
|
||||
|
||||
#if defined(a86)
|
||||
if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
|
||||
{
|
||||
CPU::x86::AMD::CPUID0x00000001 cpuid;
|
||||
asmv("cpuid"
|
||||
: "=a"(cpuid.EAX.raw), "=b"(cpuid.EBX.raw), "=c"(cpuid.ECX.raw), "=d"(cpuid.EDX.raw)
|
||||
: "a"(0x1));
|
||||
|
||||
if (Type == SIMD_SSE42)
|
||||
return cpuid.ECX.SSE42;
|
||||
else if (Type == SIMD_SSE41)
|
||||
return cpuid.ECX.SSE41;
|
||||
else if (Type == SIMD_SSE3)
|
||||
return cpuid.ECX.SSE3;
|
||||
else if (Type == SIMD_SSE2)
|
||||
return cpuid.EDX.SSE2;
|
||||
else if (Type == SIMD_SSE)
|
||||
return cpuid.EDX.SSE;
|
||||
}
|
||||
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
|
||||
{
|
||||
CPU::x86::Intel::CPUID0x00000001 cpuid;
|
||||
asmv("cpuid"
|
||||
: "=a"(cpuid.EAX.raw), "=b"(cpuid.EBX.raw), "=c"(cpuid.ECX.raw), "=d"(cpuid.EDX.raw)
|
||||
: "a"(0x1));
|
||||
|
||||
if (Type == SIMD_SSE42)
|
||||
return cpuid.ECX.SSE4_2;
|
||||
else if (Type == SIMD_SSE41)
|
||||
return cpuid.ECX.SSE4_1;
|
||||
else if (Type == SIMD_SSE3)
|
||||
return cpuid.ECX.SSE3;
|
||||
else if (Type == SIMD_SSE2)
|
||||
return cpuid.EDX.SSE2;
|
||||
else if (Type == SIMD_SSE)
|
||||
return cpuid.EDX.SSE;
|
||||
}
|
||||
#endif // a64 || a32
|
||||
return false;
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user