mirror of
https://github.com/EnderIce2/Fennix.git
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Kernel now uses SSE instructions properly
This commit is contained in:
Alex
263
Core/CPU.cpp
263
Core/CPU.cpp
@ -3,26 +3,29 @@
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#include <memory.hpp>
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#include <convert.h>
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#include <debug.h>
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#include <smp.hpp>
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#include "../kernel.h"
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namespace CPU
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{
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static bool SSEEnabled = false;
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char *Vendor()
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{
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static char Vendor[13];
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#if defined(__amd64__)
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uint32_t rax, rbx, rcx, rdx;
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x64::cpuid(0x0, &rax, &rbx, &rcx, &rdx);
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memcpy(Vendor + 0, &rbx, 4);
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memcpy(Vendor + 4, &rdx, 4);
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memcpy(Vendor + 8, &rcx, 4);
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uint32_t eax, ebx, ecx, edx;
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x64::cpuid(0x0, &eax, &ebx, &ecx, &edx);
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memcpy_unsafe(Vendor + 0, &ebx, 4);
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memcpy_unsafe(Vendor + 4, &edx, 4);
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memcpy_unsafe(Vendor + 8, &ecx, 4);
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#elif defined(__i386__)
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uint32_t rax, rbx, rcx, rdx;
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x32::cpuid(0x0, &rax, &rbx, &rcx, &rdx);
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memcpy(Vendor + 0, &rbx, 4);
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memcpy(Vendor + 4, &rdx, 4);
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memcpy(Vendor + 8, &rcx, 4);
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uint32_t eax, ebx, ecx, edx;
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x32::cpuid(0x0, &eax, &ebx, &ecx, &edx);
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memcpy_unsafe(Vendor + 0, &ebx, 4);
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memcpy_unsafe(Vendor + 4, &edx, 4);
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memcpy_unsafe(Vendor + 8, &ecx, 4);
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#elif defined(__aarch64__)
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asmv("mrs %0, MIDR_EL1"
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: "=r"(Vendor[0]));
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@ -34,39 +37,39 @@ namespace CPU
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{
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static char Name[49];
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#if defined(__amd64__)
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uint32_t rax, rbx, rcx, rdx;
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x64::cpuid(0x80000002, &rax, &rbx, &rcx, &rdx);
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memcpy(Name + 0, &rax, 4);
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memcpy(Name + 4, &rbx, 4);
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memcpy(Name + 8, &rcx, 4);
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memcpy(Name + 12, &rdx, 4);
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x64::cpuid(0x80000003, &rax, &rbx, &rcx, &rdx);
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memcpy(Name + 16, &rax, 4);
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memcpy(Name + 20, &rbx, 4);
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memcpy(Name + 24, &rcx, 4);
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memcpy(Name + 28, &rdx, 4);
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x64::cpuid(0x80000004, &rax, &rbx, &rcx, &rdx);
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memcpy(Name + 32, &rax, 4);
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memcpy(Name + 36, &rbx, 4);
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memcpy(Name + 40, &rcx, 4);
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memcpy(Name + 44, &rdx, 4);
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uint32_t eax, ebx, ecx, edx;
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x64::cpuid(0x80000002, &eax, &ebx, &ecx, &edx);
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memcpy_unsafe(Name + 0, &eax, 4);
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memcpy_unsafe(Name + 4, &ebx, 4);
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memcpy_unsafe(Name + 8, &ecx, 4);
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memcpy_unsafe(Name + 12, &edx, 4);
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x64::cpuid(0x80000003, &eax, &ebx, &ecx, &edx);
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memcpy_unsafe(Name + 16, &eax, 4);
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memcpy_unsafe(Name + 20, &ebx, 4);
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memcpy_unsafe(Name + 24, &ecx, 4);
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memcpy_unsafe(Name + 28, &edx, 4);
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x64::cpuid(0x80000004, &eax, &ebx, &ecx, &edx);
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memcpy_unsafe(Name + 32, &eax, 4);
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memcpy_unsafe(Name + 36, &ebx, 4);
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memcpy_unsafe(Name + 40, &ecx, 4);
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memcpy_unsafe(Name + 44, &edx, 4);
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#elif defined(__i386__)
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uint32_t rax, rbx, rcx, rdx;
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x32::cpuid(0x80000002, &rax, &rbx, &rcx, &rdx);
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memcpy(Name + 0, &rax, 4);
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memcpy(Name + 4, &rbx, 4);
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memcpy(Name + 8, &rcx, 4);
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memcpy(Name + 12, &rdx, 4);
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x32::cpuid(0x80000003, &rax, &rbx, &rcx, &rdx);
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memcpy(Name + 16, &rax, 4);
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memcpy(Name + 20, &rbx, 4);
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memcpy(Name + 24, &rcx, 4);
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memcpy(Name + 28, &rdx, 4);
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x32::cpuid(0x80000004, &rax, &rbx, &rcx, &rdx);
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memcpy(Name + 32, &rax, 4);
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memcpy(Name + 36, &rbx, 4);
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memcpy(Name + 40, &rcx, 4);
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memcpy(Name + 44, &rdx, 4);
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uint32_t eax, ebx, ecx, edx;
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x32::cpuid(0x80000002, &eax, &ebx, &ecx, &edx);
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memcpy_unsafe(Name + 0, &eax, 4);
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memcpy_unsafe(Name + 4, &ebx, 4);
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memcpy_unsafe(Name + 8, &ecx, 4);
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memcpy_unsafe(Name + 12, &edx, 4);
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x32::cpuid(0x80000003, &eax, &ebx, &ecx, &edx);
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memcpy_unsafe(Name + 16, &eax, 4);
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memcpy_unsafe(Name + 20, &ebx, 4);
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memcpy_unsafe(Name + 24, &ecx, 4);
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memcpy_unsafe(Name + 28, &edx, 4);
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x32::cpuid(0x80000004, &eax, &ebx, &ecx, &edx);
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memcpy_unsafe(Name + 32, &eax, 4);
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memcpy_unsafe(Name + 36, &ebx, 4);
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memcpy_unsafe(Name + 40, &ecx, 4);
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memcpy_unsafe(Name + 44, &edx, 4);
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#elif defined(__aarch64__)
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asmv("mrs %0, MIDR_EL1"
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: "=r"(Name[0]));
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@ -78,17 +81,17 @@ namespace CPU
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{
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static char Hypervisor[13];
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#if defined(__amd64__)
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uint32_t rax, rbx, rcx, rdx;
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x64::cpuid(0x40000000, &rax, &rbx, &rcx, &rdx);
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memcpy(Hypervisor + 0, &rbx, 4);
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memcpy(Hypervisor + 4, &rcx, 4);
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memcpy(Hypervisor + 8, &rdx, 4);
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uint32_t eax, ebx, ecx, edx;
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x64::cpuid(0x40000000, &eax, &ebx, &ecx, &edx);
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memcpy_unsafe(Hypervisor + 0, &ebx, 4);
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memcpy_unsafe(Hypervisor + 4, &ecx, 4);
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memcpy_unsafe(Hypervisor + 8, &edx, 4);
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#elif defined(__i386__)
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uint32_t rax, rbx, rcx, rdx;
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x64::cpuid(0x40000000, &rax, &rbx, &rcx, &rdx);
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memcpy(Hypervisor + 0, &rbx, 4);
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memcpy(Hypervisor + 4, &rcx, 4);
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memcpy(Hypervisor + 8, &rdx, 4);
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uint32_t eax, ebx, ecx, edx;
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x64::cpuid(0x40000000, &eax, &ebx, &ecx, &edx);
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memcpy_unsafe(Hypervisor + 0, &ebx, 4);
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memcpy_unsafe(Hypervisor + 4, &ecx, 4);
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memcpy_unsafe(Hypervisor + 8, &edx, 4);
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#elif defined(__aarch64__)
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asmv("mrs %0, MIDR_EL1"
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: "=r"(Hypervisor[0]));
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@ -171,15 +174,51 @@ namespace CPU
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return PT;
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}
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void InitializeFeatures()
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void InitializeFeatures(long Core)
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{
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bool PGESupport = false;
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bool SSESupport = false;
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#if defined(__amd64__)
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static int BSP = 0;
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x64::CR0 cr0 = x64::readcr0();
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x64::CR4 cr4 = x64::readcr4();
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uint32_t rax, rbx, rcx, rdx;
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x64::cpuid(0x1, &rax, &rbx, &rcx, &rdx);
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if (rdx & x64::CPUID_FEAT_RDX_PGE)
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if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
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{
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#if defined(__amd64__)
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CPU::x64::AMD::CPUID0x1 cpuid1amd;
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#elif defined(__i386__)
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CPU::x32::AMD::CPUID0x1 cpuid1amd;
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#endif
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#if defined(__amd64__) || defined(__i386__)
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asmv("cpuid"
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: "=a"(cpuid1amd.EAX.raw), "=b"(cpuid1amd.EBX.raw), "=c"(cpuid1amd.ECX.raw), "=d"(cpuid1amd.EDX.raw)
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: "a"(0x1));
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#endif
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if (cpuid1amd.EDX.PGE)
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PGESupport = true;
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if (cpuid1amd.EDX.SSE)
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SSESupport = true;
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}
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else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
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{
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#if defined(__amd64__)
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CPU::x64::Intel::CPUID0x1 cpuid1intel;
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#elif defined(__i386__)
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CPU::x32::Intel::CPUID0x1 cpuid1intel;
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#endif
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#if defined(__amd64__) || defined(__i386__)
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asmv("cpuid"
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: "=a"(cpuid1intel.EAX.raw), "=b"(cpuid1intel.EBX.raw), "=c"(cpuid1intel.ECX.raw), "=d"(cpuid1intel.EDX.raw)
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: "a"(0x1));
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#endif
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if (cpuid1intel.EDX.PGE)
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PGESupport = true;
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if (cpuid1intel.EDX.SSE)
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SSESupport = true;
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}
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if (PGESupport)
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{
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debug("Enabling global pages support...");
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if (!BSP)
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@ -187,16 +226,29 @@ namespace CPU
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cr4.PGE = 1;
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}
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if (rdx & x64::CPUID_FEAT_RDX_SSE)
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{
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debug("Enabling SSE support...");
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if (!BSP)
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KPrint("SSE is supported.");
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cr0.EM = 0;
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cr0.MP = 1;
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cr4.OSFXSR = 1;
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cr4.OSXMMEXCPT = 1;
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}
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bool SSEEnableAfter = false;
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if (strcmp(CPU::Hypervisor(), x86_CPUID_VENDOR_TCG) != 0) /* Not sure if my code is not working properly or something else is the issue. */
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if (SSESupport)
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{
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debug("Enabling SSE support...");
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if (!BSP)
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KPrint("SSE is supported.");
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cr0.EM = 0;
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cr0.MP = 1;
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cr4.OSFXSR = 1;
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cr4.OSXMMEXCPT = 1;
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CPUData *CoreData = GetCPU(Core);
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CoreData->Data.FPU = (CPU::x64::FXState *)KernelAllocator.RequestPages(TO_PAGES(sizeof(CPU::x64::FXState)));
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memset(CoreData->Data.FPU, 0, FROM_PAGES(TO_PAGES(sizeof(CPU::x64::FXState))));
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CoreData->Data.FPU->mxcsr = 0b0001111110000000;
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CoreData->Data.FPU->mxcsrmask = 0b1111111110111111;
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CoreData->Data.FPU->fcw = 0b0000001100111111;
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CPU::x64::fxrstor(CoreData->Data.FPU);
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SSEEnableAfter = true;
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}
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if (!BSP)
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KPrint("Enabling CPU cache.");
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@ -207,24 +259,26 @@ namespace CPU
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x64::writecr0(cr0);
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// FIXME: I don't think this is reporting correctly. This has to be fixed asap.
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debug("Enabling UMIP, SMEP & SMAP support...");
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x64::cpuid(0x1, &rax, &rbx, &rcx, &rdx);
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if (rdx & x64::CPUID_FEAT_RDX_UMIP) // https://en.wikipedia.org/wiki/Control_register
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uint32_t eax, ebx, ecx, edx;
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x64::cpuid(0x1, &eax, &ebx, &ecx, &edx);
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if (edx & (1 << 2)) // https://en.wikipedia.org/wiki/Control_register
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{
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if (!BSP)
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KPrint("UMIP is supported.");
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debug("UMIP is supported.");
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// cr4.UMIP = 1;
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}
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if (rdx & x64::CPUID_FEAT_RDX_SMEP) // https://en.wikipedia.org/wiki/Control_register#SMEP
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// https://web.archive.org/web/20160312223150/http://ncsi.com/nsatc11/presentations/wednesday/emerging_technologies/fischer.pdf
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if (edx & (1 << 7)) // https://en.wikipedia.org/wiki/Control_register#SMEP
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// https://web.archive.org/web/20160312223150/http://ncsi.com/nsatc11/presentations/wednesday/emerging_technologies/fischer.pdf
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{
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if (!BSP)
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KPrint("SMEP is supported.");
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debug("SMEP is supported.");
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// cr4.SMEP = 1;
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}
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if (rdx & x64::CPUID_FEAT_RDX_SMAP) // https://en.wikipedia.org/wiki/Supervisor_Mode_Access_Prevention
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if (edx & (1 << 20)) // https://en.wikipedia.org/wiki/Supervisor_Mode_Access_Prevention
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{
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if (!BSP)
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KPrint("SMAP is supported.");
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@ -252,6 +306,8 @@ namespace CPU
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x64::wrmsr(x64::MSR_CR_PAT, 0x6 | (0x0 << 8) | (0x1 << 16));
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if (!BSP++)
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trace("Features for BSP initialized.");
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if (SSEEnableAfter)
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SSEEnabled = true;
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#elif defined(__i386__)
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#elif defined(__aarch64__)
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#endif
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@ -276,6 +332,14 @@ namespace CPU
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x86SIMDType CheckSIMD()
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{
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if (unlikely(!SSEEnabled))
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return SIMD_NONE;
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static x86SIMDType SIMDType = SIMD_NONE;
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if (likely(SIMDType != SIMD_NONE))
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return SIMDType;
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if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
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{
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#if defined(__amd64__)
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@ -289,17 +353,32 @@ namespace CPU
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: "a"(0x1));
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#endif
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if (cpuid1amd.ECX.SSE4_2)
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return SIMD_SSE42;
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SIMDType = SIMD_SSE42;
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else if (cpuid1amd.ECX.SSE4_1)
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return SIMD_SSE41;
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SIMDType = SIMD_SSE41;
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else if (cpuid1amd.ECX.SSE3)
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return SIMD_SSE3;
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SIMDType = SIMD_SSE3;
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else if (cpuid1amd.EDX.SSE2)
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return SIMD_SSE2;
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SIMDType = SIMD_SSE2;
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else if (cpuid1amd.EDX.SSE)
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return SIMD_SSE;
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SIMDType = SIMD_SSE;
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#ifdef DEBUG
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if (cpuid1amd.ECX.SSE4_2)
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debug("SSE4.2 is supported.");
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if (cpuid1amd.ECX.SSE4_1)
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debug("SSE4.1 is supported.");
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if (cpuid1amd.ECX.SSE3)
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debug("SSE3 is supported.");
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if (cpuid1amd.EDX.SSE2)
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debug("SSE2 is supported.");
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if (cpuid1amd.EDX.SSE)
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debug("SSE is supported.");
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#endif
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return SIMDType;
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}
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if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
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else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
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{
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#if defined(__amd64__)
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CPU::x64::Intel::CPUID0x1 cpuid1intel;
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@ -312,15 +391,30 @@ namespace CPU
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: "a"(0x1));
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#endif
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if (cpuid1intel.ECX.SSE4_2)
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return SIMD_SSE42;
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SIMDType = SIMD_SSE42;
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else if (cpuid1intel.ECX.SSE4_1)
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return SIMD_SSE41;
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SIMDType = SIMD_SSE41;
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else if (cpuid1intel.ECX.SSE3)
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return SIMD_SSE3;
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SIMDType = SIMD_SSE3;
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else if (cpuid1intel.EDX.SSE2)
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return SIMD_SSE2;
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SIMDType = SIMD_SSE2;
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else if (cpuid1intel.EDX.SSE)
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return SIMD_SSE;
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SIMDType = SIMD_SSE;
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#ifdef DEBUG
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if (cpuid1intel.ECX.SSE4_2)
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debug("SSE4.2 is supported.");
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if (cpuid1intel.ECX.SSE4_1)
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debug("SSE4.1 is supported.");
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if (cpuid1intel.ECX.SSE3)
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debug("SSE3 is supported.");
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if (cpuid1intel.EDX.SSE2)
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debug("SSE2 is supported.");
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if (cpuid1intel.EDX.SSE)
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debug("SSE is supported.");
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#endif
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return SIMDType;
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}
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return SIMD_NONE;
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@ -328,6 +422,9 @@ namespace CPU
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bool CheckSIMD(x86SIMDType Type)
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{
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if (unlikely(!SSEEnabled))
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return false;
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if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
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{
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#if defined(__amd64__)
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@ -351,7 +448,7 @@ namespace CPU
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else if (Type == SIMD_SSE)
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return cpuid1amd.EDX.SSE;
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}
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if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
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else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
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{
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#if defined(__amd64__)
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CPU::x64::Intel::CPUID0x1 cpuid1intel;
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