enderice2/Fennix
1
0
Fork 0
mirror of https://github.com/EnderIce2/Fennix.git synced 2025-07-01 18:39:16 +00:00
Code Issues Actions Releases Wiki Activity

refactor: Fix build on i386
Some checks failed
CodeQL Advanced / Analyze (${{ matrix.language }}) (manual, c-cpp) (push) Has been cancelled
Details
Deploy Documentation / Deploy Documentation to GitHub Pages (push) Has been cancelled
Details
Build OS / Build Cross-Compiler & Toolchain (push) Has been cancelled
Details
Build OS / Build amd64 (push) Has been cancelled
Details
Build OS / Build i386 (push) Has been cancelled
Details
Build OS / Build aarch64 (push) Has been cancelled
Details

Browse Source 
Signed-off-by: EnderIce2 <enderice2@protonmail.com>
This commit is contained in:
EnderIce2
2025-01-07 17:49:37 +02:00
parent 463d16f8bc
commit 2bb997597e
57 changed files with 1489 additions and 923 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
Kernel/tasking/scheduler/custom.cpp
View File

@ -195,7 +195,7 @@ namespace Tasking::Scheduler
void Custom::StartScheduler()
{
#if defined(__amd64__) || defined(__i386__)
#if defined(__amd64__)
if (Interrupts::apicTimer[0])
{
((APIC::Timer *)Interrupts::apicTimer[0])->OneShot(CPU::x86::IRQ16, 100);
@ -587,15 +587,11 @@ namespace Tasking::Scheduler
else
{
CurrentCPU->CurrentThread->Registers = *Frame;
CPU::x64::fxsave(&CurrentCPU->CurrentThread->FPU);
#ifdef __amd64__
CurrentCPU->CurrentThread->ShadowGSBase = CPU::x64::rdmsr(CPU::x64::MSR_SHADOW_GS_BASE);
CurrentCPU->CurrentThread->GSBase = CPU::x64::rdmsr(CPU::x64::MSR_GS_BASE);
CurrentCPU->CurrentThread->FSBase = CPU::x64::rdmsr(CPU::x64::MSR_FS_BASE);
#else
CurrentCPU->CurrentThread->ShadowGSBase = uintptr_t(CPU::x32::rdmsr(CPU::x32::MSR_SHADOW_GS_BASE));
CurrentCPU->CurrentThread->GSBase = uintptr_t(CPU::x32::rdmsr(CPU::x32::MSR_GS_BASE));
CurrentCPU->CurrentThread->FSBase = uintptr_t(CPU::x32::rdmsr(CPU::x32::MSR_FS_BASE));
#if defined(__amd64__) || defined(__i386__)
CPU::x86::fxsave(&CurrentCPU->CurrentThread->FPU);
CurrentCPU->CurrentThread->ShadowGSBase = CPU::x86::rdmsr(CPU::x86::MSR_SHADOW_GS_BASE);
CurrentCPU->CurrentThread->GSBase = CPU::x86::rdmsr(CPU::x86::MSR_GS_BASE);
CurrentCPU->CurrentThread->FSBase = CPU::x86::rdmsr(CPU::x86::MSR_FS_BASE);
#endif
if (CurrentCPU->CurrentProcess->State.load() == TaskState::Running)
@ -681,18 +677,12 @@ namespace Tasking::Scheduler
*Frame = CurrentCPU->CurrentThread->Registers;
#ifdef __amd64__
#if defined(__amd64__) || defined(__i386__)
GlobalDescriptorTable::SetKernelStack((void *)((uintptr_t)CurrentCPU->CurrentThread->Stack->GetStackTop()));
CPU::x64::fxrstor(&CurrentCPU->CurrentThread->FPU);
CPU::x64::wrmsr(CPU::x64::MSR_SHADOW_GS_BASE, CurrentCPU->CurrentThread->ShadowGSBase);
CPU::x64::wrmsr(CPU::x64::MSR_GS_BASE, CurrentCPU->CurrentThread->GSBase);
CPU::x64::wrmsr(CPU::x64::MSR_FS_BASE, CurrentCPU->CurrentThread->FSBase);
#else
GlobalDescriptorTable::SetKernelStack((void *)((uintptr_t)CurrentCPU->CurrentThread->Stack->GetStackTop()));
CPU::x32::fxrstor(&CurrentCPU->CurrentThread->FPU);
CPU::x32::wrmsr(CPU::x32::MSR_SHADOW_GS_BASE, CurrentCPU->CurrentThread->ShadowGSBase);
CPU::x32::wrmsr(CPU::x32::MSR_GS_BASE, CurrentCPU->CurrentThread->GSBase);
CPU::x32::wrmsr(CPU::x32::MSR_FS_BASE, CurrentCPU->CurrentThread->FSBase);
CPU::x86::fxrstor(&CurrentCPU->CurrentThread->FPU);
CPU::x86::wrmsr(CPU::x86::MSR_SHADOW_GS_BASE, CurrentCPU->CurrentThread->ShadowGSBase);
CPU::x86::wrmsr(CPU::x86::MSR_GS_BASE, CurrentCPU->CurrentThread->GSBase);
CPU::x86::wrmsr(CPU::x86::MSR_FS_BASE, CurrentCPU->CurrentThread->FSBase);
#endif
CurrentCPU->CurrentProcess->Signals.HandleSignal(Frame, CurrentCPU->CurrentThread.load());

150
Kernel/tasking/signal.cpp
View File

@ -20,13 +20,6 @@
#include <task.hpp>
#include <errno.h>
#if defined(__amd64__)
#include "../arch/amd64/cpu/gdt.hpp"
#elif defined(__i386__)
#include "../arch/i386/cpu/gdt.hpp"
#elif defined(__aarch64__)
#endif
#include "../kernel.h"
#ifdef DEBUG
@ -344,149 +337,6 @@ namespace Tasking
return {};
}
bool Signal::HandleSignal(CPU::SchedulerFrame *tf, void *thread)
{
/* We don't want to do this in kernel mode */
if (tf->cs != GDT_USER_CODE)
return false;
if (Queue.empty())
return false;
debug("We have %d signals to handle", Queue.size());
SmartLock(SignalLock);
SignalInfo sigI = GetAvailableSignal(thread);
if (sigI.sig == SIGNULL)
return false;
uintptr_t _p_rsp = ((PCB *)ctx)->PageTable->Get(tf->rsp);
uint64_t paRsp = _p_rsp;
paRsp &= ~0xF; /* Align */
paRsp -= 128; /* Red zone */
/* Calculate the virtual rsp */
uintptr_t _v_rsp = tf->rsp;
_v_rsp &= ~0xF; /* Align */
_v_rsp -= 128; /* Red zone */
uint64_t *vRsp = (uint64_t *)(_v_rsp - sizeof(StackInfo));
vRsp--; /* Alignment */
vRsp--; /* Handler Address */
assert(!((uintptr_t)vRsp & 0xF));
/* Add the stack info */
StackInfo si{};
CPU::x64::fxsave(&si.fx);
si.tf = *tf;
si.GSBase = CPU::x64::rdmsr(CPU::x64::MSR_GS_BASE);
si.FSBase = CPU::x64::rdmsr(CPU::x64::MSR_FS_BASE);
si.ShadowGSBase = CPU::x64::rdmsr(CPU::x64::MSR_SHADOW_GS_BASE);
si.SignalMask = ((TCB *)thread)->Signals.Mask.to_ulong();
si.Compatibility = ((PCB *)ctx)->Info.Compatibility;
debug("gs: %#lx fs: %#lx shadow: %#lx",
si.GSBase, si.FSBase, si.ShadowGSBase);
/* Copy the stack info */
uint64_t *pRsp = (uint64_t *)(paRsp - sizeof(StackInfo));
memcpy(pRsp, &si, sizeof(StackInfo));
/* Set the handler address */
pRsp--; /* Alignment */
pRsp--;
*pRsp = uint64_t(sa[sigI.sig].sa_handler.Handler);
assert(!((uintptr_t)pRsp & 0xF));
int cSig = LinuxSig() ? ConvertSignalToLinux((signal_t)sigI.sig) : sigI.sig;
#ifdef DEBUG
DumpData("Stack Data", (void *)pRsp,
paRsp - uint64_t(pRsp));
debug("initial stack tf->rsp: %#lx after: %#lx",
tf->rsp, uint64_t(vRsp));
debug("sig: %d -> %d", sigI.sig, cSig);
#endif
tf->rsp = uint64_t(vRsp);
tf->rip = uint64_t(TrampAddr);
/* void func(int signo); */
/* void func(int signo, siginfo_t *info, void *context); */
tf->rdi = cSig;
if (sa[sigI.sig].Flags & SA_SIGINFO)
{
fixme("SA_SIGINFO not implemented");
siginfo_t *info = 0;
void *context = 0;
tf->rsi = uint64_t(info);
tf->rdx = uint64_t(context);
tf->rcx = 0;
tf->r8 = 0;
tf->r9 = 0;
}
else
{
tf->rsi = 0;
tf->rdx = 0;
tf->rcx = 0;
tf->r8 = 0;
tf->r9 = 0;
}
((TCB *)thread)->Signals.Mask = sa[sigI.sig].Mask;
assert(TrampAddr != nullptr);
return true;
}
void Signal::RestoreHandleSignal(SyscallsFrame *sf, void *thread)
{
debug("Restoring signal handler");
SmartLock(SignalLock);
gsTCB *gs = (gsTCB *)CPU::x64::rdmsr(CPU::x64::MSR_GS_BASE);
uint64_t *sp = (uint64_t *)((PCB *)ctx)->PageTable->Get(gs->TempStack);
sp++; /* Alignment */
sp++; /* Handler Address */
assert(!((uintptr_t)sp & 0xF));
StackInfo *si = (StackInfo *)sp;
assert(si != nullptr);
sf->r15 = si->tf.r15;
sf->r14 = si->tf.r14;
sf->r13 = si->tf.r13;
sf->r12 = si->tf.r12;
sf->r11 = si->tf.r11;
sf->r10 = si->tf.r10;
sf->r9 = si->tf.r9;
sf->r8 = si->tf.r8;
sf->bp = si->tf.rbp;
sf->di = si->tf.rdi;
sf->si = si->tf.rsi;
sf->dx = si->tf.rdx;
sf->cx = si->tf.rcx;
sf->bx = si->tf.rbx;
sf->ax = si->tf.rax;
sf->Flags = si->tf.rflags.raw;
sf->ReturnAddress = si->tf.rip;
gs->TempStack = (void *)si->tf.rsp;
((TCB *)thread)->Signals.Mask = si->SignalMask;
CPU::x64::fxrstor(&si->fx);
CPU::x64::wrmsr(CPU::x64::MSR_GS_BASE, si->ShadowGSBase);
CPU::x64::wrmsr(CPU::x64::MSR_FS_BASE, si->FSBase);
CPU::x64::wrmsr(CPU::x64::MSR_SHADOW_GS_BASE, si->GSBase);
debug("gs: %#lx fs: %#lx shadow: %#lx",
si->GSBase, si->FSBase, si->ShadowGSBase);
// ((PCB *)ctx)->GetContext()->Yield();
// __builtin_unreachable();
/* Return because we will restore at sysretq */
}
int Signal::SetAction(signal_t sig, const SignalAction *act)
{
SmartLock(SignalLock);

4
Kernel/tasking/task.cpp
View File

@ -222,12 +222,12 @@ namespace Tasking
TCB *Task::CreateThread(PCB *Parent, IP EntryPoint,
const char **argv, const char **envp,
const std::vector<AuxiliaryVector> &auxv,
TaskArchitecture arch, TaskCompatibility Compatibility,
TaskArchitecture _arch, TaskCompatibility Compatibility,
bool ThreadNotReady)
{
SmartLock(TaskingLock);
return new TCB(this, Parent, EntryPoint,
argv, envp, auxv, arch,
argv, envp, auxv, _arch,
Compatibility, ThreadNotReady);
}

20
Kernel/tasking/thread.cpp
View File

@ -485,9 +485,9 @@ namespace Tasking
#if defined(__amd64__)
this->ShadowGSBase =
CPU::x64::rdmsr(CPU::x64::MSRID::MSR_SHADOW_GS_BASE);
this->GSBase = CPU::x64::rdmsr(CPU::x64::MSRID::MSR_GS_BASE);
this->FSBase = CPU::x64::rdmsr(CPU::x64::MSRID::MSR_FS_BASE);
CPU::x86::rdmsr(CPU::x86::MSRID::MSR_SHADOW_GS_BASE);
this->GSBase = CPU::x86::rdmsr(CPU::x86::MSRID::MSR_GS_BASE);
this->FSBase = CPU::x86::rdmsr(CPU::x86::MSRID::MSR_FS_BASE);
this->Registers.cs = GDT_KERNEL_CODE;
this->Registers.ss = GDT_KERNEL_DATA;
this->Registers.rflags.AlwaysOne = 1;
@ -498,7 +498,7 @@ namespace Tasking
POKE(uintptr_t, this->Registers.rsp) = (uintptr_t)ThreadDoExit;
#elif defined(__i386__)
this->Registers.cs = GDT_KERNEL_CODE;
this->Registers.r3_ss = GDT_KERNEL_DATA;
this->Registers.ss = GDT_KERNEL_DATA;
this->Registers.eflags.AlwaysOne = 1;
this->Registers.eflags.IF = 1;
this->Registers.eflags.ID = 1;
@ -520,7 +520,13 @@ namespace Tasking
this->ctx->va.MapTo(gst, this->Parent->PageTable);
gsTCB *gsT = (gsTCB *)gst.PhysicalAddress;
#ifdef DEBUG
#if defined(__amd64__)
gsT->__stub = 0xFFFFFFFFFFFFFFFF;
#elif defined(__i386__)
gsT->__stub = 0xFFFFFFFF;
#elif defined(__aarch64__)
gsT->__stub = 0xFFFFFFFFFFFFFFFF;
#endif
#endif
gsT->ScPages = TO_PAGES(STACK_SIZE);
@ -552,7 +558,7 @@ namespace Tasking
this->SetupUserStack_x86_64(argv, envp, auxv, Compatibility);
#elif defined(__i386__)
this->Registers.cs = GDT_USER_CODE;
this->Registers.r3_ss = GDT_USER_DATA;
this->Registers.ss = GDT_USER_DATA;
this->Registers.eflags.AlwaysOne = 1;
this->Registers.eflags.IF = 1;
this->Registers.eflags.ID = 1;
@ -562,9 +568,9 @@ namespace Tasking
is exited or we are going to get
an exception. */
this->SetupUserStack_x86_32(argv, envp, auxv);
this->SetupUserStack_x86_32(argv, envp, auxv, Compatibility);
#elif defined(__aarch64__)
this->SetupUserStack_aarch64(argv, envp, auxv);
this->SetupUserStack_aarch64(argv, envp, auxv, Compatibility);
#endif
#ifdef DEBUG_TASKING
DumpData(this->Name, this->Stack, STACK_SIZE);