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refactor: Fix build on i386
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Signed-off-by: EnderIce2 <enderice2@protonmail.com>
This commit is contained in:
@ -23,13 +23,13 @@
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#include <cpu/x86/cpuid_intel.hpp>
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#include <cpu/x86/cpuid_amd.hpp>
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#include <cpu/x86/x32/cr.hpp>
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#include <cpu/x86/x32/msr.hpp>
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#include <cpu/x86/x64/cr.hpp>
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#include <cpu/x86/x64/msr.hpp>
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#include <cpu/x86/exceptions.hpp>
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#include <cpu/x86/interrupts.hpp>
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#include <cpu/signatures.hpp>
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#include <cpu/x86/msr.hpp>
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#include <cpu/membar.hpp>
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#include <assert.h>
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#include <cstring>
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/**
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@ -211,6 +211,41 @@ namespace CPU
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/** @brief Get CPU counter value. */
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uint64_t Counter();
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namespace x86
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{
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nsa static inline void fxsave(void *FXSaveArea)
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{
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assert(FXSaveArea != nullptr);
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#if defined(__amd64__)
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asmv("fxsaveq (%0)"
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:
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: "r"(FXSaveArea)
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: "memory");
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#elif defined(__i386__)
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asmv("fxsave (%0)"
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:
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: "r"(FXSaveArea)
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: "memory");
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#endif
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}
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nsa static inline void fxrstor(void *FXRstorArea)
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{
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assert(FXRstorArea != nullptr);
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#if defined(__amd64__)
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asmv("fxrstorq (%0)"
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:
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: "r"(FXRstorArea)
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: "memory");
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#elif defined(__i386__)
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asmv("fxrstor (%0)"
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:
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: "r"(FXRstorArea)
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: "memory");
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#endif
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}
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}
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namespace x32
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{
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/**
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@ -294,24 +329,83 @@ namespace CPU
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struct TrapFrame
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{
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uint32_t edi; // Destination index for string operations
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uint32_t esi; // Source index for string operations
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uint32_t ebp; // Base Pointer (meant for stack frames)
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uint32_t esp; // Stack Pointer
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uint32_t ebx; // Base
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uint32_t edx; // Data (commonly extends the A register)
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uint32_t ecx; // Counter
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uint32_t eax; // Accumulator
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uint32_t edi; /* Destination index for string operations */
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uint32_t esi; /* Source index for string operations */
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uint32_t ebp; /* Base Pointer (meant for stack frames) */
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uint32_t ebx; /* Base */
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uint32_t edx; /* Data (commonly extends the A register) */
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uint32_t ecx; /* Counter */
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uint32_t eax; /* Accumulator */
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uint32_t InterruptNumber; // Interrupt Number
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uint32_t ErrorCode; // Error code
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uint32_t InterruptNumber; /* Interrupt Number */
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uint32_t ErrorCode; /* Error code */
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uint32_t eip; // Instruction Pointer
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uint32_t cs; // Code Segment
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EFLAGS eflags; // Register Flags
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uint32_t eip; /* Instruction Pointer */
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uint32_t cs; /* Code Segment */
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EFLAGS eflags; /* Register Flags */
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uint32_t esp; /* Stack Pointer */
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uint32_t ss; /* Stack Segment */
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};
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uint32_t r3_esp; // Stack Pointer
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uint32_t r3_ss; // Stack Segment
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struct SchedulerFrame
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{
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uint32_t ppt; /* Process Page Table */
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uint32_t opt; /* Original Page Table */
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uint32_t ebp; /* Base Pointer (meant for stack frames) */
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uint32_t edi; /* Destination index for string operations */
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uint32_t esi; /* Source index for string operations */
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uint32_t edx; /* Data (commonly extends the A register) */
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uint32_t ecx; /* Counter */
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uint32_t ebx; /* Base */
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uint32_t eax; /* Accumulator */
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uint32_t InterruptNumber; /* Interrupt Number */
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uint32_t ErrorCode; /* Error code */
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uint32_t eip; /* Instruction Pointer */
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uint32_t cs; /* Code Segment */
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EFLAGS eflags; /* Register Flags */
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uint32_t esp; /* Stack Pointer */
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uint32_t ss; /* Stack Segment */
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};
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struct ExceptionFrame
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{
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uint32_t cr0; /* Control Register 0 (system control) */
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uint32_t cr2; /* Control Register 2 (page fault linear address) */
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uint32_t cr3; /* Control Register 3 (page directory base) */
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uint32_t cr4; /* Control Register 4 (system control) */
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uint32_t cr8; /* Control Register 8 (task priority) */
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uint32_t dr0; /* Debug Register */
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uint32_t dr1; /* Debug Register */
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uint32_t dr2; /* Debug Register */
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uint32_t dr3; /* Debug Register */
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uint32_t dr6; /* Debug Register */
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uint32_t dr7; /* Debug Register */
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uint32_t gs; /* General purpose */
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uint32_t fs; /* General purpose */
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uint32_t es; /* Extra Segment */
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uint32_t ds; /* Data Segment */
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uint32_t ebp; /* Base Pointer (meant for stack frames) */
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uint32_t edi; /* Destination index for string operations */
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uint32_t esi; /* Source index for string operations */
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uint32_t edx; /* Data (commonly extends the A register) */
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uint32_t ecx; /* Counter */
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uint32_t ebx; /* Base */
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uint32_t eax; /* Accumulator */
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uint32_t InterruptNumber; /* Interrupt Number */
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uint32_t ErrorCode; /* Error code */
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uint32_t eip; /* Instruction Pointer */
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uint32_t cs; /* Code Segment */
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EFLAGS eflags; /* Register Flags */
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uint32_t esp; /* Stack Pointer */
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uint32_t ss; /* Stack Segment */
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};
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typedef union DR6
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@ -319,27 +413,27 @@ namespace CPU
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struct
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{
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/** @brief Breakpoint #0 Condition Detected */
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uint64_t B0 : 1;
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uint32_t B0 : 1;
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/** @brief Breakpoint #1 Condition Detected */
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uint64_t B1 : 1;
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uint32_t B1 : 1;
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/** @brief Breakpoint #2 Condition Detected */
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uint64_t B2 : 1;
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uint32_t B2 : 1;
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/** @brief Breakpoint #3 Condition Detected */
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uint64_t B3 : 1;
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uint32_t B3 : 1;
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/** @brief Reserved */
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uint64_t Reserved0 : 8;
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uint32_t Reserved0 : 8;
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/** @brief Reserved */
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uint64_t Reserved1 : 1;
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uint32_t Reserved1 : 1;
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/** @brief Breakpoint Debug Access Detected */
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uint64_t BD : 1;
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uint32_t BD : 1;
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/** @brief Breakpoint Single Step */
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uint64_t BS : 1;
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uint32_t BS : 1;
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/** @brief Breakpoint Task Switch */
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uint64_t BT : 1;
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uint32_t BT : 1;
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/** @brief Reserved */
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uint64_t Reserved2 : 15;
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uint32_t Reserved2 : 15;
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};
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uint64_t raw;
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uint32_t raw;
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} DR6;
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typedef union DR7
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@ -978,32 +1072,6 @@ namespace CPU
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cpuid(0x0, &eax, &ebx, &ecx, &edx);
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return eax;
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}
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nsa static inline void fxsave(void *FXSaveArea)
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{
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#ifdef __amd64__
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if (!FXSaveArea || FXSaveArea >= (char *)0xfffffffffffff000)
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return;
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asmv("fxsaveq (%0)"
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:
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: "r"(FXSaveArea)
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: "memory");
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#endif
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}
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nsa static inline void fxrstor(void *FXRstorArea)
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{
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#ifdef __amd64__
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if (!FXRstorArea || FXRstorArea >= (char *)0xfffffffffffff000)
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return;
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asmv("fxrstorq (%0)"
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:
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: "r"(FXRstorArea)
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: "memory");
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#endif
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}
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}
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namespace aarch64
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