diff --git a/Architecture/amd64/MultipleAPICDescriptionTable.cpp b/Architecture/amd64/MultipleAPICDescriptionTable.cpp index 4974e7f0..9bb2e5c2 100644 --- a/Architecture/amd64/MultipleAPICDescriptionTable.cpp +++ b/Architecture/amd64/MultipleAPICDescriptionTable.cpp @@ -3,10 +3,13 @@ #include #include +#include "../../kernel.h" + namespace ACPI { MADT::MADT(ACPI::MADTHeader *madt) { + CPUCores = 0; LAPICAddress = (LAPIC *)(uintptr_t)madt->LocalControllerAddress; for (uint8_t *ptr = (uint8_t *)(madt->Entries); (uintptr_t)(ptr) < (uintptr_t)(madt) + madt->Header.Length; @@ -19,7 +22,7 @@ namespace ACPI if (ptr[4] & 1) { lapic.push_back((LocalAPIC *)ptr); - trace("Local APIC %#llx (APIC %#llx) found.", lapic.back()->ACPIProcessorId, lapic.back()->APICId); + KPrint("Local APIC %d (APIC %d) found.", lapic.back()->ACPIProcessorId, lapic.back()->APICId); CPUCores++; } break; @@ -27,35 +30,36 @@ namespace ACPI case 1: { ioapic.push_back((MADTIOApic *)ptr); - trace("I/O APIC %#llx (Address %#llx) found.", ioapic.back()->APICID, ioapic.back()->Address); + KPrint("I/O APIC %d (Address %#lx) found.", ioapic.back()->APICID, ioapic.back()->Address); Memory::Virtual().Map((void *)(uintptr_t)ioapic.back()->Address, (void *)(uintptr_t)ioapic.back()->Address, Memory::PTFlag::RW | Memory::PTFlag::PCD); // Make sure that the address is mapped. break; } case 2: { iso.push_back((MADTIso *)ptr); - trace("ISO (IRQ:%#llx, BUS:%#llx, GSI:%#llx, %s/%s) found.", - iso.back()->IRQSource, iso.back()->BuSSource, iso.back()->GSI, - iso.back()->Flags & 0x00000004 ? "Active High" : "Active Low", - iso.back()->Flags & 0x00000100 ? "Edge Triggered" : "Level Triggered"); + KPrint("ISO (IRQ:%#lx, BUS:%#lx, GSI:%#lx, %s/%s) found.", + iso.back()->IRQSource, iso.back()->BuSSource, iso.back()->GSI, + iso.back()->Flags & 0x00000004 ? "Active High" : "Active Low", + iso.back()->Flags & 0x00000100 ? "Edge Triggered" : "Level Triggered"); break; } case 4: { nmi.push_back((MADTNmi *)ptr); - trace("NMI %#llx (lint:%#llx) found.", nmi.back()->processor, nmi.back()->lint); + KPrint("NMI %#lx (lint:%#lx) found.", nmi.back()->processor, nmi.back()->lint); break; } case 5: { LAPICAddress = (LAPIC *)ptr; - trace("APIC found at %#llx", LAPICAddress); + KPrint("APIC found at %#lx", LAPICAddress); break; } } Memory::Virtual().Map((void *)LAPICAddress, (void *)LAPICAddress, Memory::PTFlag::RW | Memory::PTFlag::PCD); // I should map more than one page? } - trace("Total CPU cores: %d", CPUCores); + CPUCores--; // We start at 0 (BSP) and end at 11 (APs), so we have 12 cores. + KPrint("Total CPU cores: %d", CPUCores + 1); } MADT::~MADT() diff --git a/Architecture/amd64/acpi.hpp b/Architecture/amd64/acpi.hpp index 346892f4..f849dace 100644 --- a/Architecture/amd64/acpi.hpp +++ b/Architecture/amd64/acpi.hpp @@ -240,7 +240,7 @@ namespace ACPI Vector nmi; Vector lapic; struct LAPIC *LAPICAddress; - uint8_t CPUCores; + uint16_t CPUCores; MADT(ACPI::MADTHeader *madt); ~MADT(); diff --git a/Architecture/amd64/cpu/SymmetricMultiprocessing.cpp b/Architecture/amd64/cpu/SymmetricMultiprocessing.cpp index 2d16178c..c91073ef 100644 --- a/Architecture/amd64/cpu/SymmetricMultiprocessing.cpp +++ b/Architecture/amd64/cpu/SymmetricMultiprocessing.cpp @@ -121,6 +121,7 @@ namespace SMP return; } for (uint8_t i = 0; i < ((ACPI::MADT *)madt)->CPUCores; i++) + { if ((((APIC::APIC *)Interrupts::apic)->Read(APIC::APIC::APIC_ID) >> 24) != ((ACPI::MADT *)madt)->lapic[i]->ACPIProcessorId) { ((APIC::APIC *)Interrupts::apic)->Write(APIC::APIC::APIC_ICRHI, (((ACPI::MADT *)madt)->lapic[i]->APICId << 24)); @@ -151,5 +152,8 @@ namespace SMP trace("CPU %d loaded.", ((ACPI::MADT *)madt)->lapic[i]->APICId); CPUEnabled = false; } + else + KPrint("CPU %d is the BSP", ((ACPI::MADT *)madt)->lapic[i]->APICId); + } } }