mirror of
https://github.com/Fennix-Project/Drivers.git
synced 2025-05-25 22:14:31 +00:00
636 lines
11 KiB
C++
636 lines
11 KiB
C++
/*
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This file is part of Fennix Drivers.
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Fennix Drivers is free software: you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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Fennix Drivers is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Fennix Drivers. If not, see <https://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <types.h>
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#ifdef __cplusplus
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struct StreamDescriptor
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{
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/** Control */
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uint32_t CTL : 24;
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/** Status */
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uint8_t STS;
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/** Link Position in Current Buffer */
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uint32_t LPIB;
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/** Cyclic Buffer Length */
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uint32_t CBL;
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/** Last Valid Index */
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uint16_t LVI;
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/** Reserved */
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uint8_t Rsvd0[2];
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/** FIFO Size */
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uint16_t FIFOD;
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/** Format */
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uint16_t FMT;
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/** Reserved */
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uint8_t Rsvd1[4];
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/** Buffer Descriptor List Pointer - Lower */
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uint32_t BDPL;
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/** Buffer Descriptor List Pointer - Upper */
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uint32_t BDPU;
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} __attribute__((packed));
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struct ControllerRegisters
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{
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uint16_t GCAP;
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uint8_t VMIN;
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uint8_t VMJ;
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uint16_t OUTPAY;
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uint16_t INPAY;
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uint32_t GCTL;
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uint16_t WAKEEN;
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uint16_t WAKESTS;
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uint16_t GSTS;
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uint8_t Rsvd0[6];
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uint16_t OUTSTRMPAY;
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uint16_t INSTRMPAY;
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uint8_t Rsvd1[4];
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uint32_t INTCTL;
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uint32_t INTSTS;
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uint8_t Rsvd2[8];
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uint32_t WALCLK;
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uint8_t Rsvd3[4];
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uint32_t SSYNC;
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uint8_t Rsvd4[4];
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uint32_t CORBLBASE;
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uint32_t CORBUBASE;
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uint16_t CORBWP;
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uint16_t CORBRP;
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uint8_t CORBCTL;
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uint8_t CORBSTS;
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uint8_t CORBSIZE;
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uint8_t Rsvd5;
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uint32_t RIRBLBASE;
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uint32_t RIRBUBASE;
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uint16_t RIRBWP;
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uint16_t RINTCNT;
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uint8_t RIRBCTL;
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uint8_t RIRBSTS;
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uint8_t RIRBSIZE;
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uint8_t Rsvd6;
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uint32_t ICOI;
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uint32_t ICII;
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uint16_t ICIS;
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uint8_t Rsvd7[6];
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uint32_t DPIBLBASE;
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uint32_t DPIBUBASE;
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uint8_t Rsvd8[8];
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StreamDescriptor SD[];
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} __attribute__((packed));
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/* Not working as expected */
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struct __ControllerRegisters
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{
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/** Global Capabilities */
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union
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{
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struct
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{
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/** 64 Bit Address Supported
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*
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* 0 = 32-bit addressing
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* 1 = 64-bit addressing
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*/
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uint16_t _64OK : 1;
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/** Number of Serial Data Out Signals
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*
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* 00 = 1 SDO
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* 01 = 2 SDOs
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* 10 = 4 SDOs
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* 11 = Reserved
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*/
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uint16_t NSDO : 2;
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/** Number of Bidirectional Streams Supported
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*
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* 00000b = No bidirectional streams supported
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* 00001b = 1 bidirectional stream supported
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* ...
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* 11110b = 30 bidirectional streams supported
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*/
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uint16_t BSS : 5;
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/** Number of Input Streams Supported
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*
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* 0000b = No input streams supported
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* 0001b = 1 input stream supported
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* ...
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* 1111b = 15 input streams supported
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*/
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uint16_t ISS : 4;
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/** Number of Output Streams Supported
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*
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* 0000b = No output streams supported
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* 0001b = 1 output stream supported
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* ...
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* 1111b = 15 output streams supported
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*/
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uint16_t OSS : 4;
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} __attribute__((packed));
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uint16_t Raw;
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} GCAP;
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/** Minor Version */
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uint8_t VMIN;
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/** Major Version */
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uint8_t VMJ;
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/** Output Payload Capability
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*
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* 00h = 0 Words
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* 01h = 1 Word payload
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* ...
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* FFh = 255h Word payload
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*/
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uint16_t OUTPAY;
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/** Input Payload Capability
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*
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* 00h = 0 Words
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* 01h = 1 Word payload
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* ...
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* FFh = 255h Word payload
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*/
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uint16_t INPAY;
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/** Global Control */
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union
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{
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struct
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{
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/** Controller Reset
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*
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* 0 = Reset
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* 1 = Normal Operation
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*/
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uint32_t CRST : 1;
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/** Flush Control
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*
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* 0 = Idle
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* 1 = Flush
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*/
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uint32_t FCNTRL : 1;
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/** Reserved */
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uint32_t RsvdP0 : 6;
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/** Accept Unsolicited Response Enable
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*
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* 0 = Disabled
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* 1 = Enabled
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*/
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uint32_t UNSOL : 1;
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/** Reserved */
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uint32_t RsvdP1 : 23;
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} __attribute__((packed));
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uint32_t Raw;
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} GCTL;
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/** Wake Enable */
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union
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{
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struct
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{
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/** SDIN Wake Enable Flags */
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uint16_t SDIWEN : 15;
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/** Reserved */
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uint16_t RsvdP0 : 1;
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} __attribute__((packed));
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uint16_t Raw;
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} WAKEEN;
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/** Wake Status */
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union
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{
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struct
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{
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/** SDIN State Change Status Flags */
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uint16_t SDIWAKE : 15;
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/** Reserved */
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uint16_t RsvdZ0 : 1;
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} __attribute__((packed));
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uint16_t Raw;
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} WAKESTS;
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/** Global Status */
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union
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{
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struct
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{
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uint16_t RsvdZ0 : 1;
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uint16_t FSTS : 1;
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uint16_t RsvdZ1 : 14;
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} __attribute__((packed));
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uint16_t Raw;
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} GSTS;
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/** Reserved */
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uint8_t Rsvd0[6];
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/** Output Stream Payload Capability */
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uint16_t OUTSTRMPAY;
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/** Input Stream Payload Capability */
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uint16_t INSTRMPAY;
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/** Reserved */
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uint8_t Rsvd1[4];
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/** Interrupt Control */
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union
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{
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struct
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{
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/** Stream Interrupt Enable
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*
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* Bit 0 = Input Stream 0
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* Bit 1 = Input Stream 1
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* Bit 2 = Output Stream 0
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* Bit 3 = Output Stream 1
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* Bit 4 = Output Stream 2
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* Bit 5 = Bidirectional Stream 0
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* Bits 6-28 = Reserved
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*/
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uint32_t SIE : 30;
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/** Controller Interrupt Enable */
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uint32_t CIE : 1;
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/** Global Interrupt Enable */
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uint32_t GIE : 1;
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} __attribute__((packed));
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uint32_t Raw;
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} INTCTL;
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/** Interrupt Status */
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union
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{
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struct
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{
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/** Stream Interrupt Status */
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uint32_t SIS : 30;
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/** Controller Interrupt Status */
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uint32_t CIS : 1;
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/** Global Interrupt Status */
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uint32_t GIS : 1;
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} __attribute__((packed));
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uint32_t Raw;
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} INTSTS;
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/** Reserved */
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uint8_t Rsvd2[8];
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/** Wall Clock Counter */
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uint32_t WALCLK;
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/** Reserved */
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uint8_t Rsvd3[4];
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/** Stream Synchronization */
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union
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{
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struct
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{
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/** Stream Synchronization Bits */
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uint32_t SSYNC : 30;
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/** Reserved */
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uint32_t RsvdP0 : 2;
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} __attribute__((packed));
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uint32_t Raw;
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} SSYNC;
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/** Reserved */
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uint8_t Rsvd4[4];
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/** CORB Lower Base Address */
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union
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{
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struct
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{
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/** CORB Lower Base Unimplemented Bits */
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uint32_t Unimplemented : 7;
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/** CORB Lower Base Address */
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uint32_t CORBLBASE : 25;
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} __attribute__((packed));
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uint32_t Raw;
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} CORBLBASE;
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/** CORB Upper Base Address */
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uint32_t CORBUBASE;
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/** CORB Write Pointer */
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union
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{
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struct
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{
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/** CORB Write Pointer */
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uint16_t CORBWP : 8;
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/** Reserved */
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uint16_t RsvdP0 : 8;
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} __attribute__((packed));
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uint16_t Raw;
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} CORBWP;
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/** CORB Read Pointer */
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union
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{
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struct
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{
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/** CORB Read Pointer */
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uint16_t CORBRP : 8;
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/** Reserved */
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uint16_t RsvdP0 : 7;
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/** CORB Read Pointer Reset */
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uint16_t CORBRPRST : 1;
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} __attribute__((packed));
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uint16_t Raw;
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} CORBRP;
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/** CORB Control */
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union
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{
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struct
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{
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/** CORB Memory Error Interrupt Enable */
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uint8_t CMEIE : 1;
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/** Enable CORB DMA Engine
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*
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* 0 = DMA Stop
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* 1 = DMA Run
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*
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* @note Must read the value back.
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*/
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uint8_t CORBRUN : 1;
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/** Reserved */
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uint8_t RsvdP0 : 6;
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} __attribute__((packed));
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uint8_t Raw;
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} CORBCTL;
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/** CORB Status */
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union
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{
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struct
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{
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/** CORB Memory Error Indication */
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uint8_t CMEI : 1;
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/** Reserved */
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uint8_t RsvdZ0 : 7;
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} __attribute__((packed));
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uint8_t Raw;
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} CORBSTS;
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/** CORB Size */
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union
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{
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struct
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{
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/** CORB Size
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*
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* 00b = 2 entries
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* 01b = 16 entries
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* 10b = 256 entries
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* 11b = Reserved
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*/
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uint8_t CORBSIZE : 2;
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/** Reserved */
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uint8_t RsvdP0 : 2;
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/** CORB Size Capability
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*
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* 0001b = 2 entries
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* 0010b = 16 entries
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* 0100b = 256 entries
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* 1000b = Reserved
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*/
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uint8_t CORBSZCAP : 4;
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} __attribute__((packed));
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uint8_t Raw;
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} CORBSIZE;
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/** Reserved */
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uint8_t Rsvd5;
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/** RIRB Lower Base Address */
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union
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{
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struct
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{
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/** RIRB Lower Base Unimplemented Bits */
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uint32_t Unimplemented : 7;
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/** RIRB Lower Base Address */
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uint32_t RIRBLBASE : 25;
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} __attribute__((packed));
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uint32_t Raw;
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} RIRBLBASE;
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/** RIRB Upper Base Address */
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uint32_t RIRBUBASE;
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/** RIRB Write Pointer */
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union
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{
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struct
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{
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/** RIRB Write Pointer */
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uint16_t RIRBWP : 8;
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/** Reserved */
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uint16_t RsvdP0 : 7;
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/** RIRB Write Pointer Reset */
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uint16_t RIRBWPRST : 1;
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} __attribute__((packed));
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uint16_t Raw;
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} RIRBWP;
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/** Response Interrupt Count */
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union
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{
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struct
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{
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/** N Response Interrupt Count
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*
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* 00000001b = 1 Response sent to RIRB
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* ...
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* 11111111b = 255 Responses sent to RIRB
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* 00000000b = 256 Response sent to RIRB
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*/
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uint16_t RINTCNT : 8;
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/** Reserved */
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uint16_t RsvdP0 : 8;
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} __attribute__((packed));
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uint16_t Raw;
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} RINTCNT;
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/** RIRB Control */
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union
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{
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struct
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{
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/** Response Interrupt Control
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*
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* 0 = Disable Interrupt
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* 1 = Generate an interrupt after N responses are sent to the RIRB
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*/
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uint8_t RINTCTL : 1;
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/** RIRB DMA Enable
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*
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* 0 = DMA Stop
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* 1 = DMA Run
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*/
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uint8_t RIRBDMAEN : 1;
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/** Response Overrun Interrupt Control */
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uint8_t RIRBOIC : 1;
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/** Reserved */
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uint8_t RsvdP0 : 5;
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} __attribute__((packed));
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uint8_t Raw;
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} RIRBCTL;
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/** RIRB Status */
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union
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{
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struct
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{
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/** Response Interrupt */
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uint8_t RINTFL : 1;
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/** Reserved */
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uint8_t RsvdZ0 : 1;
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/** Response Overrun Interrupt Status */
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uint8_t RIRBOIS : 1;
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/** Reserved */
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uint8_t RsvdZ1 : 5;
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} __attribute__((packed));
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uint8_t Raw;
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} RIRBSTS;
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/** RIRB Size */
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union
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{
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struct
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{
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/** RIRB Size
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*
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* 00b = 2 entries
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* 01b = 16 entries
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* 10b = 256 entries
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* 11b = Reserved
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*/
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uint8_t RIRBSIZE : 2;
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/** Reserved */
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uint8_t RsvdP0 : 2;
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/** RIRB Size Capability
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*
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* 0001b = 2 entries
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* 0010b = 16 entries
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* 0100b = 256 entries
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* 1000b = Reserved
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*/
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uint8_t RIRBSZCAP : 4;
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} __attribute__((packed));
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uint8_t Raw;
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} RIRBSIZE;
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/** Reserved */
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uint8_t Rsvd6;
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/** Immediate Command Output Interface */
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uint32_t ICOI;
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/** Immediate Command Input Interface */
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uint32_t ICII;
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/** Immediate Command Status */
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uint16_t ICIS;
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/** Reserved */
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uint8_t Rsvd7[6];
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/** DMA Position Buffer Lower Base */
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union
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{
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struct
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{
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/** DMA Position Buffer Enable */
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uint32_t DPBEN : 1;
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/** Reserved */
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uint32_t RsvdZ0 : 6;
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/** DMA Position Lower Base Address */
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uint32_t DPLBASE : 25;
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} __attribute__((packed));
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uint32_t Raw;
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} DPIBLBASE;
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/** DMA Position Buffer Upper Base */
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uint32_t DPIBUBASE;
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/** Reserved */
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uint8_t Rsvd8[8];
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|
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StreamDescriptor SD[];
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} __attribute__((packed));
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#endif
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EXTERNC int cxx_Panic();
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EXTERNC int cxx_Probe();
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EXTERNC int cxx_Initialize();
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EXTERNC int cxx_Finalize();
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