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Updated PCI header

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This commit is contained in:
Alex 2023-03-08 05:47:40 +02:00
parent 8692ed4d1b
commit aa6b6d0285
Signed by untrusted user who does not match committer: enderice2
GPG Key ID: EACC3AD603BAB4DD
1 changed files with 62 additions and 6 deletions
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68
include/pci.h
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@ -55,18 +55,74 @@ struct PCIHeader0
uint32_t BAR3; uint32_t BAR3;
uint32_t BAR4; uint32_t BAR4;
uint32_t BAR5; uint32_t BAR5;
uint32_t CardbusCISPtr; uint32_t CardbusCISPointer;
uint16_t SubsystemVendorID; uint16_t SubsystemVendorID;
uint16_t SubsystemID; uint16_t SubsystemID;
uint32_t ExpansionROMBaseAddr; uint32_t ExpansionROMBaseAddress;
uint8_t CapabilitiesPtr; uint8_t CapabilitiesPointer;
uint8_t Rsv0; uint8_t Reserved0;
uint16_t Rsv1; uint16_t Reserved1;
uint32_t Rsv2; uint32_t Reserved2;
uint8_t InterruptLine; uint8_t InterruptLine;
uint8_t InterruptPin; uint8_t InterruptPin;
uint8_t MinGrant; uint8_t MinGrant;
uint8_t MaxLatency; uint8_t MaxLatency;
}; };
struct PCIHeader1
{
PCIDeviceHeader Header;
uint32_t BAR0;
uint32_t BAR1;
uint8_t PrimaryBusNumber;
uint8_t SecondaryBusNumber;
uint8_t SubordinateBusNumber;
uint8_t SecondaryLatencyTimer;
uint8_t IOBase;
uint8_t IOLimit;
uint16_t SecondaryStatus;
uint16_t MemoryBase;
uint16_t MemoryLimit;
uint16_t PrefetchableMemoryBase;
uint16_t PrefetchableMemoryLimit;
uint32_t PrefetchableMemoryBaseUpper32;
uint32_t PrefetchableMemoryLimitUpper32;
uint16_t IOBaseUpper16;
uint16_t IOLimitUpper16;
uint8_t CapabilitiesPointer;
uint8_t Reserved0;
uint16_t Reserved1;
uint32_t ExpansionROMBaseAddress;
uint8_t InterruptLine;
uint8_t InterruptPin;
uint16_t BridgeControl;
};
struct PCIHeader2
{
PCIDeviceHeader Header;
uint32_t CardbusSocketRegistersBaseAddress;
uint8_t CapabilitiesPointer;
uint8_t Reserved0;
uint16_t SecondaryStatus;
uint8_t PCIbusNumber;
uint8_t CardbusBusNumber;
uint8_t SubordinateBusNumber;
uint8_t CardbusLatencyTimer;
uint32_t MemoryBase0;
uint32_t MemoryLimit0;
uint32_t MemoryBase1;
uint32_t MemoryLimit1;
uint32_t IOBase0;
uint32_t IOLimit0;
uint32_t IOBase1;
uint32_t IOLimit1;
uint8_t InterruptLine;
uint8_t InterruptPin;
uint16_t BridgeControl;
uint16_t SubsystemVendorID;
uint16_t SubsystemID;
uint32_t LegacyBaseAddress;
};
#endif // !__FENNIX_API_PCI_H__ #endif // !__FENNIX_API_PCI_H__