mirror of
https://github.com/Fennix-Project/Kernel.git
synced 2025-05-28 15:34:33 +00:00
308 lines
9.8 KiB
C++
308 lines
9.8 KiB
C++
#include "apic.hpp"
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#include <memory.hpp>
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#include <uart.hpp>
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#include <cpu.hpp>
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#include <smp.hpp>
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#include <io.h>
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#include "../../../kernel.h"
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#include "../acpi.hpp"
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using namespace CPU::x64;
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namespace APIC
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{
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enum IOAPICRegisters
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{
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GetIOAPICVersion = 0x1
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};
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enum IOAPICFlags
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{
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ActiveHighLow = 2,
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EdgeLevel = 8
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};
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struct IOAPICVersion
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{
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uint8_t Version;
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uint8_t Reserved;
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uint8_t MaximumRedirectionEntry;
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uint8_t Reserved2;
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};
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// headache
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// https://www.amd.com/system/files/TechDocs/24593.pdf
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// https://www.naic.edu/~phil/software/intel/318148.pdf
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uint32_t APIC::Read(uint32_t Register)
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{
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debug("APIC::Read(%#lx) [x2=%d]", Register, x2APICSupported ? 1 : 0);
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if (x2APICSupported)
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{
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if (Register != APIC_ICRHI)
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return rdmsr((Register >> 4) + 0x800);
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else
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return rdmsr(0x30 + 0x800);
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}
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else
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{
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CPU::MemBar::Barrier();
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uint32_t ret = *((volatile uint32_t *)((uintptr_t)((ACPI::MADT *)PowerManager->GetMADT())->LAPICAddress + Register));
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CPU::MemBar::Barrier();
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return ret;
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}
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}
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void APIC::Write(uint32_t Register, uint32_t Value)
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{
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if (Register != APIC_EOI &&
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Register != APIC_TDCR &&
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Register != APIC_TIMER &&
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Register != APIC_TICR)
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debug("APIC::Write(%#lx, %#lx) [x2=%d]", Register, Value, x2APICSupported ? 1 : 0);
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if (x2APICSupported)
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{
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if (Register != APIC_ICRHI)
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wrmsr((Register >> 4) + 0x800, Value);
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else
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wrmsr(MSR_X2APIC_ICR, Value);
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}
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else
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{
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CPU::MemBar::Barrier();
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*((volatile uint32_t *)(((uintptr_t)((ACPI::MADT *)PowerManager->GetMADT())->LAPICAddress) + Register)) = Value;
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CPU::MemBar::Barrier();
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}
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}
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void APIC::IOWrite(uint64_t Base, uint32_t Register, uint32_t Value)
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{
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debug("APIC::IOWrite(%#lx, %#lx, %#lx)", Base, Register, Value);
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CPU::MemBar::Barrier();
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*((volatile uint32_t *)(((uintptr_t)Base))) = Register;
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CPU::MemBar::Barrier();
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*((volatile uint32_t *)(((uintptr_t)Base + 16))) = Value;
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CPU::MemBar::Barrier();
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}
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uint32_t APIC::IORead(uint64_t Base, uint32_t Register)
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{
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debug("APIC::IORead(%#lx, %#lx)", Base, Register);
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CPU::MemBar::Barrier();
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*((volatile uint32_t *)(((uintptr_t)Base))) = Register;
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CPU::MemBar::Barrier();
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uint32_t ret = *((volatile uint32_t *)(((uintptr_t)Base + 16)));
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CPU::MemBar::Barrier();
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return ret;
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}
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void APIC::EOI() { this->Write(APIC_EOI, 0); }
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void APIC::RedirectIRQs(int CPU)
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{
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debug("Redirecting IRQs...");
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for (int i = 0; i < 16; i++)
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this->RedirectIRQ(CPU, i, 1);
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debug("Redirecting IRQs completed.");
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}
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void APIC::IPI(uint8_t CPU, uint32_t InterruptNumber)
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{
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if (x2APICSupported)
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{
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wrmsr(MSR_X2APIC_ICR, ((uint64_t)CPU) << 32 | InterruptNumber);
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}
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else
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{
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InterruptNumber = (1 << 14) | InterruptNumber;
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this->Write(APIC_ICRHI, (CPU << 24));
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this->Write(APIC_ICRLO, InterruptNumber);
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}
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}
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uint32_t APIC::IOGetMaxRedirect(uint32_t APICID)
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{
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uint32_t TableAddress = (this->IORead((((ACPI::MADT *)PowerManager->GetMADT())->ioapic[APICID]->Address), GetIOAPICVersion));
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return ((IOAPICVersion *)&TableAddress)->MaximumRedirectionEntry;
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}
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void APIC::RawRedirectIRQ(uint8_t Vector, uint32_t GSI, uint16_t Flags, int CPU, int Status)
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{
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uint64_t Value = Vector;
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int64_t IOAPICTarget = -1;
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for (uint64_t i = 0; ((ACPI::MADT *)PowerManager->GetMADT())->ioapic[i] != 0; i++)
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if (((ACPI::MADT *)PowerManager->GetMADT())->ioapic[i]->GSIBase <= GSI)
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if (((ACPI::MADT *)PowerManager->GetMADT())->ioapic[i]->GSIBase + IOGetMaxRedirect(i) > GSI)
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{
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IOAPICTarget = i;
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break;
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}
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if (IOAPICTarget == -1)
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{
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error("No ISO table found for I/O APIC");
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return;
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}
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if (Flags & ActiveHighLow)
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Value |= (1 << 13);
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if (Flags & EdgeLevel)
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Value |= (1 << 15);
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if (!Status)
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Value |= (1 << 16);
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// Value |= (((uintptr_t)GetCPU(CPU)->Data->LAPIC.APICId) << 56);
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Value |= (((uintptr_t)0) << 56);
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uint32_t IORegister = (GSI - ((ACPI::MADT *)PowerManager->GetMADT())->ioapic[IOAPICTarget]->GSIBase) * 2 + 16;
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this->IOWrite(((ACPI::MADT *)PowerManager->GetMADT())->ioapic[IOAPICTarget]->Address, IORegister, (uint32_t)Value);
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this->IOWrite(((ACPI::MADT *)PowerManager->GetMADT())->ioapic[IOAPICTarget]->Address, IORegister + 1, (uint32_t)(Value >> 32));
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}
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void APIC::RedirectIRQ(int CPU, uint8_t IRQ, int Status)
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{
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for (uint64_t i = 0; i < ((ACPI::MADT *)PowerManager->GetMADT())->iso.size(); i++)
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if (((ACPI::MADT *)PowerManager->GetMADT())->iso[i]->IRQSource == IRQ)
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{
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debug("[ISO %d] Mapping to source IRQ%#d GSI:%#lx on CPU %d",
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i, ((ACPI::MADT *)PowerManager->GetMADT())->iso[i]->IRQSource, ((ACPI::MADT *)PowerManager->GetMADT())->iso[i]->GSI, CPU);
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this->RawRedirectIRQ(((ACPI::MADT *)PowerManager->GetMADT())->iso[i]->IRQSource + 0x20, ((ACPI::MADT *)PowerManager->GetMADT())->iso[i]->GSI, ((ACPI::MADT *)PowerManager->GetMADT())->iso[i]->Flags, CPU, Status);
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return;
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}
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debug("Mapping IRQ%d on CPU %d", IRQ, CPU);
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this->RawRedirectIRQ(IRQ + 0x20, IRQ, 0, CPU, Status);
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}
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APIC::APIC(int Core)
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{
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APIC_BASE BaseStruct = {.raw = rdmsr(MSR_APIC_BASE)};
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void *APICBaseAddress = (void *)(uint64_t)(BaseStruct.ApicBaseLo << 12u | BaseStruct.ApicBaseHi << 32u);
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trace("APIC Address: %#lx", APICBaseAddress);
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uint32_t rcx;
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cpuid(1, 0, 0, &rcx, 0);
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if (rcx & CPUID_FEAT_RCX_x2APIC)
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{
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// this->x2APICSupported = true;
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warn("x2APIC not supported yet.");
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// wrmsr(MSR_APIC_BASE, (rdmsr(MSR_APIC_BASE) | (1 << 11)) & ~(1 << 10));
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BaseStruct.EN = 1;
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wrmsr(MSR_APIC_BASE, BaseStruct.raw);
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}
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else
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{
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BaseStruct.EN = 1;
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wrmsr(MSR_APIC_BASE, BaseStruct.raw);
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}
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this->Write(APIC_TPR, 0x0);
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this->Write(APIC_SVR, this->Read(APIC_SVR) | 0x100); // 0x1FF or 0x100 ? on https://wiki.osdev.org/APIC is 0x100
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if (!this->x2APICSupported)
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{
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this->Write(APIC_DFR, 0xF0000000);
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this->Write(APIC_LDR, this->Read(APIC_ID));
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}
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ACPI::MADT *madt = (ACPI::MADT *)PowerManager->GetMADT();
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for (size_t i = 0; i < madt->nmi.size(); i++)
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{
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if (madt->nmi[i]->processor != 0xFF && Core != madt->nmi[i]->processor)
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return;
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uint32_t nmi = 0x402;
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if (madt->nmi[i]->flags & 2)
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nmi |= 1 << 13;
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if (madt->nmi[i]->flags & 8)
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nmi |= 1 << 15;
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if (madt->nmi[i]->lint == 0)
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this->Write(APIC_LINT0, nmi);
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else if (madt->nmi[i]->lint == 1)
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this->Write(APIC_LINT1, nmi);
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}
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}
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APIC::~APIC()
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{
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}
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void Timer::OnInterruptReceived(TrapFrame *Frame)
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{
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// fixme("APIC IRQ0 INTERRUPT RECEIVED ON CPU %d", rdmsr(MSR_FS_BASE));
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// UniversalAsynchronousReceiverTransmitter::UART(UniversalAsynchronousReceiverTransmitter::COM1).Write('\n');
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// UniversalAsynchronousReceiverTransmitter::UART(UniversalAsynchronousReceiverTransmitter::COM1).Write('H');
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// UniversalAsynchronousReceiverTransmitter::UART(UniversalAsynchronousReceiverTransmitter::COM1).Write('\n');
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}
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void Timer::OneShot(uint32_t Vector, uint64_t Miliseconds)
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{
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this->lapic->Write(APIC_TDCR, 0x03);
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LVTTimer timer = {0, 0, 0, 0, 0, 0, 0};
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timer.Vector = Vector;
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timer.TimerMode = 0;
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this->lapic->Write(APIC_TIMER, timer.raw);
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this->lapic->Write(APIC_TICR, (TicksIn10ms / 10) * Miliseconds);
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}
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Timer::Timer(APIC *apic) : Interrupts::Handler(IRQ0)
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{
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trace("Initializing APIC timer on CPU %d", GetCurrentCPU()->ID);
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this->lapic = apic;
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this->lapic->Write(APIC_TDCR, 0x3);
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int Count = 10000; /* µs */
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int Ticks = 1193180 / (Count / 100);
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int IOIn = inb(0x61);
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IOIn = (IOIn & 0xFD) | 1;
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outb(0x61, IOIn);
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outb(0x43, 178);
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outb(0x40, Ticks & 0xff);
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inb(0x60);
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outb(0x40, Ticks >> 8);
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this->lapic->Write(APIC_TICR, 0xFFFFFFFF);
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IOIn = inb(0x61);
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IOIn = (IOIn & 0xFC);
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outb(0x61, IOIn);
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IOIn |= 1;
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outb(0x61, IOIn);
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uint32_t Loop = 0;
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while ((inb(0x61) & 0x20) != 0)
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++Loop;
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this->lapic->Write(APIC_TIMER, 0x10000);
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outb(0x43, 0x28);
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outb(0x40, 0x0);
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outb(0x21, 0xFF);
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outb(0xA1, 0xFF);
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TicksIn10ms = 0xFFFFFFFF - this->lapic->Read(APIC_TCCR);
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LVTTimer timer = {0, 0, 0, 0, 0, 0, 0};
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timer.Vector = IRQ0;
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timer.Mask = 0;
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timer.TimerMode = 1;
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this->lapic->Write(APIC_TIMER, timer.raw);
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this->lapic->Write(APIC_TDCR, 0x3);
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this->lapic->Write(APIC_TICR, TicksIn10ms / 10);
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trace("APIC Timer (CPU %d): %d ticks in 10ms", GetCurrentCPU()->ID, TicksIn10ms / 10);
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KPrint("APIC Timer: \e8888FF%ld\eCCCCCC ticks in 10ms", TicksIn10ms / 10);
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}
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Timer::~Timer()
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{
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}
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}
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