mirror of
https://github.com/Fennix-Project/Kernel.git
synced 2025-05-27 15:04:33 +00:00
370 lines
9.3 KiB
C++
370 lines
9.3 KiB
C++
#include "gigabit.hpp"
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#include <net/net.hpp>
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#include <debug.h>
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#include <pci.hpp>
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#include <io.h>
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#include "../../DAPI.hpp"
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#include "../drv.hpp"
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using namespace PCI;
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namespace Gigabit
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{
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KernelAPI KAPI;
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PCIDeviceHeader *PCIBaseAddress;
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uint32_t CurrentPacket;
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BARData BAR;
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bool EEPROMAvailable;
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uint16_t RXCurrent;
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uint16_t TXCurrent;
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RXDescriptor *RX[E1000_NUM_RX_DESC];
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TXDescriptor *TX[E1000_NUM_TX_DESC];
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MediaAccessControl MAC;
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InternetProtocol::Version4 IP;
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void WriteCMD(uint16_t Address, uint32_t Value)
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{
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if (BAR.Type == 0)
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mmioout32(BAR.MemoryBase + Address, Value);
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else
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{
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outportl(BAR.IOBase, Address);
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outportl(BAR.IOBase + 4, Value);
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}
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}
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uint32_t ReadCMD(uint16_t Address)
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{
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if (BAR.Type == 0)
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return mmioin32(BAR.MemoryBase + Address);
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else
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{
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outportl(BAR.IOBase, Address);
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return inportl(BAR.IOBase + 0x4);
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}
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}
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uint32_t ReadEEPROM(uint8_t Address)
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{
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uint16_t Data = 0;
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uint32_t temp = 0;
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if (EEPROMAvailable)
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{
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WriteCMD(REG::EEPROM, (1) | ((uint32_t)(Address) << 8));
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while (!((temp = ReadCMD(REG::EEPROM)) & (1 << 4)))
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;
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}
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else
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{
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WriteCMD(REG::EEPROM, (1) | ((uint32_t)(Address) << 2));
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while (!((temp = ReadCMD(REG::EEPROM)) & (1 << 1)))
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;
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}
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Data = (uint16_t)((temp >> 16) & 0xFFFF);
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return Data;
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}
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MediaAccessControl GetMAC()
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{
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MediaAccessControl mac;
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if (EEPROMAvailable)
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{
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uint32_t temp;
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temp = ReadEEPROM(0);
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mac.Address[0] = temp & 0xff;
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mac.Address[1] = (uint8_t)(temp >> 8);
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temp = ReadEEPROM(1);
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mac.Address[2] = temp & 0xff;
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mac.Address[3] = (uint8_t)(temp >> 8);
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temp = ReadEEPROM(2);
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mac.Address[4] = temp & 0xff;
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mac.Address[5] = (uint8_t)(temp >> 8);
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}
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else
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{
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uint8_t *BaseMac8 = (uint8_t *)(BAR.MemoryBase + 0x5400);
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uint32_t *BaseMac32 = (uint32_t *)(BAR.MemoryBase + 0x5400);
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if (BaseMac32[0] != 0)
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for (int i = 0; i < 6; i++)
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mac.Address[i] = BaseMac8[i];
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else
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{
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error("No MAC address found.");
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return MediaAccessControl();
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}
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}
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return mac;
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}
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void InitializeRX()
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{
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debug("Initializing RX...");
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uintptr_t Ptr = (uintptr_t)KAPI.Memory.RequestPage((((sizeof(RXDescriptor) * E1000_NUM_RX_DESC + 16)) / KAPI.Memory.PageSize) + 1);
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for (int i = 0; i < E1000_NUM_RX_DESC; i++)
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{
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RX[i] = (RXDescriptor *)(Ptr + i * 16);
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RX[i]->Address = (uint64_t)(uintptr_t)KAPI.Memory.RequestPage(((8192 + 16) / KAPI.Memory.PageSize) + 1);
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RX[i]->Status = 0;
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}
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WriteCMD(REG::TXDESCLO, (uint32_t)(Ptr >> 32));
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WriteCMD(REG::TXDESCHI, (uint32_t)(Ptr & 0xFFFFFFFF));
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WriteCMD(REG::RXDESCLO, (uint32_t)Ptr);
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WriteCMD(REG::RXDESCHI, 0);
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WriteCMD(REG::RXDESCLEN, E1000_NUM_RX_DESC * 16);
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WriteCMD(REG::RXDESCHEAD, 0);
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WriteCMD(REG::RXDESCTAIL, E1000_NUM_RX_DESC - 1);
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RXCurrent = 0;
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WriteCMD(REG::RCTRL, RCTL::EN | RCTL::SBP | RCTL::UPE | RCTL::MPE | RCTL::LBM_NONE | RTCL::RDMTS_HALF | RCTL::BAM | RCTL::SECRC | RCTL::BSIZE_8192);
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}
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void InitializeTX()
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{
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debug("Initializing TX...");
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uintptr_t Ptr = (uintptr_t)KAPI.Memory.RequestPage(((sizeof(TXDescriptor) * E1000_NUM_RX_DESC + 16) / KAPI.Memory.PageSize) + 1);
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for (short i = 0; i < E1000_NUM_TX_DESC; i++)
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{
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TX[i] = (TXDescriptor *)((uintptr_t)Ptr + i * 16);
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TX[i]->Address = 0;
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TX[i]->Command = 0;
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TX[i]->Status = TSTA::DD;
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}
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WriteCMD(REG::TXDESCHI, (uint32_t)((uint64_t)Ptr >> 32));
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WriteCMD(REG::TXDESCLO, (uint32_t)((uint64_t)Ptr & 0xFFFFFFFF));
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WriteCMD(REG::TXDESCLEN, E1000_NUM_TX_DESC * 16);
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WriteCMD(REG::TXDESCHEAD, 0);
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WriteCMD(REG::TXDESCTAIL, 0);
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TXCurrent = 0;
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WriteCMD(REG::TCTRL, TCTL::EN_ | TCTL::PSP | (15 << TCTL::CT_SHIFT) | (64 << TCTL::COLD_SHIFT) | TCTL::RTLC);
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WriteCMD(REG::TCTRL, 0b0110000000000111111000011111010);
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WriteCMD(REG::TIPG, 0x0060200A);
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}
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int DriverEntry(void *Data)
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{
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if (!Data)
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return INVALID_KERNEL_API;
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KAPI = *(KernelAPI *)Data;
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if (KAPI.Version.Major < 0 || KAPI.Version.Minor < 0 || KAPI.Version.Patch < 0)
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return KERNEL_API_VERSION_NOT_SUPPORTED;
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return OK;
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}
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int CallbackHandler(KernelCallback *Data)
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{
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switch (Data->Reason)
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{
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case AcknowledgeReason:
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{
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debug("Kernel acknowledged the driver.");
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break;
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}
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case ConfigurationReason:
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{
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debug("Driver received configuration data.");
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PCIBaseAddress = reinterpret_cast<PCIDeviceHeader *>(Data->RawPtr);
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switch (PCIBaseAddress->DeviceID)
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{
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case 0x100E:
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{
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trace("Found Intel 82540EM Gigabit Ethernet Controller.");
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PCIBaseAddress->Command |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
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uint32_t PCIBAR0 = ((PCIHeader0 *)PCIBaseAddress)->BAR0;
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uint32_t PCIBAR1 = ((PCIHeader0 *)PCIBaseAddress)->BAR1;
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BAR.Type = PCIBAR0 & 1;
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BAR.IOBase = (uint16_t)(PCIBAR1 & (~3));
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BAR.MemoryBase = PCIBAR0 & (~15);
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// Detect EEPROM
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WriteCMD(REG::EEPROM, 0x1);
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for (int i = 0; i < 1000 && !EEPROMAvailable; i++)
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if (ReadCMD(REG::EEPROM) & 0x10)
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EEPROMAvailable = true;
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else
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EEPROMAvailable = false;
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// Get MAC address
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if (!GetMAC().Valid())
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return NOT_AVAILABLE;
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else
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debug("MAC address found.");
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MAC = GetMAC();
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// Start link
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uint32_t cmdret = ReadCMD(REG::CTRL);
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WriteCMD(REG::CTRL, cmdret | ECTRL::SLU);
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for (int i = 0; i < 0x80; i++)
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WriteCMD((uint16_t)(0x5200 + i * 4), 0);
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WriteCMD(REG::IMASK, 0x1F6DC);
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WriteCMD(REG::IMASK, 0xFF & ~4);
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ReadCMD(0xC0);
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InitializeRX();
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InitializeTX();
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return OK;
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}
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case 0x100F:
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{
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trace("Found Intel 82545EM Gigabit Ethernet Controller.");
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PCIBaseAddress->Command |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
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uint32_t PCIBAR0 = ((PCIHeader0 *)PCIBaseAddress)->BAR0;
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uint32_t PCIBAR1 = ((PCIHeader0 *)PCIBaseAddress)->BAR1;
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BAR.Type = PCIBAR0 & 1;
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BAR.IOBase = (uint16_t)(PCIBAR1 & (~3));
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BAR.MemoryBase = PCIBAR0 & (~15);
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// Detect EEPROM
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WriteCMD(REG::EEPROM, 0x1);
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for (int i = 0; i < 1000 && !EEPROMAvailable; i++)
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if (ReadCMD(REG::EEPROM) & 0x10)
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EEPROMAvailable = true;
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else
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EEPROMAvailable = false;
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// Get MAC address
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if (!GetMAC().Valid())
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return NOT_AVAILABLE;
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else
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debug("MAC address found.");
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MAC = GetMAC();
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return NOT_IMPLEMENTED;
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}
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case 0x10D3:
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{
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trace("Found Intel 82574L Gigabit Ethernet Controller.");
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PCIBaseAddress->Command |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
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uint32_t PCIBAR0 = ((PCIHeader0 *)PCIBaseAddress)->BAR0;
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uint32_t PCIBAR1 = ((PCIHeader0 *)PCIBaseAddress)->BAR1;
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BAR.Type = PCIBAR0 & 1;
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BAR.IOBase = (uint16_t)(PCIBAR1 & (~3));
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BAR.MemoryBase = PCIBAR0 & (~15);
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// Detect EEPROM
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WriteCMD(REG::EEPROM, 0x1);
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for (int i = 0; i < 1000 && !EEPROMAvailable; i++)
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if (ReadCMD(REG::EEPROM) & 0x10)
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EEPROMAvailable = true;
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else
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EEPROMAvailable = false;
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// Get MAC address
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if (!GetMAC().Valid())
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return NOT_AVAILABLE;
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else
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debug("MAC address found.");
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MAC = GetMAC();
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return NOT_IMPLEMENTED;
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}
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case 0x10EA:
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{
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fixme("Found Intel I217-LM Gigabit Ethernet Controller.");
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return NOT_IMPLEMENTED;
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}
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case 0x153A:
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{
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fixme("Found Intel 82577LM Gigabit Ethernet Controller.");
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return NOT_IMPLEMENTED;
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}
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default:
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{
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error("Unsupported Intel Ethernet Controller.");
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return DEVICE_NOT_SUPPORTED;
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}
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}
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return ERROR;
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}
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case FetchReason:
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{
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memcpy(Data->NetworkCallback.Fetch.Name, (void *)"Intel Gigabit Ethernet Controller", 34);
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Data->NetworkCallback.Fetch.MAC = MAC.ToHex();
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break;
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}
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case SendReason:
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{
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TX[TXCurrent]->Address = (uint64_t)Data->NetworkCallback.Send.Data;
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TX[TXCurrent]->Length = (uint16_t)Data->NetworkCallback.Send.Length;
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TX[TXCurrent]->Command = CMD::EOP | CMD::IFCS | CMD::RS;
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TX[TXCurrent]->Status = 0;
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uint16_t OldTXCurrent = TXCurrent;
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TXCurrent = (uint16_t)((TXCurrent + 1) % E1000_NUM_TX_DESC);
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WriteCMD(REG::TXDESCTAIL, TXCurrent);
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while (!(TX[OldTXCurrent]->Status & 0xFF))
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;
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break;
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}
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case StopReason:
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{
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// Clearing Enable bit in Receive Control Register
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uint32_t cmdret = ReadCMD(REG::RCTRL);
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WriteCMD(REG::RCTRL, cmdret & ~RCTL::EN);
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// Masking Interrupt Mask, Interrupt Throttling Rate & Interrupt Auto-Mask
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WriteCMD(REG::IMASK, 0x00000000);
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WriteCMD(REG::ITR, 0x00000000);
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WriteCMD(REG::IAM, 0x00000000);
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// Clearing SLU bit in Device Control Register
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cmdret = ReadCMD(REG::CTRL);
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WriteCMD(REG::CTRL, cmdret & ~ECTRL::SLU);
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// Clear the Interrupt Cause Read register by reading it
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ReadCMD(REG::ICR);
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// Powering down the device (?)
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WriteCMD(REG::CTRL, PCTRL::POWER_DOWN);
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/* TODO: Stop link; further testing required */
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debug("Driver stopped.");
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break;
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}
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default:
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{
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warn("Unknown reason.");
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break;
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}
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}
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return OK;
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}
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int InterruptCallback(CPURegisters *)
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{
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WriteCMD(REG::IMASK, 0x1);
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uint32_t status = ReadCMD(0xC0);
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UNUSED(status);
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while ((RX[RXCurrent]->Status & 0x1))
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{
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uint8_t *Data = (uint8_t *)RX[RXCurrent]->Address;
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uint16_t DataLength = RX[RXCurrent]->Length;
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KAPI.Command.Network.ReceivePacket(KAPI.Info.DriverUID, Data, DataLength);
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RX[RXCurrent]->Status = 0;
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uint16_t OldRXCurrent = RXCurrent;
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RXCurrent = (uint16_t)((RXCurrent + 1) % E1000_NUM_RX_DESC);
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WriteCMD(REG::RXDESCTAIL, OldRXCurrent);
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}
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return OK;
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}
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}
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