mirror of
https://github.com/Fennix-Project/Kernel.git
synced 2025-05-28 15:34:33 +00:00
611 lines
18 KiB
C++
611 lines
18 KiB
C++
#ifndef __FENNIX_KERNEL_CPU_x32_CPUID_AMD_H__
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#define __FENNIX_KERNEL_CPU_x32_CPUID_AMD_H__
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#include <types.h>
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namespace CPU
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{
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namespace x32
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{
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/** @brief EXPERIMENTAL IMPLEMENTATION */
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namespace AMD
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{
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/** @brief Basic CPU information */
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struct CPUID0x0
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{
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union
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{
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struct
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{
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uint32_t HighestFunctionSupported : 32;
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};
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uint32_t raw;
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} EAX;
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union
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{
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struct
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{
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char Vendor[4];
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};
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uint32_t raw;
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} EBX;
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union
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{
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struct
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{
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char Vendor[4];
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};
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uint32_t raw;
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} ECX;
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union
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{
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struct
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{
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char Vendor[4];
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};
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uint32_t raw;
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} EDX;
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};
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/** @brief Additional CPU information */
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struct CPUID0x1
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{
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union
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{
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struct
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{
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uint32_t SteppingID : 4;
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uint32_t ModelID : 4;
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uint32_t FamilyID : 4;
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uint32_t Reserved0 : 4;
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uint32_t ExtendedModel : 4;
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uint32_t ExtendedFamily : 8;
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uint32_t Reserved1 : 4;
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};
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uint32_t raw;
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} EAX;
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union
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{
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struct
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{
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uint32_t BrandIndex : 8;
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uint32_t CLFLUSHLineSize : 8;
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uint32_t LogicalProcessorsPerPackage : 8;
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uint32_t LocalAPICID : 8;
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};
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uint32_t raw;
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} EBX;
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union
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{
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struct
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{
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uint32_t SSE3 : 1;
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uint32_t Reserved0 : 1;
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uint32_t MONITOR : 1;
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uint32_t Reserved1 : 1;
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uint32_t DS_CPL : 1;
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uint32_t Reserved2 : 1;
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uint32_t SMX : 1;
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uint32_t Reserved3 : 1;
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uint32_t TM2 : 1;
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uint32_t Reserved4 : 1;
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uint32_t CNXT_ID : 1;
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uint32_t Reserved5 : 1;
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uint32_t CMPXCHG16B : 1;
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uint32_t Reserved6 : 1;
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uint32_t xTPRUpdateControl : 1;
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uint32_t Reserved7 : 1;
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uint32_t Reserved8 : 1;
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uint32_t DCA : 1;
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uint32_t Reserved9 : 1;
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uint32_t SSE4_1 : 1;
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uint32_t SSE4_2 : 1;
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uint32_t Reserved10 : 1;
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uint32_t MOVBE : 1;
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uint32_t POPCNT : 1;
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uint32_t Reserved11 : 1;
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uint32_t AES : 1;
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uint32_t Reserved12 : 1;
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uint32_t XSAVE : 1;
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uint32_t OSXSAVE : 1;
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uint32_t AVX : 1;
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uint32_t Reserved13 : 1;
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uint32_t RDRAND : 1;
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uint32_t Reserved14 : 1;
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uint32_t Hypervisor : 1;
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};
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uint32_t raw;
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} ECX;
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union
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{
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struct
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{
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uint32_t FPU : 1;
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uint32_t VME : 1;
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uint32_t DE : 1;
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uint32_t PSE : 1;
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uint32_t TSC : 1;
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uint32_t MSR : 1;
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uint32_t PAE : 1;
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uint32_t MCE : 1;
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uint32_t CX8 : 1;
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uint32_t APIC : 1;
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uint32_t Reserved0 : 1;
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uint32_t SEP : 1;
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uint32_t MTRR : 1;
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uint32_t PGE : 1;
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uint32_t MCA : 1;
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uint32_t CMOV : 1;
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uint32_t PAT : 1;
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uint32_t PSE36 : 1;
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uint32_t PSN : 1;
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uint32_t CLFSH : 1;
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uint32_t Reserved1 : 1;
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uint32_t DS : 1;
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uint32_t ACPI : 1;
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uint32_t MMX : 1;
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uint32_t FXSR : 1;
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uint32_t SSE : 1;
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uint32_t SSE2 : 1;
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uint32_t SS : 1;
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uint32_t HTT : 1;
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uint32_t TM : 1;
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uint32_t Reserved2 : 1;
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uint32_t PBE : 1;
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};
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uint32_t raw;
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} EDX;
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};
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/** @brief CPU cache and TLB */
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struct CPUID0x2
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{
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union
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{
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struct
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{
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uint32_t L1DataCacheSize : 8;
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uint32_t L1DataCacheAssociativity : 8;
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uint32_t L1DataCacheLineSize : 8;
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uint32_t L1DataCachePartitions : 8;
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};
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uint32_t raw;
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} EAX;
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union
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{
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struct
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{
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uint32_t L1InstructionCacheSize : 8;
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uint32_t L1InstructionCacheAssociativity : 8;
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uint32_t L1InstructionCacheLineSize : 8;
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uint32_t L1InstructionCachePartitions : 8;
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};
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uint32_t raw;
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} EBX;
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union
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{
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struct
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{
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uint32_t L2UnifiedCacheSize : 16;
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uint32_t L2UnifiedCacheAssociativity : 8;
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uint32_t L2UnifiedCacheLineSize : 8;
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uint32_t L2UnifiedCachePartitions : 8;
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};
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uint32_t raw;
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} ECX;
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union
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{
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struct
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{
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uint32_t L3UnifiedCacheSize : 18;
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uint32_t L3UnifiedCacheAssociativity : 8;
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uint32_t L3UnifiedCacheLineSize : 8;
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uint32_t L3UnifiedCachePartitions : 8;
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};
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uint32_t raw;
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} EDX;
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};
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/** @brief Get CPU hypervisor information */
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struct CPUID0x40000000
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{
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union
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{
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struct
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{
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/**
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* @brief Maximum input value for hypervisor CPUID information.
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* @note Can be from 0x40000001 to 0x400000FF
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*/
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uint32_t MaximumInputValue : 32;
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};
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uint32_t raw;
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} EAX;
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union
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{
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struct
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{
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/** @brief Hypervisor vendor signature */
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char Hypervisor[4];
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};
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uint32_t raw;
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} EBX;
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union
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{
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struct
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{
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/** @brief Hypervisor vendor signature */
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char Hypervisor[4];
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};
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uint32_t raw;
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} ECX;
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union
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{
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struct
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{
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/** @brief Hypervisor vendor signature */
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char Hypervisor[4];
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};
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uint32_t raw;
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} EDX;
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};
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/** @brief Extended CPU information */
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struct CPUID0x80000001
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{
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union
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{
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struct
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{
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uint32_t SteppingID : 4;
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uint32_t ModelID : 4;
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uint32_t FamilyID : 4;
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uint32_t Reserved0 : 4;
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uint32_t ExtendedModel : 4;
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uint32_t ExtendedFamily : 8;
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uint32_t Reserved1 : 4;
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};
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uint32_t raw;
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} EAX;
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union
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{
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struct
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{
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uint32_t BranchID : 16;
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uint32_t Reserved0 : 16;
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};
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uint32_t raw;
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} EBX;
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union
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{
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struct
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{
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uint32_t LAHF_SAHF : 1;
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uint32_t CmpLegacy : 1;
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uint32_t SVM : 1;
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uint32_t Reserved0 : 1;
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uint32_t AltMovCr8 : 1;
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uint32_t Reserved1 : 26;
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};
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uint32_t raw;
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} ECX;
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union
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{
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struct
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{
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uint32_t FPU : 1;
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uint32_t VME : 1;
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uint32_t DE : 1;
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uint32_t PSE : 1;
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uint32_t TSC : 1;
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uint32_t MSR : 1;
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uint32_t PAE : 1;
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uint32_t MCE : 1;
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uint32_t CMPXCHG8B : 1;
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uint32_t APIC : 1;
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uint32_t Reserved0 : 1;
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uint32_t SYSCALL : 1;
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uint32_t MTRR : 1;
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uint32_t PGE : 1;
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uint32_t MCA : 1;
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uint32_t CMOV : 1;
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uint32_t PAT : 1;
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uint32_t PSE36 : 1;
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uint32_t Reserved1 : 1;
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uint32_t ExeDisable : 1;
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uint32_t Reserved2 : 1;
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uint32_t MMXExtended : 1;
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uint32_t MMX : 1;
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uint32_t FXSR : 1;
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uint32_t FFXSR : 1;
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uint32_t Reserved3 : 1;
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uint32_t RDTSCP : 1;
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uint32_t Reserved4 : 1;
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uint32_t LongMode : 1;
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uint32_t ThreeDNowExtended : 1;
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uint32_t ThreeDNow : 1;
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};
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uint32_t raw;
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} EDX;
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};
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/** @brief CPU brand string */
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struct CPUID0x80000002
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{
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union
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{
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struct
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{
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char Brand[4];
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};
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uint32_t raw;
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} EAX;
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union
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{
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struct
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{
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char Brand[4];
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};
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uint32_t raw;
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} EBX;
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union
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{
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struct
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{
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char Brand[4];
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};
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uint32_t raw;
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} ECX;
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union
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{
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struct
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{
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char Brand[4];
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};
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uint32_t raw;
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} EDX;
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};
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/** @brief CPU brand string */
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struct CPUID0x80000003
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{
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union
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{
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struct
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{
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char Brand[4];
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};
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uint32_t raw;
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} EAX;
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union
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{
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struct
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{
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char Brand[4];
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};
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uint32_t raw;
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} EBX;
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union
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{
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struct
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{
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char Brand[4];
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};
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uint32_t raw;
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} ECX;
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union
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{
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struct
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{
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char Brand[4];
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};
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uint32_t raw;
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} EDX;
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};
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/** @brief CPU brand string */
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struct CPUID0x80000004
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{
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union
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{
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struct
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{
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char Brand[4];
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};
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uint32_t raw;
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} EAX;
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union
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{
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struct
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{
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char Brand[4];
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};
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uint32_t raw;
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} EBX;
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union
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{
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struct
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{
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char Brand[4];
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};
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uint32_t raw;
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} ECX;
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union
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{
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struct
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{
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char Brand[4];
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};
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uint32_t raw;
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} EDX;
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};
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/** @brief Cache and TLB information */
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struct CPUID0x80000005
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{
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union
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{
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struct
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{
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uint32_t InstructionCount : 8;
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uint32_t InstructionAssociativity : 8;
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uint32_t DataCount : 8;
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uint32_t DataAssociativity : 8;
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};
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uint32_t raw;
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} EAX;
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union
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{
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struct
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{
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uint32_t InstructionCount : 8;
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uint32_t InstructionAssociativity : 8;
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uint32_t DataCount : 8;
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uint32_t DataAssociativity : 8;
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};
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uint32_t raw;
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} EBX;
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union
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{
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struct
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{
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uint32_t LineSize : 8;
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uint32_t LinePerTag : 8;
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uint32_t Associativity : 8;
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uint32_t CacheSize : 8;
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};
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uint32_t raw;
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} ECX;
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union
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{
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struct
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{
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uint32_t LineSize : 8;
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uint32_t LinePerTag : 8;
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uint32_t Associativity : 8;
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uint32_t CacheSize : 8;
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};
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uint32_t raw;
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} EDX;
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};
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/** @brief CPU cache line information */
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struct CPUID0x80000006
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{
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union
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{
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struct
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{
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uint32_t Reserved : 32;
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};
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uint32_t raw;
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} EAX;
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union
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{
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struct
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{
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uint32_t Reserved : 32;
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};
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uint32_t raw;
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} EBX;
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union
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{
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struct
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{
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uint32_t LineSize : 8;
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uint32_t LinePerTag : 4;
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uint32_t Associativity : 4;
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uint32_t CacheSize : 16;
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};
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uint32_t raw;
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} ECX;
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union
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{
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struct
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{
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uint32_t Reserved : 32;
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};
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uint32_t raw;
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} EDX;
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};
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/** @brief APM */
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struct CPUID0x80000007
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{
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union
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{
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struct
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{
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uint32_t Reserved : 32;
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};
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uint32_t raw;
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} EAX;
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union
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{
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struct
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{
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uint32_t Reserved : 32;
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};
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uint32_t raw;
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} EBX;
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union
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{
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struct
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{
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uint32_t Reserved : 32;
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};
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uint32_t raw;
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} ECX;
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union
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{
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struct
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{
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uint32_t TemperatureSensor : 1;
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uint32_t FrequencyID : 1;
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uint32_t VoltageID : 1;
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uint32_t ThermaTrip : 1;
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uint32_t HarwareThermalControl : 1;
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uint32_t SoftwareThermalControl : 1;
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uint32_t Reserved0 : 2;
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uint32_t TSCInvariant : 1;
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uint32_t Reserved1 : 23;
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};
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uint32_t raw;
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} EDX;
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};
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}
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}
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}
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#endif // !__FENNIX_KERNEL_CPU_x32_CPUID_AMD_H__
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