mirror of
https://github.com/Fennix-Project/Kernel.git
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.github
.vscode
Architecture
Core
Crash
Screens
CrashDetails.cpp
CrashHandler.cpp
KBDrv.cpp
SFrame.cpp
UserHandler.cpp
chfcts.hpp
Driver
Memory
Time
Video
CPU.cpp
Debugger.cpp
Disk.cpp
InterruptsManager.cpp
Lock.cpp
PeripheralComponentInterconnect.cpp
Power.cpp
README.md
Random.cpp
StackCheck.cpp
Symbols.cpp
SystemManagementBIOS.cpp
UndefinedBehaviorSanitization.c
UniversalAsynchronousReceiverTransmitter.cpp
crashhandler.hpp
smbios.hpp
ubsan.h
ExecutionLayer
FileSystem
Files
KernelShell
Library
Modules
Network
Profiling
SystemCalls
Tasking
Tests
Virtualization
include
include_std
.gitignore
DAPI.hpp
Doxyfile
Fex.hpp
Kernel.cpp
KernelConfig.cpp
KernelThread.cpp
LICENSE
Makefile
README.md
dump.sh
ipc.h
kernel.h
syscalls.h
399 lines
19 KiB
C++
399 lines
19 KiB
C++
/*
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This file is part of Fennix Kernel.
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Fennix Kernel is free software: you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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Fennix Kernel is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include "../crashhandler.hpp"
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#include "chfcts.hpp"
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#include <display.hpp>
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#include <printf.h>
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#include <debug.h>
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#include <smp.hpp>
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#include <cpu.hpp>
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#if defined(a64)
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#include "../../Architecture/amd64/cpu/gdt.hpp"
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#elif defined(a32)
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#elif defined(aa64)
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#endif
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#include "../../kernel.h"
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static const char *PageFaultDescriptions[8] = {
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"Supervisory process tried to read a non-present page entry\n",
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"Supervisory process tried to read a page and caused a protection fault\n",
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"Supervisory process tried to write to a non-present page entry\n",
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"Supervisory process tried to write a page and caused a protection fault\n",
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"User process tried to read a non-present page entry\n",
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"User process tried to read a page and caused a protection fault\n",
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"User process tried to write to a non-present page entry\n",
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"User process tried to write a page and caused a protection fault\n"};
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SafeFunction void UserModeExceptionHandler(CHArchTrapFrame *Frame)
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{
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CriticalSection cs;
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debug("Interrupts? %s.", cs.IsInterruptsEnabled() ? "Yes" : "No");
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fixme("Handling user mode exception");
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thisThread->Status = Tasking::TaskStatus::Zombie;
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CPUData *CurCPU = GetCurrentCPU();
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{
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#if defined(a64)
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CPU::x64::CR0 cr0 = CPU::x64::readcr0();
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CPU::x64::CR2 cr2 = CPU::x64::CR2{.PFLA = CrashHandler::PageFaultAddress};
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CPU::x64::CR3 cr3 = CPU::x64::readcr3();
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CPU::x64::CR4 cr4 = CPU::x64::readcr4();
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CPU::x64::CR8 cr8 = CPU::x64::readcr8();
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CPU::x64::EFER efer;
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efer.raw = CPU::x64::rdmsr(CPU::x64::MSR_EFER);
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error("Technical Informations on CPU %lld:", CurCPU->ID);
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uintptr_t ds;
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asmv("mov %%ds, %0"
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: "=r"(ds));
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#elif defined(a32)
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CPU::x32::CR0 cr0 = CPU::x32::readcr0();
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CPU::x32::CR2 cr2 = CPU::x32::CR2{.PFLA = CrashHandler::PageFaultAddress};
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CPU::x32::CR3 cr3 = CPU::x32::readcr3();
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CPU::x32::CR4 cr4 = CPU::x32::readcr4();
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CPU::x32::CR8 cr8 = CPU::x32::readcr8();
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error("Technical Informations on CPU %lld:", CurCPU->ID);
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uintptr_t ds;
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asmv("mov %%ds, %0"
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: "=r"(ds));
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#elif defined(aa64)
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#endif
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#if defined(a64)
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error("FS=%#llx GS=%#llx SS=%#llx CS=%#llx DS=%#llx",
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CPU::x64::rdmsr(CPU::x64::MSR_FS_BASE), CPU::x64::rdmsr(CPU::x64::MSR_GS_BASE),
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Frame->ss, Frame->cs, ds);
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error("R8=%#llx R9=%#llx R10=%#llx R11=%#llx", Frame->r8, Frame->r9, Frame->r10, Frame->r11);
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error("R12=%#llx R13=%#llx R14=%#llx R15=%#llx", Frame->r12, Frame->r13, Frame->r14, Frame->r15);
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error("RAX=%#llx RBX=%#llx RCX=%#llx RDX=%#llx", Frame->rax, Frame->rbx, Frame->rcx, Frame->rdx);
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error("RSI=%#llx RDI=%#llx RBP=%#llx RSP=%#llx", Frame->rsi, Frame->rdi, Frame->rbp, Frame->rsp);
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error("RIP=%#llx RFL=%#llx INT=%#llx ERR=%#llx EFER=%#llx", Frame->rip, Frame->rflags.raw, Frame->InterruptNumber, Frame->ErrorCode, efer.raw);
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#elif defined(a32)
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error("FS=%#llx GS=%#llx SS=%#llx CS=%#llx DS=%#llx",
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CPU::x32::rdmsr(CPU::x32::MSR_FS_BASE), CPU::x32::rdmsr(CPU::x32::MSR_GS_BASE),
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Frame->ss, Frame->cs, ds);
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error("EAX=%#llx EBX=%#llx ECX=%#llx EDX=%#llx", Frame->eax, Frame->ebx, Frame->ecx, Frame->edx);
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error("ESI=%#llx EDI=%#llx EBP=%#llx ESP=%#llx", Frame->esi, Frame->edi, Frame->ebp, Frame->esp);
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error("EIP=%#llx EFL=%#llx INT=%#llx ERR=%#llx", Frame->eip, Frame->eflags.raw, Frame->InterruptNumber, Frame->ErrorCode);
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#elif defined(aa64)
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#endif
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#if defined(a86)
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error("CR0=%#llx CR2=%#llx CR3=%#llx CR4=%#llx CR8=%#llx", cr0.raw, cr2.raw, cr3.raw, cr4.raw, cr8.raw);
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error("CR0: PE:%s MP:%s EM:%s TS:%s ET:%s NE:%s WP:%s AM:%s NW:%s CD:%s PG:%s R0:%#x R1:%#x R2:%#x",
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cr0.PE ? "True " : "False", cr0.MP ? "True " : "False", cr0.EM ? "True " : "False", cr0.TS ? "True " : "False",
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cr0.ET ? "True " : "False", cr0.NE ? "True " : "False", cr0.WP ? "True " : "False", cr0.AM ? "True " : "False",
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cr0.NW ? "True " : "False", cr0.CD ? "True " : "False", cr0.PG ? "True " : "False",
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cr0.Reserved0, cr0.Reserved1, cr0.Reserved2);
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error("CR2: PFLA: %#llx",
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cr2.PFLA);
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error("CR3: PWT:%s PCD:%s PDBR:%#llx",
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cr3.PWT ? "True " : "False", cr3.PCD ? "True " : "False", cr3.PDBR);
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#endif // defined(a86)
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#if defined(a64)
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error("CR4: VME:%s PVI:%s TSD:%s DE:%s PSE:%s PAE:%s MCE:%s PGE:%s PCE:%s UMIP:%s OSFXSR:%s OSXMMEXCPT:%s LA57:%s VMXE:%s SMXE:%s PCIDE:%s OSXSAVE:%s SMEP:%s SMAP:%s PKE:%s R0:%#x R1:%#x R2:%#x",
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cr4.VME ? "True " : "False", cr4.PVI ? "True " : "False", cr4.TSD ? "True " : "False", cr4.DE ? "True " : "False",
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cr4.PSE ? "True " : "False", cr4.PAE ? "True " : "False", cr4.MCE ? "True " : "False", cr4.PGE ? "True " : "False",
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cr4.PCE ? "True " : "False", cr4.UMIP ? "True " : "False", cr4.OSFXSR ? "True " : "False", cr4.OSXMMEXCPT ? "True " : "False",
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cr4.LA57 ? "True " : "False", cr4.VMXE ? "True " : "False", cr4.SMXE ? "True " : "False", cr4.PCIDE ? "True " : "False",
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cr4.OSXSAVE ? "True " : "False", cr4.SMEP ? "True " : "False", cr4.SMAP ? "True " : "False", cr4.PKE ? "True " : "False",
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cr4.Reserved0, cr4.Reserved1, cr4.Reserved2);
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#elif defined(a32)
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error("CR4: VME:%s PVI:%s TSD:%s DE:%s PSE:%s PAE:%s MCE:%s PGE:%s PCE:%s UMIP:%s OSFXSR:%s OSXMMEXCPT:%s LA57:%s VMXE:%s SMXE:%s PCIDE:%s OSXSAVE:%s SMEP:%s SMAP:%s PKE:%s R0:%#x R1:%#x",
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cr4.VME ? "True " : "False", cr4.PVI ? "True " : "False", cr4.TSD ? "True " : "False", cr4.DE ? "True " : "False",
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cr4.PSE ? "True " : "False", cr4.PAE ? "True " : "False", cr4.MCE ? "True " : "False", cr4.PGE ? "True " : "False",
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cr4.PCE ? "True " : "False", cr4.UMIP ? "True " : "False", cr4.OSFXSR ? "True " : "False", cr4.OSXMMEXCPT ? "True " : "False",
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cr4.LA57 ? "True " : "False", cr4.VMXE ? "True " : "False", cr4.SMXE ? "True " : "False", cr4.PCIDE ? "True " : "False",
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cr4.OSXSAVE ? "True " : "False", cr4.SMEP ? "True " : "False", cr4.SMAP ? "True " : "False", cr4.PKE ? "True " : "False",
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cr4.Reserved0, cr4.Reserved1);
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#endif
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#if defined(a86)
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error("CR8: TPL:%d", cr8.TPL);
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#endif // defined(a86)
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#if defined(a64)
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error("RFL: CF:%s PF:%s AF:%s ZF:%s SF:%s TF:%s IF:%s DF:%s OF:%s IOPL:%s NT:%s RF:%s VM:%s AC:%s VIF:%s VIP:%s ID:%s AlwaysOne:%d R0:%#x R1:%#x R2:%#x R3:%#x",
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Frame->rflags.CF ? "True " : "False", Frame->rflags.PF ? "True " : "False", Frame->rflags.AF ? "True " : "False", Frame->rflags.ZF ? "True " : "False",
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Frame->rflags.SF ? "True " : "False", Frame->rflags.TF ? "True " : "False", Frame->rflags.IF ? "True " : "False", Frame->rflags.DF ? "True " : "False",
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Frame->rflags.OF ? "True " : "False", Frame->rflags.IOPL ? "True " : "False", Frame->rflags.NT ? "True " : "False", Frame->rflags.RF ? "True " : "False",
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Frame->rflags.VM ? "True " : "False", Frame->rflags.AC ? "True " : "False", Frame->rflags.VIF ? "True " : "False", Frame->rflags.VIP ? "True " : "False",
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Frame->rflags.ID ? "True " : "False", Frame->rflags.AlwaysOne,
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Frame->rflags.Reserved0, Frame->rflags.Reserved1, Frame->rflags.Reserved2, Frame->rflags.Reserved3);
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#elif defined(a32)
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error("EFL: CF:%s PF:%s AF:%s ZF:%s SF:%s TF:%s IF:%s DF:%s OF:%s IOPL:%s NT:%s RF:%s VM:%s AC:%s VIF:%s VIP:%s ID:%s AlwaysOne:%d R0:%#x R1:%#x R2:%#x",
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Frame->eflags.CF ? "True " : "False", Frame->eflags.PF ? "True " : "False", Frame->eflags.AF ? "True " : "False", Frame->eflags.ZF ? "True " : "False",
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Frame->eflags.SF ? "True " : "False", Frame->eflags.TF ? "True " : "False", Frame->eflags.IF ? "True " : "False", Frame->eflags.DF ? "True " : "False",
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Frame->eflags.OF ? "True " : "False", Frame->eflags.IOPL ? "True " : "False", Frame->eflags.NT ? "True " : "False", Frame->eflags.RF ? "True " : "False",
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Frame->eflags.VM ? "True " : "False", Frame->eflags.AC ? "True " : "False", Frame->eflags.VIF ? "True " : "False", Frame->eflags.VIP ? "True " : "False",
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Frame->eflags.ID ? "True " : "False", Frame->eflags.AlwaysOne,
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Frame->eflags.Reserved0, Frame->eflags.Reserved1, Frame->eflags.Reserved2);
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#elif defined(aa64)
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#endif
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#if defined(a64)
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error("EFER: SCE:%s LME:%s LMA:%s NXE:%s SVME:%s LMSLE:%s FFXSR:%s TCE:%s R0:%#x R1:%#x R2:%#x",
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efer.SCE ? "True " : "False", efer.LME ? "True " : "False", efer.LMA ? "True " : "False", efer.NXE ? "True " : "False",
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efer.SVME ? "True " : "False", efer.LMSLE ? "True " : "False", efer.FFXSR ? "True " : "False", efer.TCE ? "True " : "False",
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efer.Reserved0, efer.Reserved1, efer.Reserved2);
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#endif
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}
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switch (Frame->InterruptNumber)
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{
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case CPU::x86::DivideByZero:
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{
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break;
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}
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case CPU::x86::Debug:
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{
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break;
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}
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case CPU::x86::NonMaskableInterrupt:
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{
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break;
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}
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case CPU::x86::Breakpoint:
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{
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break;
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}
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case CPU::x86::Overflow:
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{
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break;
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}
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case CPU::x86::BoundRange:
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{
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break;
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}
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case CPU::x86::InvalidOpcode:
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{
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break;
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}
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case CPU::x86::DeviceNotAvailable:
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{
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break;
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}
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case CPU::x86::DoubleFault:
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{
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break;
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}
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case CPU::x86::CoprocessorSegmentOverrun:
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{
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break;
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}
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case CPU::x86::InvalidTSS:
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{
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break;
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}
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case CPU::x86::SegmentNotPresent:
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{
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break;
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}
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case CPU::x86::StackSegmentFault:
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{
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break;
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}
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case CPU::x86::GeneralProtectionFault:
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{
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break;
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}
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case CPU::x86::PageFault:
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{
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uintptr_t CheckPageFaultAddress = 0;
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CPU::x64::PageFaultErrorCode params = {.raw = (uint32_t)Frame->ErrorCode};
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#if defined(a64)
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CheckPageFaultAddress = CrashHandler::PageFaultAddress;
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if (CheckPageFaultAddress == 0)
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CheckPageFaultAddress = Frame->rip;
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error("An exception occurred at %#lx by %#lx", CrashHandler::PageFaultAddress, Frame->rip);
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#elif defined(a32)
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error("An exception occurred at %#lx by %#lx", CrashHandler::PageFaultAddress, Frame->eip);
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#elif defined(aa64)
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#endif
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error("Page: %s", params.P ? "Present" : "Not Present");
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error("Write Operation: %s", params.W ? "Read-Only" : "Read-Write");
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error("Processor Mode: %s", params.U ? "User-Mode" : "Kernel-Mode");
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error("CPU Reserved Bits: %s", params.R ? "Reserved" : "Unreserved");
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error("Caused By An Instruction Fetch: %s", params.I ? "Yes" : "No");
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error("Caused By A Protection-Key Violation: %s", params.PK ? "Yes" : "No");
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error("Caused By A Shadow Stack Access: %s", params.SS ? "Yes" : "No");
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error("Caused By An SGX Violation: %s", params.SGX ? "Yes" : "No");
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if (Frame->ErrorCode & 0x00000008)
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error("One or more page directory entries contain reserved bits which are set to 1.");
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else
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error(PageFaultDescriptions[Frame->ErrorCode & 0b111]);
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#ifdef DEBUG
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if (CurCPU)
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{
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Memory::Virtual vmm = Memory::Virtual(CurCPU->CurrentProcess->PageTable);
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bool PageAvailable = vmm.Check((void *)CheckPageFaultAddress);
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debug("Page available (Check(...)): %s. %s",
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PageAvailable ? "Yes" : "No",
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(params.P && !PageAvailable) ? "CR2 == Present; Check() != Present??????" : "CR2 confirms Check() result.");
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if (PageAvailable)
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{
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bool Present = vmm.Check((void *)CheckPageFaultAddress);
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bool ReadWrite = vmm.Check((void *)CheckPageFaultAddress, Memory::PTFlag::RW);
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bool User = vmm.Check((void *)CheckPageFaultAddress, Memory::PTFlag::US);
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bool WriteThrough = vmm.Check((void *)CheckPageFaultAddress, Memory::PTFlag::PWT);
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bool CacheDisabled = vmm.Check((void *)CheckPageFaultAddress, Memory::PTFlag::PCD);
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bool Accessed = vmm.Check((void *)CheckPageFaultAddress, Memory::PTFlag::A);
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bool Dirty = vmm.Check((void *)CheckPageFaultAddress, Memory::PTFlag::D);
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bool Global = vmm.Check((void *)CheckPageFaultAddress, Memory::PTFlag::G);
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/* ... */
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debug("Page available: %s", Present ? "Yes" : "No");
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debug("Page read/write: %s", ReadWrite ? "Yes" : "No");
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debug("Page user/kernel: %s", User ? "User" : "Kernel");
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debug("Page write-through: %s", WriteThrough ? "Yes" : "No");
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debug("Page cache disabled: %s", CacheDisabled ? "Yes" : "No");
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debug("Page accessed: %s", Accessed ? "Yes" : "No");
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debug("Page dirty: %s", Dirty ? "Yes" : "No");
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debug("Page global: %s", Global ? "Yes" : "No");
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if (Present)
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{
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#if defined(a64)
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uintptr_t CheckPageFaultLinearAddress = (uintptr_t)CheckPageFaultAddress;
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CheckPageFaultLinearAddress &= 0xFFFFFFFFFFFFF000;
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debug("%#lx -> %#lx", CheckPageFaultAddress, CheckPageFaultLinearAddress);
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Memory::Virtual::PageMapIndexer Index = Memory::Virtual::PageMapIndexer((uintptr_t)CheckPageFaultLinearAddress);
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debug("Index for %#lx is PML:%d PDPTE:%d PDE:%d PTE:%d",
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CheckPageFaultLinearAddress,
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Index.PMLIndex,
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Index.PDPTEIndex,
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Index.PDEIndex,
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Index.PTEIndex);
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Memory::PageMapLevel4 PML4 = CurCPU->CurrentProcess->PageTable->Entries[Index.PMLIndex];
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Memory::PageDirectoryPointerTableEntryPtr *PDPTE = (Memory::PageDirectoryPointerTableEntryPtr *)((uintptr_t)PML4.GetAddress() << 12);
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Memory::PageDirectoryEntryPtr *PDE = (Memory::PageDirectoryEntryPtr *)((uintptr_t)PDPTE->Entries[Index.PDPTEIndex].GetAddress() << 12);
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Memory::PageTableEntryPtr *PTE = (Memory::PageTableEntryPtr *)((uintptr_t)PDE->Entries[Index.PDEIndex].GetAddress() << 12);
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debug("# %03d-%03d-%03d-%03d: P:%s RW:%s US:%s PWT:%s PCB:%s A:%s NX:%s Address:%#lx",
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Index.PMLIndex, 0, 0, 0,
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PML4.Present ? "1" : "0",
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PML4.ReadWrite ? "1" : "0",
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PML4.UserSupervisor ? "1" : "0",
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PML4.WriteThrough ? "1" : "0",
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PML4.CacheDisable ? "1" : "0",
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PML4.Accessed ? "1" : "0",
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PML4.ExecuteDisable ? "1" : "0",
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PML4.GetAddress() << 12);
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debug("# %03d-%03d-%03d-%03d: P:%s RW:%s US:%s PWT:%s PCB:%s A:%s NX:%s Address:%#lx",
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Index.PMLIndex, Index.PDPTEIndex, 0, 0,
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PDPTE->Entries[Index.PDPTEIndex].Present ? "1" : "0",
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PDPTE->Entries[Index.PDPTEIndex].ReadWrite ? "1" : "0",
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PDPTE->Entries[Index.PDPTEIndex].UserSupervisor ? "1" : "0",
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PDPTE->Entries[Index.PDPTEIndex].WriteThrough ? "1" : "0",
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PDPTE->Entries[Index.PDPTEIndex].CacheDisable ? "1" : "0",
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PDPTE->Entries[Index.PDPTEIndex].Accessed ? "1" : "0",
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PDPTE->Entries[Index.PDPTEIndex].ExecuteDisable ? "1" : "0",
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PDPTE->Entries[Index.PDPTEIndex].GetAddress() << 12);
|
|
|
|
debug("# %03d-%03d-%03d-%03d: P:%s RW:%s US:%s PWT:%s PCB:%s A:%s NX:%s Address:%#lx",
|
|
Index.PMLIndex, Index.PDPTEIndex, Index.PDEIndex, 0,
|
|
PDE->Entries[Index.PDEIndex].Present ? "1" : "0",
|
|
PDE->Entries[Index.PDEIndex].ReadWrite ? "1" : "0",
|
|
PDE->Entries[Index.PDEIndex].UserSupervisor ? "1" : "0",
|
|
PDE->Entries[Index.PDEIndex].WriteThrough ? "1" : "0",
|
|
PDE->Entries[Index.PDEIndex].CacheDisable ? "1" : "0",
|
|
PDE->Entries[Index.PDEIndex].Accessed ? "1" : "0",
|
|
PDE->Entries[Index.PDEIndex].ExecuteDisable ? "1" : "0",
|
|
PDE->Entries[Index.PDEIndex].GetAddress() << 12);
|
|
|
|
debug("# %03d-%03d-%03d-%03d: P:%s RW:%s US:%s PWT:%s PCB:%s A:%s D:%s PAT:%s G:%s PK:%d NX:%s Address:%#lx",
|
|
Index.PMLIndex, Index.PDPTEIndex, Index.PDEIndex, Index.PTEIndex,
|
|
PTE->Entries[Index.PTEIndex].Present ? "1" : "0",
|
|
PTE->Entries[Index.PTEIndex].ReadWrite ? "1" : "0",
|
|
PTE->Entries[Index.PTEIndex].UserSupervisor ? "1" : "0",
|
|
PTE->Entries[Index.PTEIndex].WriteThrough ? "1" : "0",
|
|
PTE->Entries[Index.PTEIndex].CacheDisable ? "1" : "0",
|
|
PTE->Entries[Index.PTEIndex].Accessed ? "1" : "0",
|
|
PTE->Entries[Index.PTEIndex].Dirty ? "1" : "0",
|
|
PTE->Entries[Index.PTEIndex].PageAttributeTable ? "1" : "0",
|
|
PTE->Entries[Index.PTEIndex].Global ? "1" : "0",
|
|
PTE->Entries[Index.PTEIndex].ProtectionKey,
|
|
PTE->Entries[Index.PTEIndex].ExecuteDisable ? "1" : "0",
|
|
PTE->Entries[Index.PTEIndex].GetAddress() << 12);
|
|
#endif
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
if (CurCPU)
|
|
if (CurCPU->CurrentThread->Stack->Expand(CrashHandler::PageFaultAddress))
|
|
{
|
|
debug("Stack expanded");
|
|
thisThread->Status = Tasking::TaskStatus::Ready;
|
|
return;
|
|
}
|
|
break;
|
|
}
|
|
case CPU::x86::x87FloatingPoint:
|
|
{
|
|
break;
|
|
}
|
|
case CPU::x86::AlignmentCheck:
|
|
{
|
|
break;
|
|
}
|
|
case CPU::x86::MachineCheck:
|
|
{
|
|
break;
|
|
}
|
|
case CPU::x86::SIMDFloatingPoint:
|
|
{
|
|
break;
|
|
}
|
|
case CPU::x86::Virtualization:
|
|
{
|
|
break;
|
|
}
|
|
case CPU::x86::Security:
|
|
{
|
|
break;
|
|
}
|
|
default:
|
|
{
|
|
break;
|
|
}
|
|
}
|
|
|
|
thisThread->Status = Tasking::TaskStatus::Terminated;
|
|
__sync;
|
|
error("End of report.");
|
|
CPU::Interrupts(CPU::Enable);
|
|
debug("Interrupts enabled back.");
|
|
return;
|
|
}
|