mirror of
https://github.com/Fennix-Project/Kernel.git
synced 2025-05-25 22:14:37 +00:00
226 lines
9.7 KiB
C++
226 lines
9.7 KiB
C++
/*
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This file is part of Fennix Kernel.
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Fennix Kernel is free software: you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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Fennix Kernel is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include "../crashhandler.hpp"
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#include "chfcts.hpp"
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#include <display.hpp>
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#include <printf.h>
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#include <debug.h>
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#include <smp.hpp>
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#include <cpu.hpp>
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#if defined(a64)
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#include "../../arch/amd64/cpu/gdt.hpp"
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#elif defined(a32)
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#elif defined(aa64)
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#endif
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#include "../../kernel.h"
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nsa bool UserModeExceptionHandler(CPU::TrapFrame *Frame)
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{
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CPUData *CurCPU = GetCurrentCPU();
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Tasking::PCB *CurProc = CurCPU->CurrentProcess;
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Tasking::TCB *CurThread = CurCPU->CurrentThread;
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debug("Current process %s(%d) and thread %s(%d)",
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CurProc->Name, CurProc->ID, CurThread->Name, CurThread->ID);
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CurThread->SetState(Tasking::Waiting);
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#ifdef DEBUG
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{
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#if defined(a64)
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CPU::x64::CR0 cr0 = CPU::x64::readcr0();
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CPU::x64::CR2 cr2 = CPU::x64::CR2{.PFLA = CrashHandler::PageFaultAddress};
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CPU::x64::CR3 cr3 = CPU::x64::readcr3();
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CPU::x64::CR4 cr4 = CPU::x64::readcr4();
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CPU::x64::CR8 cr8 = CPU::x64::readcr8();
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CPU::x64::EFER efer;
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efer.raw = CPU::x64::rdmsr(CPU::x64::MSR_EFER);
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uintptr_t ds;
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asmv("mov %%ds, %0"
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: "=r"(ds));
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#elif defined(a32)
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CPU::x32::CR0 cr0 = CPU::x32::readcr0();
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CPU::x32::CR2 cr2 = CPU::x32::CR2{.PFLA = CrashHandler::PageFaultAddress};
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CPU::x32::CR3 cr3 = CPU::x32::readcr3();
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CPU::x32::CR4 cr4 = CPU::x32::readcr4();
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CPU::x32::CR8 cr8 = CPU::x32::readcr8();
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uintptr_t ds;
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asmv("mov %%ds, %0"
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: "=r"(ds));
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#elif defined(aa64)
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#endif
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#if defined(a64)
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debug("FS=%#lx GS=%#lx SS=%#lx CS=%#lx DS=%#lx",
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CPU::x64::rdmsr(CPU::x64::MSR_FS_BASE), CPU::x64::rdmsr(CPU::x64::MSR_GS_BASE),
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Frame->ss, Frame->cs, ds);
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debug("R8=%#lx R9=%#lx R10=%#lx R11=%#lx", Frame->r8, Frame->r9, Frame->r10, Frame->r11);
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debug("R12=%#lx R13=%#lx R14=%#lx R15=%#lx", Frame->r12, Frame->r13, Frame->r14, Frame->r15);
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debug("RAX=%#lx RBX=%#lx RCX=%#lx RDX=%#lx", Frame->rax, Frame->rbx, Frame->rcx, Frame->rdx);
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debug("RSI=%#lx RDI=%#lx RBP=%#lx RSP=%#lx", Frame->rsi, Frame->rdi, Frame->rbp, Frame->rsp);
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debug("RIP=%#lx RFL=%#lx INT=%#lx ERR=%#lx EFER=%#lx", Frame->rip, Frame->rflags.raw, Frame->InterruptNumber, Frame->ErrorCode, efer.raw);
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#elif defined(a32)
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debug("FS=%#x GS=%#x CS=%#x DS=%#x",
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CPU::x32::rdmsr(CPU::x32::MSR_FS_BASE), CPU::x32::rdmsr(CPU::x32::MSR_GS_BASE),
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Frame->cs, ds);
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debug("EAX=%#x EBX=%#x ECX=%#x EDX=%#x", Frame->eax, Frame->ebx, Frame->ecx, Frame->edx);
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debug("ESI=%#x EDI=%#x EBP=%#x ESP=%#x", Frame->esi, Frame->edi, Frame->ebp, Frame->esp);
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debug("EIP=%#x EFL=%#x INT=%#x ERR=%#x", Frame->eip, Frame->eflags.raw, Frame->InterruptNumber, Frame->ErrorCode);
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#elif defined(aa64)
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#endif
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#if defined(a86)
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debug("CR0=%#lx CR2=%#lx CR3=%#lx CR4=%#lx CR8=%#lx", cr0.raw, cr2.raw, cr3.raw, cr4.raw, cr8.raw);
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debug("CR0: PE:%s MP:%s EM:%s TS:%s ET:%s NE:%s WP:%s AM:%s NW:%s CD:%s PG:%s R0:%#x R1:%#x R2:%#x",
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cr0.PE ? "True " : "False", cr0.MP ? "True " : "False", cr0.EM ? "True " : "False", cr0.TS ? "True " : "False",
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cr0.ET ? "True " : "False", cr0.NE ? "True " : "False", cr0.WP ? "True " : "False", cr0.AM ? "True " : "False",
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cr0.NW ? "True " : "False", cr0.CD ? "True " : "False", cr0.PG ? "True " : "False",
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cr0.Reserved0, cr0.Reserved1, cr0.Reserved2);
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debug("CR2: PFLA: %#lx",
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cr2.PFLA);
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debug("CR3: PWT:%s PCD:%s PDBR:%#llx",
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cr3.PWT ? "True " : "False", cr3.PCD ? "True " : "False", cr3.PDBR);
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#endif // defined(a86)
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#if defined(a64)
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debug("CR4: VME:%s PVI:%s TSD:%s DE:%s PSE:%s PAE:%s MCE:%s PGE:%s PCE:%s UMIP:%s OSFXSR:%s OSXMMEXCPT:%s LA57:%s VMXE:%s SMXE:%s PCIDE:%s OSXSAVE:%s SMEP:%s SMAP:%s PKE:%s R0:%#x R1:%#x R2:%#x",
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cr4.VME ? "True " : "False", cr4.PVI ? "True " : "False", cr4.TSD ? "True " : "False", cr4.DE ? "True " : "False",
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cr4.PSE ? "True " : "False", cr4.PAE ? "True " : "False", cr4.MCE ? "True " : "False", cr4.PGE ? "True " : "False",
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cr4.PCE ? "True " : "False", cr4.UMIP ? "True " : "False", cr4.OSFXSR ? "True " : "False", cr4.OSXMMEXCPT ? "True " : "False",
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cr4.LA57 ? "True " : "False", cr4.VMXE ? "True " : "False", cr4.SMXE ? "True " : "False", cr4.PCIDE ? "True " : "False",
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cr4.OSXSAVE ? "True " : "False", cr4.SMEP ? "True " : "False", cr4.SMAP ? "True " : "False", cr4.PKE ? "True " : "False",
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cr4.Reserved0, cr4.Reserved1, cr4.Reserved2);
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#elif defined(a32)
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debug("CR4: VME:%s PVI:%s TSD:%s DE:%s PSE:%s PAE:%s MCE:%s PGE:%s PCE:%s UMIP:%s OSFXSR:%s OSXMMEXCPT:%s LA57:%s VMXE:%s SMXE:%s PCIDE:%s OSXSAVE:%s SMEP:%s SMAP:%s PKE:%s R0:%#x R1:%#x",
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cr4.VME ? "True " : "False", cr4.PVI ? "True " : "False", cr4.TSD ? "True " : "False", cr4.DE ? "True " : "False",
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cr4.PSE ? "True " : "False", cr4.PAE ? "True " : "False", cr4.MCE ? "True " : "False", cr4.PGE ? "True " : "False",
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cr4.PCE ? "True " : "False", cr4.UMIP ? "True " : "False", cr4.OSFXSR ? "True " : "False", cr4.OSXMMEXCPT ? "True " : "False",
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cr4.LA57 ? "True " : "False", cr4.VMXE ? "True " : "False", cr4.SMXE ? "True " : "False", cr4.PCIDE ? "True " : "False",
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cr4.OSXSAVE ? "True " : "False", cr4.SMEP ? "True " : "False", cr4.SMAP ? "True " : "False", cr4.PKE ? "True " : "False",
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cr4.Reserved0, cr4.Reserved1);
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#endif
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#if defined(a86)
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debug("CR8: TPL:%d", cr8.TPL);
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#endif // defined(a86)
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#if defined(a64)
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debug("RFL: CF:%s PF:%s AF:%s ZF:%s SF:%s TF:%s IF:%s DF:%s OF:%s IOPL:%s NT:%s RF:%s VM:%s AC:%s VIF:%s VIP:%s ID:%s AlwaysOne:%d R0:%#x R1:%#x R2:%#x R3:%#x",
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Frame->rflags.CF ? "True " : "False", Frame->rflags.PF ? "True " : "False", Frame->rflags.AF ? "True " : "False", Frame->rflags.ZF ? "True " : "False",
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Frame->rflags.SF ? "True " : "False", Frame->rflags.TF ? "True " : "False", Frame->rflags.IF ? "True " : "False", Frame->rflags.DF ? "True " : "False",
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Frame->rflags.OF ? "True " : "False", Frame->rflags.IOPL ? "True " : "False", Frame->rflags.NT ? "True " : "False", Frame->rflags.RF ? "True " : "False",
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Frame->rflags.VM ? "True " : "False", Frame->rflags.AC ? "True " : "False", Frame->rflags.VIF ? "True " : "False", Frame->rflags.VIP ? "True " : "False",
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Frame->rflags.ID ? "True " : "False", Frame->rflags.AlwaysOne,
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Frame->rflags.Reserved0, Frame->rflags.Reserved1, Frame->rflags.Reserved2, Frame->rflags.Reserved3);
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#elif defined(a32)
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debug("EFL: CF:%s PF:%s AF:%s ZF:%s SF:%s TF:%s IF:%s DF:%s OF:%s IOPL:%s NT:%s RF:%s VM:%s AC:%s VIF:%s VIP:%s ID:%s AlwaysOne:%d R0:%#x R1:%#x R2:%#x",
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Frame->eflags.CF ? "True " : "False", Frame->eflags.PF ? "True " : "False", Frame->eflags.AF ? "True " : "False", Frame->eflags.ZF ? "True " : "False",
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Frame->eflags.SF ? "True " : "False", Frame->eflags.TF ? "True " : "False", Frame->eflags.IF ? "True " : "False", Frame->eflags.DF ? "True " : "False",
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Frame->eflags.OF ? "True " : "False", Frame->eflags.IOPL ? "True " : "False", Frame->eflags.NT ? "True " : "False", Frame->eflags.RF ? "True " : "False",
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Frame->eflags.VM ? "True " : "False", Frame->eflags.AC ? "True " : "False", Frame->eflags.VIF ? "True " : "False", Frame->eflags.VIP ? "True " : "False",
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Frame->eflags.ID ? "True " : "False", Frame->eflags.AlwaysOne,
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Frame->eflags.Reserved0, Frame->eflags.Reserved1, Frame->eflags.Reserved2);
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#elif defined(aa64)
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#endif
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#if defined(a64)
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debug("EFER: SCE:%s LME:%s LMA:%s NXE:%s SVME:%s LMSLE:%s FFXSR:%s TCE:%s R0:%#x R1:%#x R2:%#x",
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efer.SCE ? "True " : "False", efer.LME ? "True " : "False", efer.LMA ? "True " : "False", efer.NXE ? "True " : "False",
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efer.SVME ? "True " : "False", efer.LMSLE ? "True " : "False", efer.FFXSR ? "True " : "False", efer.TCE ? "True " : "False",
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efer.Reserved0, efer.Reserved1, efer.Reserved2);
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#endif
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}
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#endif
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switch (Frame->InterruptNumber)
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{
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case CPU::x86::PageFault:
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{
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bool Handled = false;
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Handled = CurProc->vma->HandleCoW(CrashHandler::PageFaultAddress);
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if (!Handled)
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Handled = CurThread->Stack->Expand(CrashHandler::PageFaultAddress);
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if (Handled)
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{
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debug("Page fault handled");
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CurThread->SetState(Tasking::Ready);
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return true;
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}
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CurProc->Signals->SendSignal(SIGSEGV,
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{Tasking::KILL_CRASH});
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break;
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}
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case CPU::x86::Debug:
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case CPU::x86::Breakpoint:
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{
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CurProc->Signals->SendSignal(SIGTRAP,
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{Tasking::KILL_CRASH});
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break;
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}
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case CPU::x86::DivideByZero:
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case CPU::x86::Overflow:
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case CPU::x86::BoundRange:
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case CPU::x86::x87FloatingPoint:
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case CPU::x86::SIMDFloatingPoint:
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{
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CurProc->Signals->SendSignal(SIGFPE,
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{Tasking::KILL_CRASH});
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break;
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}
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case CPU::x86::InvalidOpcode:
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case CPU::x86::GeneralProtectionFault:
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{
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CurProc->Signals->SendSignal(SIGILL,
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{Tasking::KILL_CRASH});
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break;
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}
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case CPU::x86::DeviceNotAvailable:
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{
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CurProc->Signals->SendSignal(SIGBUS,
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{Tasking::KILL_CRASH});
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break;
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}
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case CPU::x86::NonMaskableInterrupt:
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case CPU::x86::DoubleFault:
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case CPU::x86::CoprocessorSegmentOverrun:
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case CPU::x86::InvalidTSS:
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case CPU::x86::SegmentNotPresent:
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case CPU::x86::StackSegmentFault:
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case CPU::x86::AlignmentCheck:
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case CPU::x86::MachineCheck:
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case CPU::x86::Virtualization:
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case CPU::x86::Security:
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default:
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{
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error("Unhandled exception %d on CPU %d",
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Frame->InterruptNumber, CurCPU->ID);
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break;
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}
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}
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error("User mode exception handler failed");
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return false;
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}
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