mirror of
https://github.com/Fennix-Project/Kernel.git
synced 2025-05-25 22:14:37 +00:00
1137 lines
27 KiB
C++
1137 lines
27 KiB
C++
/*
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This file is part of Fennix Kernel.
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Fennix Kernel is free software: you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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Fennix Kernel is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <pci.hpp>
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#include <power.hpp>
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#include <acpi.hpp>
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#include "../kernel.h"
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namespace PCI
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{
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namespace Descriptors
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{
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const char *u8ToHexString(uint8_t Value)
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{
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static char Buffer[3];
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memset(Buffer, 0, 3);
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for (size_t i = 0; i < 2; i++)
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{
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uint8_t Digit = (Value >> (4 - (i * 4))) & 0xF;
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if (Digit < 10)
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Buffer[i] = s_cst(char, '0' + Digit);
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else
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Buffer[i] = s_cst(char, 'A' + (Digit - 10));
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}
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return Buffer;
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}
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const char *u32ToHexString(uint32_t Value)
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{
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static char Buffer[9];
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memset(Buffer, 0, 9);
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for (size_t i = 0; i < 8; i++)
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{
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uint8_t Digit = (Value >> (28 - (i * 4))) & 0xF;
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if (Digit < 10)
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Buffer[i] = s_cst(char, '0' + Digit);
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else
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Buffer[i] = s_cst(char, 'A' + (Digit - 10));
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}
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return Buffer;
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}
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const char *MassStorageControllerSubclassName(uint8_t SubclassCode)
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{
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switch (SubclassCode)
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{
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case 0x00:
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return "SCSI Bus Controller";
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case 0x01:
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return "IDE Controller";
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case 0x02:
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return "Floppy Disk Controller";
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case 0x03:
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return "IPI Bus Controller";
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case 0x04:
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return "RAID Controller";
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case 0x05:
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return "ATA Controller";
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case 0x06:
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return "Serial ATA";
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case 0x07:
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return "Serial Attached SCSI Controller";
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case 0x08:
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return "Non-Volatile Memory Controller";
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case 0x80:
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return "Mass Storage Controller";
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default:
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break;
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}
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fixme("Unknown mass storage controller %02x", SubclassCode);
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return u8ToHexString(SubclassCode);
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}
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const char *NetworkControllerSubclassName(uint8_t SubclassCode)
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{
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switch (SubclassCode)
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{
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case 0x00:
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return "Ethernet Controller";
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case 0x01:
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return "Token Ring Controller";
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case 0x02:
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return "FDDI Controller";
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case 0x03:
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return "ATM Controller";
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case 0x04:
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return "ISDN Controller";
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case 0x05:
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return "WorldFip Controller";
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case 0x06:
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return "PICMG HyperCard Controller";
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case 0x07:
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return "Infiniband Controller";
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case 0x08:
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return "Fabric Controller";
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case 0x80:
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return "Network Controller";
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default:
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break;
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}
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fixme("Unknown network controller %02x", SubclassCode);
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return u8ToHexString(SubclassCode);
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}
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const char *DisplayControllerSubclassName(uint8_t SubclassCode)
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{
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switch (SubclassCode)
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{
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case 0x00:
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return "VGA Compatible Controller";
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case 0x01:
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return "XGA Controller";
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case 0x02:
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return "3D Controller";
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case 0x80:
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return "Display Controller";
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default:
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break;
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}
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fixme("Unknown display controller %02x", SubclassCode);
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return u8ToHexString(SubclassCode);
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}
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const char *CommunicationControllerSubclassName(uint8_t SubclassCode)
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{
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switch (SubclassCode)
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{
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case 0x00:
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return "Serial Controller";
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case 0x01:
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return "Parallel Controller";
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case 0x02:
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return "Multi-Serial Controller";
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case 0x03:
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return "IEEE-1284 Controller";
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case 0x04:
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return "ATM Controller";
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case 0x05:
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return "Object Storage Controller";
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case 0x80:
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return "Communication controller";
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default:
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break;
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}
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fixme("Unknown communication controller %02x", SubclassCode);
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return u8ToHexString(SubclassCode);
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}
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const char *BaseSystemPeripheralSubclassName(uint8_t SubclassCode)
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{
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// not sure if it's right
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switch (SubclassCode)
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{
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case 0x00:
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return "Unclassified";
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case 0x01:
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return "Keyboard";
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case 0x02:
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return "Pointing Device";
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case 0x03:
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return "Mouse";
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case 0x04:
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return "Scanner";
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case 0x05:
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return "Gameport";
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case 0x80:
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return "Unclassified";
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default:
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break;
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}
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fixme("Unknown base system peripheral %02x", SubclassCode);
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return u8ToHexString(SubclassCode);
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}
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const char *SerialBusControllerSubclassName(uint8_t SubclassCode)
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{
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switch (SubclassCode)
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{
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case 0x00:
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return "FireWire (IEEE 1394) Controller";
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case 0x01:
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return "ACCESS Bus Controller";
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case 0x02:
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return "SSA Controller";
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case 0x03:
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return "USB Controller";
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case 0x04:
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return "Fibre Channel Controller";
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case 0x05:
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return "SMBus Controller";
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case 0x06:
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return "Infiniband Controller";
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case 0x07:
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return "IPMI Interface Controller";
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case 0x08:
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return "SERCOS Interface (IEC 61491) Controller";
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case 0x09:
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return "CANbus Controller";
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case 0x80:
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return "Serial Bus Controller";
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default:
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break;
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}
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fixme("Unknown serial bus controller %02x", SubclassCode);
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return u8ToHexString(SubclassCode);
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}
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const char *BridgeDeviceSubclassName(uint8_t SubclassCode)
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{
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switch (SubclassCode)
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{
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case 0x00:
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return "Host Bridge";
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case 0x01:
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return "ISA Bridge";
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case 0x02:
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return "EISA Bridge";
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case 0x03:
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return "MCA Bridge";
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case 0x04:
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return "PCI-to-PCI Bridge";
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case 0x05:
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return "PCMCIA Bridge";
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case 0x06:
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return "NuBus Bridge";
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case 0x07:
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return "CardBus Bridge";
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case 0x08:
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return "RACEway Bridge";
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case 0x09:
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return "PCI-to-PCI Bridge";
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case 0x0A:
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return "InfiniBand-to-PCI Host Bridge";
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case 0x80:
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return "Bridge Device";
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default:
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break;
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}
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fixme("Unknown bridge device %02x", SubclassCode);
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return u8ToHexString(SubclassCode);
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}
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const char *WirelessControllerSubclassName(uint8_t SubclassCode)
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{
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switch (SubclassCode)
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{
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case 0x11:
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return "Bluetooth";
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case 0x20:
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return "802.1a controller";
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case 0x21:
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return "802.1b controller";
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case 0x80:
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return "Wireless controller";
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default:
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break;
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}
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fixme("Unknown wireless controller %02x", SubclassCode);
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return u8ToHexString(SubclassCode);
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}
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const char *GetVendorName(uint32_t VendorID)
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{
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switch (VendorID)
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{
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case 0x106B:
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return "Apple Inc.";
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case 0x104B:
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return "Bus Logic";
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case 0x1000:
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return "Symbios Logic";
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case 0x1B36:
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case 0x1AF4:
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return "Red Hat, Inc.";
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case 0x10EC:
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return "Realtek Semiconductor Co., Ltd.";
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case 0x80EE:
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return "VirtualBox";
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case 0x1274:
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return "Ensoniq";
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case 0x1234:
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return "QEMU";
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case 0x15AD:
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return "VMware";
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case 0x8086:
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return "Intel Corporation";
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case 0x1022:
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return "Advanced Micro Devices, Inc.";
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case 0x10DE:
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return "NVIDIA Corporation";
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case 0x1AE0:
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return "Google, Inc.";
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case 0x1a58:
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return "Razer USA Ltd.";
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case 0x1414:
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return "Microsoft Corporation";
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default:
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break;
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}
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fixme("Unknown vendor %04x", VendorID);
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return u32ToHexString(VendorID);
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}
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const char *GetDeviceName(uint32_t VendorID, uint32_t DeviceID)
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{
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switch (VendorID)
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{
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case Apple:
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{
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switch (DeviceID)
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{
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case 0x3f:
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return "KeyLargo/Intrepid USB";
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default:
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break;
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}
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break;
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}
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case BusLogic:
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{
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switch (DeviceID)
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{
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case 0x1040:
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return "BT-946C (BA80C30) [MultiMaster 10]";
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default:
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break;
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}
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break;
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}
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case SymbiosLogic:
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{
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switch (DeviceID)
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{
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case 0x30:
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return "53c1030 PCI-X Fusion-MPT Dual Ultra320 SCSI";
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case 0x54:
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return "SAS1068 PCI-X Fusion-MPT SAS";
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case 0x1000:
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return "63C815";
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default:
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break;
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}
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break;
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}
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case RedHat:
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{
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switch (DeviceID)
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{
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case 0x1000:
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case 0x1041:
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return "Virtio network device";
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case 0x1001:
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case 0x1042:
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return "Virtio block device";
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case 0x1002:
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case 0x1045:
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return "Virtio memory balloon";
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case 0x1003:
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case 0x1043:
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return "Virtio console";
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case 0x1004:
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case 0x1048:
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return "Virtio SCSI";
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case 0x1005:
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case 0x1044:
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return "Virtio RNG";
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case 0x1009:
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case 0x1049:
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case 0x105a:
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return "Virtio filesystem";
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case 0x1050:
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return "Virtio GPU";
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case 0x1052:
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return "Virtio input";
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case 0x1053:
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return "Virtio socket";
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case 1110:
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return "Inter-VM shared memory";
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case 0x1af41100:
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return "QEMU Virtual Machine";
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default:
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break;
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}
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break;
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}
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case REDHat2:
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{
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switch (DeviceID)
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{
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case 0x0001:
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return "QEMU PCI-PCI bridge";
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case 0x0002:
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return "QEMU PCI 16550A Adapter";
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case 0x0003:
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return "QEMU PCI Dual-port 16550A Adapter";
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case 0x0004:
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return "QEMU PCI Quad-port 16550A Adapter";
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case 0x0005:
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return "QEMU PCI Test Device";
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case 0x0006:
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return "PCI Rocker Ethernet switch device";
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case 0x0007:
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return "PCI SD Card Host Controller Interface";
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case 0x0008:
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return "QEMU PCIe Host bridge";
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case 0x0009:
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return "QEMU PCI Expander bridge";
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case 0x000A:
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return "PCI-PCI bridge (multiseat)";
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case 0x000B:
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return "QEMU PCIe Expander bridge";
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case 0x000C:
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return "QEMU PCIe Root Port";
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case 0x000D:
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return "QEMU XHCI Host Controller";
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case 0x0010:
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return "QEMU NVM Express Controller";
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case 0x0100:
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return "QXL Paravirtual Graphic Card";
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case 0x1AF41100:
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return "QEMU Virtual Machine";
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default:
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break;
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}
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break;
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}
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case Realtek:
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{
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switch (DeviceID)
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{
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case 0x8029:
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return "RTL-8029(AS)";
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case 0x8139:
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return "RTL-8139/8139C/8139C+ Ethernet Controller";
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case 0x8161:
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return "RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller";
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case 0x8168:
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return "RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller";
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case 0xC821:
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return "RTL8821CE 802.11ac PCIe Wireless Network Adapter";
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default:
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break;
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}
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break;
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}
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case VirtualBox:
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{
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switch (DeviceID)
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{
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case 0xCAFE:
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return "VirtualBox Guest Service";
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case 0xBEEF:
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return "VirtualBox Graphics Adapter";
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case 0x0021:
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return "USB Tablet";
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case 0x0022:
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return "Multitouch tablet";
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case 0x4E56:
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return "NVM Express";
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default:
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break;
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}
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break;
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}
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case Ensoniq:
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{
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switch (DeviceID)
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{
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case 0x1371:
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return "ES1371/ES1373 / Creative Labs CT2518";
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|
case 0x5000:
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return "ES1370 [AudioPCI]";
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|
default:
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break;
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|
}
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break;
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}
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case QEMU:
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{
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switch (DeviceID)
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{
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case 0x1111:
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return "QEMU Display";
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|
default:
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break;
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}
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break;
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}
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case VMware:
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{
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switch (DeviceID)
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{
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case 0x0740:
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return "Virtual Machine Communication Interface";
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|
case 0x0405:
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return "SVGA II Adapter";
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|
case 0x0790:
|
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return "PCI bridge";
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|
case 0x07A0:
|
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return "PCI Express Root Port";
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|
case 0x0774:
|
|
return "USB1.1 UHCI Controller";
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|
case 0x0770:
|
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return "USB2 EHCI Controller";
|
|
case 0x0779:
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|
return "USB3 xHCI 1.0 Controller";
|
|
case 0x07E0:
|
|
return "SATA AHCI controller";
|
|
case 0x07F0:
|
|
return "NVM Express";
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|
default:
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
case IntelCorporation:
|
|
{
|
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switch (DeviceID)
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{
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|
case 0x1229:
|
|
return "82557/8/9/0/1 Ethernet Pro 100";
|
|
case 0x1209:
|
|
return "8255xER/82551IT Fast Ethernet Controller";
|
|
case 0x1004:
|
|
return "82543GC Gigabit Ethernet Controller (Copper)";
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|
case 0x100E:
|
|
return "82540EM Gigabit Ethernet Controller";
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|
case 0x7190:
|
|
return "440BX/ZX/DX - 82443BX/ZX/DX Host bridge";
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|
case 0x7191:
|
|
return "440BX/ZX/DX - 82443BX/ZX/DX AGP bridge";
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|
case 0x7110:
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|
return "82371AB/EB/MB PIIX4 ISA";
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|
case 0x7111:
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|
return "82371AB/EB/MB PIIX4 IDE";
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|
case 0x7113:
|
|
return "82371AB/EB/MB PIIX4 ACPI";
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|
case 0x1e31:
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|
return "7 Series/C210 Series Chipset Family USB xHCI Host Controller";
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|
case 0x100F:
|
|
return "82545EM Gigabit Ethernet Controller (Copper)";
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|
case 0x1903:
|
|
return "Xeon E3-1200 v5/E3-1500 v5/6th Gen Core Processor Thermal Subsystem";
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|
case 0x1911:
|
|
return "Xeon E3-1200 v5/v6 / E3-1500 v5 / 6th/7th Gen Core Processor Gaussian Mixture Model";
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|
case 0x1371:
|
|
return "ES1371/ES1373 / Creative Labs CT2518";
|
|
case 0x27b9:
|
|
return "82801GBM (ICH7-M) LPC Interface Bridge";
|
|
case 0x07E0:
|
|
return "SATA AHCI controller";
|
|
case 0x293E:
|
|
return "82801I (ICH9 Family) HD Audio Controller";
|
|
case 0x2935:
|
|
return "82801I (ICH9 Family) USB UHCI Controller #2";
|
|
case 0x2936:
|
|
return "82801I (ICH9 Family) USB UHCI Controller #3";
|
|
case 0x293A:
|
|
return "82801I (ICH9 Family) USB2 EHCI Controller #1";
|
|
case 0x2934:
|
|
return "82801I (ICH9 Family) USB UHCI Controller #1";
|
|
case 0x2668:
|
|
return "82801FB/FBM/FR/FW/FRW (ICH6 Family) High Definition Audio Controller";
|
|
case 0x265C:
|
|
return "82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller";
|
|
case 0x2415:
|
|
return "82801AA AC'97 Audio Controller";
|
|
case 0x10D3:
|
|
return "82574L Gigabit Network Connection";
|
|
case 0x29C0:
|
|
return "82G33/G31/P35/P31 Express DRAM Controller";
|
|
case 0x2918:
|
|
return "82801IB (ICH9) LPC Interface Controller";
|
|
case 0x2829:
|
|
return "82801HM/HEM (ICH8M/ICH8M-E) SATA Controller [AHCI mode]";
|
|
case 0x2922:
|
|
return "82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA Controller [AHCI mode]";
|
|
case 0x2930:
|
|
return "82801I (ICH9 Family) SMBus Controller";
|
|
case 0x269E:
|
|
return "631xESB/632xESB IDE Controller";
|
|
case 0x282A:
|
|
return "82801 Mobile SATA Controller [RAID mode]";
|
|
case 0x5914:
|
|
return "Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers";
|
|
case 0x5917:
|
|
return "UHD Graphics 620";
|
|
case 0x9D10:
|
|
return "Sunrise Point-LP PCI Express Root Port #1";
|
|
case 0x9D11:
|
|
return "Sunrise Point-LP PCI Express Root Port #2";
|
|
case 0x9D12:
|
|
return "Sunrise Point-LP PCI Express Root Port #1";
|
|
case 0x9D13:
|
|
return "Sunrise Point-LP PCI Express Root Port #1";
|
|
case 0x9D14:
|
|
return "Sunrise Point-LP PCI Express Root Port #5";
|
|
case 0x9D15:
|
|
return "Sunrise Point-LP PCI Express Root Port #6";
|
|
case 0x9D21:
|
|
return "Sunrise Point-LP PMC";
|
|
case 0x9D23:
|
|
return "Sunrise Point-LP SMBus";
|
|
case 0x9D2F:
|
|
return "Sunrise Point-LP USB 3.0 xHCI Controller";
|
|
case 0x9D31:
|
|
return "Sunrise Point-LP Thermal subsystem";
|
|
case 0x9D3A:
|
|
return "Sunrise Point-LP CSME HECI #1";
|
|
case 0x9D4E:
|
|
return "Intel(R) 100 Series Chipset Family LPC Controller/eSPI Controller - 9D4E";
|
|
case 0x9D71:
|
|
return "Sunrise Point-LP HD Audio";
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
case AdvancedMicroDevices:
|
|
{
|
|
switch (DeviceID)
|
|
{
|
|
case 0x2000:
|
|
return "79C970 [PCnet32 LANCE]";
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
case NVIDIACorporation:
|
|
{
|
|
switch (DeviceID)
|
|
{
|
|
case 0x174D:
|
|
return "GM108M [GeForce MX130]";
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
fixme("Unknown device %04x:%04x", VendorID, DeviceID);
|
|
return u32ToHexString(DeviceID);
|
|
}
|
|
|
|
const char *GetSubclassName(uint8_t ClassCode, uint8_t SubclassCode)
|
|
{
|
|
switch (ClassCode)
|
|
{
|
|
case 0x00:
|
|
return "Unclassified";
|
|
case 0x01:
|
|
return MassStorageControllerSubclassName(SubclassCode);
|
|
case 0x02:
|
|
return NetworkControllerSubclassName(SubclassCode);
|
|
case 0x03:
|
|
return DisplayControllerSubclassName(SubclassCode);
|
|
case 0x04:
|
|
return "Multimedia controller";
|
|
case 0x05:
|
|
return "Memory Controller";
|
|
case 0x06:
|
|
return BridgeDeviceSubclassName(SubclassCode);
|
|
case 0x07:
|
|
return CommunicationControllerSubclassName(SubclassCode);
|
|
case 0x08:
|
|
return BaseSystemPeripheralSubclassName(SubclassCode);
|
|
case 0x09:
|
|
return "Input device controller";
|
|
case 0x0A:
|
|
return "Docking station";
|
|
case 0x0B:
|
|
return "Processor";
|
|
case 0x0C:
|
|
return SerialBusControllerSubclassName(SubclassCode);
|
|
case 0x0D:
|
|
return WirelessControllerSubclassName(SubclassCode);
|
|
case 0x0E:
|
|
return "Intelligent controller";
|
|
case 0x0F:
|
|
return "Satellite communication controller";
|
|
case 0x10:
|
|
return "Encryption controller";
|
|
case 0x11:
|
|
return "Signal processing accelerators";
|
|
case 0x12:
|
|
return "Processing accelerators";
|
|
case 0x13:
|
|
return "Non-Essential Instrumentation";
|
|
case 0x40:
|
|
return "Coprocessor";
|
|
default:
|
|
break;
|
|
}
|
|
fixme("Unknown subclass name %02x:%02x", ClassCode, SubclassCode);
|
|
return u8ToHexString(SubclassCode);
|
|
}
|
|
|
|
const char *GetProgIFName(uint8_t ClassCode, uint8_t SubclassCode, uint8_t ProgIF)
|
|
{
|
|
switch (ClassCode)
|
|
{
|
|
case 0x01:
|
|
{
|
|
switch (SubclassCode)
|
|
{
|
|
case 0x06:
|
|
{
|
|
switch (ProgIF)
|
|
{
|
|
case 0:
|
|
return "Vendor Specific SATA Controller";
|
|
case 1:
|
|
return "AHCI SATA Controller";
|
|
case 2:
|
|
return "Serial Storage Bus SATA Controller";
|
|
default:
|
|
return "SATA controller";
|
|
}
|
|
break;
|
|
}
|
|
case 0x08:
|
|
{
|
|
switch (ProgIF)
|
|
{
|
|
case 0x01:
|
|
return "NVMHCI Controller";
|
|
case 0x02:
|
|
return "NVM Express Controller";
|
|
default:
|
|
return "Non-Volatile Memory Controller";
|
|
}
|
|
break;
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
case 0x03:
|
|
{
|
|
switch (SubclassCode)
|
|
{
|
|
case 0x00:
|
|
switch (ProgIF)
|
|
{
|
|
case 0x00:
|
|
return "VGA Controller";
|
|
case 0x01:
|
|
return "8514-Compatible Controller";
|
|
default:
|
|
return "VGA Compatible Controller";
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
case 0x07:
|
|
{
|
|
switch (SubclassCode)
|
|
{
|
|
case 0x00:
|
|
{
|
|
switch (ProgIF)
|
|
{
|
|
case 0x00:
|
|
return "Serial controller <8250>";
|
|
case 0x01:
|
|
return "Serial controller <16450>";
|
|
case 0x02:
|
|
return "Serial controller <16550>";
|
|
case 0x03:
|
|
return "Serial controller <16650>";
|
|
case 0x04:
|
|
return "Serial controller <16750>";
|
|
case 0x05:
|
|
return "Serial controller <16850>";
|
|
case 0x06:
|
|
return "Serial controller <16950";
|
|
default:
|
|
return "Serial controller";
|
|
}
|
|
break;
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
case 0x0C:
|
|
{
|
|
switch (SubclassCode)
|
|
{
|
|
case 0x00:
|
|
{
|
|
switch (ProgIF)
|
|
{
|
|
case 0x00:
|
|
return "Generic FireWire (IEEE 1394) Controller";
|
|
case 0x10:
|
|
return "OHCI FireWire (IEEE 1394) Controller";
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
case 0x03:
|
|
{
|
|
switch (ProgIF)
|
|
{
|
|
case 0x00:
|
|
return "UHCI (USB1) Controller";
|
|
case 0x10:
|
|
return "OHCI (USB1) Controller";
|
|
case 0x20:
|
|
return "EHCI (USB2) Controller";
|
|
case 0x30:
|
|
return "XHCI (USB3) Controller";
|
|
case 0x80:
|
|
return "Unspecified";
|
|
case 0xFE:
|
|
return "USB Device";
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
// not really a fixme
|
|
// fixme("Unknown prog IF name %02x:%02x:%02x", ClassCode, SubclassCode, ProgIF);
|
|
return u8ToHexString(ProgIF);
|
|
}
|
|
}
|
|
|
|
#ifdef DEBUG
|
|
void e(PCIDevice dev)
|
|
{
|
|
PCIDeviceHeader *hdr = dev.Header;
|
|
|
|
debug("%02x.%02x.%02x - %#x:%#x\t\t%s / %s / %s / %s / %s",
|
|
dev.Bus, dev.Device, dev.Function,
|
|
hdr->VendorID, hdr->DeviceID,
|
|
Descriptors::GetVendorName(hdr->VendorID),
|
|
Descriptors::GetDeviceName(hdr->VendorID, hdr->DeviceID),
|
|
Descriptors::DeviceClasses[hdr->Class],
|
|
Descriptors::GetSubclassName(hdr->Class, hdr->Subclass),
|
|
Descriptors::GetProgIFName(hdr->Class, hdr->Subclass, hdr->ProgIF));
|
|
}
|
|
#endif
|
|
|
|
void Manager::MapPCIAddresses(PCIDevice Device, Memory::PageTable *Table)
|
|
{
|
|
debug("Header Type: %d", Device.Header->HeaderType);
|
|
switch (Device.Header->HeaderType)
|
|
{
|
|
case 128:
|
|
warn("Unknown header type %d! Guessing PCI Header 0",
|
|
Device.Header->HeaderType);
|
|
[[fallthrough]];
|
|
case 0: /* PCI Header 0 */
|
|
{
|
|
PCIHeader0 *hdr0 = (PCIHeader0 *)Device.Header;
|
|
|
|
uint32_t BAR[6];
|
|
size_t BARsSize[6];
|
|
|
|
BAR[0] = hdr0->BAR0;
|
|
BAR[1] = hdr0->BAR1;
|
|
BAR[2] = hdr0->BAR2;
|
|
BAR[3] = hdr0->BAR3;
|
|
BAR[4] = hdr0->BAR4;
|
|
BAR[5] = hdr0->BAR5;
|
|
|
|
debug("Type: %d; IOBase: %#lx; MemoryBase: %#lx",
|
|
BAR[0] & 1, BAR[1] & (~3), BAR[0] & (~15));
|
|
|
|
/* BARs Size */
|
|
for (short i = 0; i < 6; i++)
|
|
{
|
|
if (BAR[i] == 0)
|
|
continue;
|
|
|
|
size_t size;
|
|
if ((BAR[i] & 1) == 0) /* Memory Base */
|
|
{
|
|
hdr0->BAR0 = 0xFFFFFFFF;
|
|
size = hdr0->BAR0;
|
|
hdr0->BAR0 = BAR[i];
|
|
BARsSize[i] = size & (~15);
|
|
BARsSize[i] = ~BARsSize[i] + 1;
|
|
BARsSize[i] = BARsSize[i] & 0xFFFFFFFF;
|
|
debug("BAR%d %#lx size: %d",
|
|
i, BAR[i], BARsSize[i]);
|
|
}
|
|
else if ((BAR[i] & 1) == 1) /* I/O Base */
|
|
{
|
|
hdr0->BAR1 = 0xFFFFFFFF;
|
|
size = hdr0->BAR1;
|
|
hdr0->BAR1 = BAR[i];
|
|
BARsSize[i] = size & (~3);
|
|
BARsSize[i] = ~BARsSize[i] + 1;
|
|
BARsSize[i] = BARsSize[i] & 0xFFFF;
|
|
debug("BAR%d %#lx size: %d",
|
|
i, BAR[i], BARsSize[i]);
|
|
}
|
|
}
|
|
|
|
/* Mapping the BARs */
|
|
for (short i = 0; i < 6; i++)
|
|
{
|
|
if (BAR[i] == 0)
|
|
continue;
|
|
|
|
if ((BAR[i] & 1) == 0) /* Memory Base */
|
|
{
|
|
uintptr_t BARBase = BAR[i] & (~15);
|
|
size_t BARSize = BARsSize[i];
|
|
|
|
debug("Mapping BAR%d %#lx-%#lx",
|
|
i, BARBase, BARBase + BARSize);
|
|
|
|
if (BARSize > 0)
|
|
Memory::Virtual(Table).Map((void *)BARBase, (void *)BARBase,
|
|
BARSize, Memory::RW | Memory::PWT);
|
|
}
|
|
else if ((BAR[i] & 1) == 1) /* I/O Base */
|
|
{
|
|
uintptr_t BARBase = BAR[i] & (~3);
|
|
size_t BARSize = BARsSize[i];
|
|
|
|
debug("Mapping BAR%d %#x-%#x",
|
|
i, BARBase, BARBase + BARSize);
|
|
|
|
if (BARSize > 0)
|
|
Memory::Virtual(Table).Map((void *)BARBase, (void *)BARBase,
|
|
BARSize, Memory::RW | Memory::PWT);
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
case 1: /* PCI Header 1 (PCI-to-PCI Bridge) */
|
|
{
|
|
fixme("PCI Header 1 (PCI-to-PCI Bridge) not implemented yet");
|
|
break;
|
|
}
|
|
case 2: /* PCI Header 2 (PCI-to-CardBus Bridge) */
|
|
{
|
|
fixme("PCI Header 2 (PCI-to-CardBus Bridge) not implemented yet");
|
|
break;
|
|
}
|
|
default:
|
|
{
|
|
error("Unknown header type %d", Device.Header->HeaderType);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
void Manager::EnumerateFunction(uint64_t DeviceAddress, uint32_t Function, PCIDevice dev)
|
|
{
|
|
dev.Function = Function;
|
|
|
|
uintptr_t Offset = Function << 12;
|
|
uint64_t FunctionAddress = DeviceAddress + Offset;
|
|
Memory::Virtual(KernelPageTable).Map((void *)FunctionAddress, (void *)FunctionAddress, Memory::PTFlag::RW);
|
|
PCIDeviceHeader *PCIDeviceHdr = (PCIDeviceHeader *)FunctionAddress;
|
|
dev.Header = PCIDeviceHdr;
|
|
|
|
if (PCIDeviceHdr->DeviceID == 0)
|
|
return;
|
|
if (PCIDeviceHdr->DeviceID == 0xFFFF)
|
|
return;
|
|
|
|
Devices.push_back(dev);
|
|
#ifdef DEBUG
|
|
e(dev);
|
|
#endif
|
|
}
|
|
|
|
void Manager::EnumerateDevice(uint64_t BusAddress, uint32_t Device, PCIDevice dev)
|
|
{
|
|
dev.Device = Device;
|
|
|
|
uintptr_t Offset = Device << 15;
|
|
uint64_t DeviceAddress = BusAddress + Offset;
|
|
Memory::Virtual(KernelPageTable).Map((void *)DeviceAddress, (void *)DeviceAddress, Memory::PTFlag::RW);
|
|
PCIDeviceHeader *PCIDeviceHdr = (PCIDeviceHeader *)DeviceAddress;
|
|
|
|
if (PCIDeviceHdr->DeviceID == 0)
|
|
return;
|
|
if (PCIDeviceHdr->DeviceID == 0xFFFF)
|
|
return;
|
|
|
|
for (uint32_t Function = 0; Function < 8; Function++)
|
|
EnumerateFunction(DeviceAddress, Function, dev);
|
|
}
|
|
|
|
void Manager::EnumerateBus(uint64_t BaseAddress, uint32_t Bus, PCIDevice dev)
|
|
{
|
|
dev.Bus = Bus;
|
|
|
|
uintptr_t Offset = Bus << 20;
|
|
uint64_t BusAddress = BaseAddress + Offset;
|
|
Memory::Virtual(KernelPageTable).Map((void *)BusAddress, (void *)BusAddress, Memory::PTFlag::RW);
|
|
PCIDeviceHeader *PCIDeviceHdr = (PCIDeviceHeader *)BusAddress;
|
|
|
|
if (Bus != 0) // TODO: VirtualBox workaround (UNTESTED ON REAL HARDWARE!)
|
|
{
|
|
if (PCIDeviceHdr->DeviceID == 0)
|
|
return;
|
|
if (PCIDeviceHdr->DeviceID == 0xFFFF)
|
|
return;
|
|
}
|
|
|
|
debug("PCI Bus DeviceID:%#x VendorID:%#x BIST:%#x Cache:%#x Class:%#x Cmd:%#x HdrType:%#x LatencyTimer:%#x ProgIF:%#x RevID:%#x Status:%#x SubClass:%#x ",
|
|
PCIDeviceHdr->DeviceID, PCIDeviceHdr->VendorID, PCIDeviceHdr->BIST,
|
|
PCIDeviceHdr->CacheLineSize, PCIDeviceHdr->Class, PCIDeviceHdr->Command,
|
|
PCIDeviceHdr->HeaderType, PCIDeviceHdr->LatencyTimer, PCIDeviceHdr->ProgIF,
|
|
PCIDeviceHdr->RevisionID, PCIDeviceHdr->Status, PCIDeviceHdr->Subclass);
|
|
|
|
for (uint32_t Device = 0; Device < 32; Device++)
|
|
EnumerateDevice(BusAddress, Device, dev);
|
|
}
|
|
|
|
std::list<PCIDevice> Manager::FindPCIDevice(uint8_t Class, uint8_t Subclass, uint8_t ProgIF)
|
|
{
|
|
std::list<PCIDevice> DeviceFound;
|
|
foreach (auto dev in Devices)
|
|
{
|
|
if (dev.Header->Class == Class &&
|
|
dev.Header->Subclass == Subclass &&
|
|
dev.Header->ProgIF == ProgIF)
|
|
{
|
|
DeviceFound.push_back(dev);
|
|
}
|
|
}
|
|
return DeviceFound;
|
|
}
|
|
|
|
std::list<PCIDevice> Manager::FindPCIDevice(uint16_t VendorID, uint16_t DeviceID)
|
|
{
|
|
std::list<PCIDevice> DeviceFound;
|
|
foreach (auto dev in Devices)
|
|
{
|
|
if (dev.Header->VendorID == VendorID &&
|
|
dev.Header->DeviceID == DeviceID)
|
|
{
|
|
DeviceFound.push_back(dev);
|
|
}
|
|
}
|
|
return DeviceFound;
|
|
}
|
|
|
|
std::list<PCIDevice> Manager::FindPCIDevice(std::list<uint16_t> VendorIDs,
|
|
std::list<uint16_t> DeviceIDs)
|
|
{
|
|
std::list<PCIDevice> DeviceFound;
|
|
foreach (auto dev in Devices)
|
|
{
|
|
foreach (auto VendorID in VendorIDs)
|
|
{
|
|
foreach (auto DeviceID in DeviceIDs)
|
|
{
|
|
if (dev.Header->VendorID == VendorID &&
|
|
dev.Header->DeviceID == DeviceID)
|
|
{
|
|
DeviceFound.push_back(dev);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return DeviceFound;
|
|
}
|
|
|
|
Manager::Manager()
|
|
{
|
|
#if defined(a86)
|
|
if (!PowerManager->GetACPI())
|
|
{
|
|
error("ACPI not found");
|
|
return;
|
|
}
|
|
|
|
if (!((ACPI::ACPI *)PowerManager->GetACPI())->MCFG)
|
|
{
|
|
error("MCFG not found");
|
|
return;
|
|
}
|
|
|
|
int Entries = s_cst(int, ((((ACPI::ACPI *)PowerManager->GetACPI())->MCFG->Header.Length) - sizeof(ACPI::ACPI::MCFGHeader)) / sizeof(DeviceConfig));
|
|
Memory::Virtual vmm(KernelPageTable);
|
|
for (int t = 0; t < Entries; t++)
|
|
{
|
|
DeviceConfig *NewDeviceConfig = (DeviceConfig *)((uintptr_t)((ACPI::ACPI *)PowerManager->GetACPI())->MCFG + sizeof(ACPI::ACPI::MCFGHeader) + (sizeof(DeviceConfig) * t));
|
|
vmm.Map((void *)NewDeviceConfig->BaseAddress, (void *)NewDeviceConfig->BaseAddress, Memory::PTFlag::RW);
|
|
debug("PCI Entry %d Address:%p BUS:%#x-%#x", t, NewDeviceConfig->BaseAddress,
|
|
NewDeviceConfig->StartBus, NewDeviceConfig->EndBus);
|
|
|
|
PCIDevice dev{};
|
|
dev.Config = NewDeviceConfig;
|
|
for (uint32_t Bus = NewDeviceConfig->StartBus; Bus < NewDeviceConfig->EndBus; Bus++)
|
|
EnumerateBus(NewDeviceConfig->BaseAddress, Bus, dev);
|
|
}
|
|
#elif defined(aa64)
|
|
error("PCI not implemented on aarch64");
|
|
#endif
|
|
}
|
|
|
|
Manager::~Manager() {}
|
|
}
|