mirror of
https://github.com/Fennix-Project/Kernel.git
synced 2025-05-29 07:47:59 +00:00
557 lines
16 KiB
C++
557 lines
16 KiB
C++
#ifndef __FENNIX_KERNEL_CPU_H__
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#define __FENNIX_KERNEL_CPU_H__
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#include <types.h>
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/**
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* @brief CPU related functions.
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*/
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namespace CPU
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{
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/**
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* @brief Enum for CPU::Interrupts() function.
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*/
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enum InterruptsType
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{
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/**
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* @brief Check if interrupts are enabled.
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*/
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Check,
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/**
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* @brief Enable interrupts.
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*/
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Enable,
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/**
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* @brief Disable interrupts.
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*/
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Disable
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};
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/**
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* @brief Get CPU vendor identifier.
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*
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* @return char* CPU Vendor ID.
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*/
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char *Vendor();
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/**
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* @brief Get CPU name.
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*
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* @return char* CPU Name.
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*/
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char *Name();
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/**
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* @brief Get CPU hypervisor vendor.
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*
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* @return char* Hypervisor vendor.
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*/
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char *Hypervisor();
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/**
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* @brief Pause the CPU
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*/
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void Pause();
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/**
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* @brief Stop the CPU (infinite loop)
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*/
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void Stop();
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/**
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* @brief Halt the CPU
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*/
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void Halt();
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/**
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* @brief Check if interrupts are enabled
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*
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* @return true If InterruptsType::Check and interrupts are enabled, or if other InterruptsType were executed successfully
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* @return false If InterruptsType::Check and interrupts are disabled, or if other InterruptsType failed
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*/
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bool Interrupts(InterruptsType Type = Check);
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/**
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* @brief Get/Set the CPU's page table
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*
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* @param PT The new page table, if empty, the current page table will be returned
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* @return void* The current page table
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*/
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void *PageTable(void *PT = nullptr);
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namespace MemBar
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{
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static inline void Barrier()
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("" ::
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: "memory");
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#elif defined(__aarch64__)
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asmv("dmb ish" ::
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: "memory");
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#endif
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}
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static inline void Fence()
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("mfence" ::
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: "memory");
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#elif defined(__aarch64__)
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asmv("dmb ish" ::
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: "memory");
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#endif
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}
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static inline void StoreFence()
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("sfence" ::
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: "memory");
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#elif defined(__aarch64__)
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asmv("dmb ishst" ::
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: "memory");
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#endif
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}
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static inline void LoadFence()
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{
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#if defined(__amd64__) || defined(__i386__)
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asmv("lfence" ::
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: "memory");
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#elif defined(__aarch64__)
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asmv("dmb ishld" ::
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: "memory");
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#endif
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}
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}
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namespace x32
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{
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}
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namespace x64
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{
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typedef enum
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{
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DivideByZero = 0x0,
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Debug = 0x1,
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NonMaskableInterrupt = 0x2,
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Breakpoint = 0x3,
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Overflow = 0x4,
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BoundRange = 0x5,
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InvalidOpcode = 0x6,
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DeviceNotAvailable = 0x7,
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DoubleFault = 0x8,
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CoprocessorSegmentOverrun = 0x9,
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InvalidTSS = 0xa,
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SegmentNotPresent = 0xb,
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StackSegmentFault = 0xc,
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GeneralProtectionFault = 0xd,
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PageFault = 0xe,
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x87FloatingPoint = 0x10,
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AlignmentCheck = 0x11,
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MachineCheck = 0x12,
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SIMDFloatingPoint = 0x13,
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Virtualization = 0x14,
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Security = 0x1e
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} ISRExceptions;
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typedef enum
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{
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ISR0 = 0x0, // Divide-by-zero Error
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ISR1 = 0x1, // Debug
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ISR2 = 0x2, // Non-maskable Interrupt
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ISR3 = 0x3, // Breakpoint
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ISR4 = 0x4, // Overflow
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ISR5 = 0x5, // Bound Range Exceeded
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ISR6 = 0x6, // Invalid Opcode
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ISR7 = 0x7, // Device Not Available
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ISR8 = 0x8, // Double Fault
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ISR9 = 0x9, // Coprocessor Segment Overrun
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ISR10 = 0xa, // Invalid TSS
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ISR11 = 0xb, // Segment Not P
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ISR12 = 0xc, // Stack-Segment Fault
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ISR13 = 0xd, // General Protection Fault
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ISR14 = 0xe, // Page Fault
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ISR15 = 0xf, // Reserved
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ISR16 = 0x10, // x87 Floating-Point Exception
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ISR17 = 0x11, // Alignment Check
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ISR18 = 0x12, // Machine Check
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ISR19 = 0x13, // SIMD Floating-Point Exception
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ISR20 = 0x14, // Virtualization Exception
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ISR21 = 0x15, // Reserved
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ISR22 = 0x16, // Reserved
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ISR23 = 0x17, // Reserved
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ISR24 = 0x18, // Reserved
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ISR25 = 0x19, // Reserved
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ISR26 = 0x1a, // Reserved
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ISR27 = 0x1b, // Reserved
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ISR28 = 0x1c, // Reserved
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ISR29 = 0x1d, // Reserved
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ISR30 = 0x1e, // Security Exception
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ISR31 = 0x1f, // Reserved
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IRQ0 = 0x20, // Programmable Interrupt Timer Interrupt
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IRQ1 = 0x21, // Keyboard Interrupt
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IRQ2 = 0x22, // Cascade (used internally by the two PICs. never raised)
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IRQ3 = 0x23, // COM2 (if enabled)
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IRQ4 = 0x24, // COM1 (if enabled)
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IRQ5 = 0x25, // LPT2 (if enabled)
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IRQ6 = 0x26, // Floppy Disk
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IRQ7 = 0x27, // LPT1 / Unreliable "spurious" interrupt (usually)
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IRQ8 = 0x28, // CMOS real-time clock (if enabled)
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IRQ9 = 0x29, // Free for peripherals / legacy SCSI / NIC
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IRQ10 = 0x2a, // Free for peripherals / SCSI / NIC
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IRQ11 = 0x2b, // Free for peripherals / SCSI / NIC
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IRQ12 = 0x2c, // PS2 Mouse
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IRQ13 = 0x2d, // FPU / Coprocessor / Inter-processor
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IRQ14 = 0x2e, // Primary ATA Hard Disk
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IRQ15 = 0x2f, // Secondary ATA Hard Disk
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IRQ16 = 0x30, // Reserved for multitasking
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IRQ17 = 0x31, // Reserved for monotasking
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IRQ18 = 0x32,
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IRQ19 = 0x33,
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IRQ20 = 0x34,
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IRQ21 = 0x35,
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IRQ22 = 0x36,
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IRQ23 = 0x37,
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IRQ24 = 0x38,
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IRQ25 = 0x39,
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IRQ26 = 0x3a,
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IRQ27 = 0x3b,
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IRQ28 = 0x3c,
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IRQ29 = 0x3d,
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IRQ30 = 0x3e,
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IRQ31 = 0x3f,
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IRQ32 = 0x40,
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IRQ33 = 0x41,
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IRQ34 = 0x42,
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IRQ35 = 0x43,
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IRQ36 = 0x44,
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IRQ37 = 0x45,
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IRQ38 = 0x46,
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IRQ39 = 0x47,
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IRQ40 = 0x48,
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IRQ41 = 0x49,
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IRQ42 = 0x4a,
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IRQ43 = 0x4b,
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IRQ44 = 0x4c,
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IRQ45 = 0x4d,
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IRQ46 = 0x4e,
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IRQ47 = 0x4f,
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IRQ48 = 0x50,
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IRQ49 = 0x51,
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IRQ50 = 0x52,
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IRQ51 = 0x53,
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IRQ52 = 0x54,
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IRQ53 = 0x55,
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IRQ54 = 0x56,
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IRQ55 = 0x57,
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IRQ56 = 0x58,
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IRQ57 = 0x59,
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IRQ58 = 0x5a,
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IRQ59 = 0x5b,
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IRQ60 = 0x5c,
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IRQ61 = 0x5d,
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IRQ62 = 0x5e,
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IRQ63 = 0x5f,
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IRQ64 = 0x60,
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IRQ65 = 0x61,
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IRQ66 = 0x62,
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IRQ67 = 0x63,
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IRQ68 = 0x64,
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IRQ69 = 0x65,
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IRQ70 = 0x66,
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IRQ71 = 0x67,
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IRQ72 = 0x68,
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IRQ73 = 0x69,
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IRQ74 = 0x6a,
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IRQ75 = 0x6b,
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IRQ76 = 0x6c,
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IRQ77 = 0x6d,
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IRQ78 = 0x6e,
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IRQ79 = 0x6f,
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IRQ80 = 0x70,
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IRQ81 = 0x71,
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IRQ82 = 0x72,
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IRQ83 = 0x73,
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IRQ84 = 0x74,
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IRQ85 = 0x75,
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IRQ86 = 0x76,
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IRQ87 = 0x77,
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IRQ88 = 0x78,
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IRQ89 = 0x79,
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IRQ90 = 0x7a,
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IRQ91 = 0x7b,
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IRQ92 = 0x7c,
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IRQ93 = 0x7d,
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IRQ94 = 0x7e,
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IRQ95 = 0x7f,
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IRQ96 = 0x80,
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IRQ97 = 0x81,
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IRQ98 = 0x82,
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IRQ99 = 0x83,
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IRQ100 = 0x84,
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IRQ101 = 0x85,
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IRQ102 = 0x86,
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IRQ103 = 0x87,
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IRQ104 = 0x88,
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IRQ105 = 0x89,
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IRQ106 = 0x8a,
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IRQ107 = 0x8b,
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IRQ108 = 0x8c,
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IRQ109 = 0x8d,
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IRQ110 = 0x8e,
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IRQ111 = 0x8f,
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IRQ112 = 0x90,
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IRQ113 = 0x91,
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IRQ114 = 0x92,
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IRQ115 = 0x93,
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IRQ116 = 0x94,
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IRQ117 = 0x95,
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IRQ118 = 0x96,
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IRQ119 = 0x97,
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IRQ120 = 0x98,
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IRQ121 = 0x99,
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IRQ122 = 0x9a,
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IRQ123 = 0x9b,
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IRQ124 = 0x9c,
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IRQ125 = 0x9d,
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IRQ126 = 0x9e,
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IRQ127 = 0x9f,
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IRQ128 = 0xa0,
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IRQ129 = 0xa1,
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IRQ130 = 0xa2,
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IRQ131 = 0xa3,
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IRQ132 = 0xa4,
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IRQ133 = 0xa5,
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IRQ134 = 0xa6,
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IRQ135 = 0xa7,
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IRQ136 = 0xa8,
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IRQ137 = 0xa9,
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IRQ138 = 0xaa,
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IRQ139 = 0xab,
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IRQ140 = 0xac,
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IRQ141 = 0xad,
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IRQ142 = 0xae,
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IRQ143 = 0xaf,
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IRQ144 = 0xb0,
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IRQ145 = 0xb1,
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IRQ146 = 0xb2,
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IRQ147 = 0xb3,
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IRQ148 = 0xb4,
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IRQ149 = 0xb5,
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IRQ150 = 0xb6,
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IRQ151 = 0xb7,
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IRQ152 = 0xb8,
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IRQ153 = 0xb9,
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IRQ154 = 0xba,
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IRQ155 = 0xbb,
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IRQ156 = 0xbc,
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IRQ157 = 0xbd,
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IRQ158 = 0xbe,
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IRQ159 = 0xbf,
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IRQ160 = 0xc0,
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IRQ161 = 0xc1,
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IRQ162 = 0xc2,
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IRQ163 = 0xc3,
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IRQ164 = 0xc4,
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IRQ165 = 0xc5,
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IRQ166 = 0xc6,
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IRQ167 = 0xc7,
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IRQ168 = 0xc8,
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IRQ169 = 0xc9,
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IRQ170 = 0xca,
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IRQ171 = 0xcb,
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IRQ172 = 0xcc,
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IRQ173 = 0xcd,
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IRQ174 = 0xce,
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IRQ175 = 0xcf,
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IRQ176 = 0xd0,
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IRQ177 = 0xd1,
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IRQ178 = 0xd2,
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IRQ179 = 0xd3,
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IRQ180 = 0xd4,
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IRQ181 = 0xd5,
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IRQ182 = 0xd6,
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IRQ183 = 0xd7,
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IRQ184 = 0xd8,
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IRQ185 = 0xd9,
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IRQ186 = 0xda,
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IRQ187 = 0xdb,
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IRQ188 = 0xdc,
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IRQ189 = 0xdd,
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IRQ190 = 0xde,
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IRQ191 = 0xdf,
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IRQ192 = 0xe0,
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IRQ193 = 0xe1,
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IRQ194 = 0xe2,
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IRQ195 = 0xe3,
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IRQ196 = 0xe4,
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IRQ197 = 0xe5,
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IRQ198 = 0xe6,
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IRQ199 = 0xe7,
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IRQ200 = 0xe8,
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IRQ201 = 0xe9,
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IRQ202 = 0xea,
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IRQ203 = 0xeb,
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IRQ204 = 0xec,
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IRQ205 = 0xed,
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IRQ206 = 0xee,
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IRQ207 = 0xef,
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IRQ208 = 0xf0,
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IRQ209 = 0xf1,
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IRQ210 = 0xf2,
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IRQ211 = 0xf3,
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IRQ212 = 0xf4,
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IRQ213 = 0xf5,
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IRQ214 = 0xf6,
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IRQ215 = 0xf7,
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IRQ216 = 0xf8,
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IRQ217 = 0xf9,
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IRQ218 = 0xfa,
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IRQ219 = 0xfb,
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IRQ220 = 0xfc,
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IRQ221 = 0xfd,
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IRQ222 = 0xfe,
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IRQ223 = 0xff,
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} Interrupts;
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typedef union
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{
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struct
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{
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/** @brief Carry Flag */
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uint64_t CF : 1;
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/** @brief Reserved */
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uint64_t always_one : 1;
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/** @brief Parity Flag */
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uint64_t PF : 1;
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/** @brief Reserved */
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uint64_t _reserved0 : 1;
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/** @brief Auxiliary Carry Flag */
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uint64_t AF : 1;
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/** @brief Reserved */
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uint64_t _reserved1 : 1;
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/** @brief Zero Flag */
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uint64_t ZF : 1;
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/** @brief Sign Flag */
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uint64_t SF : 1;
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/** @brief Trap Flag */
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uint64_t TF : 1;
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/** @brief Interrupt Enable Flag */
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uint64_t IF : 1;
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/** @brief Direction Flag */
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uint64_t DF : 1;
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/** @brief Overflow Flag */
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uint64_t OF : 1;
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/** @brief I/O Privilege Level */
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uint64_t IOPL : 2;
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/** @brief Nested Task */
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uint64_t NT : 1;
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/** @brief Reserved */
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uint64_t _reserved2 : 1;
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/** @brief Resume Flag */
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uint64_t RF : 1;
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/** @brief Virtual 8086 Mode */
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uint64_t VM : 1;
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/** @brief Alignment Check */
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uint64_t AC : 1;
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/** @brief Virtual Interrupt Flag */
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uint64_t VIF : 1;
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/** @brief Virtual Interrupt Pending */
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uint64_t VIP : 1;
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/** @brief ID Flag */
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uint64_t ID : 1;
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/** @brief Reserved */
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uint64_t _reserved3 : 10;
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};
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uint64_t raw;
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} RFLAGS;
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typedef struct _TrapFrame
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{
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// uint64_t gs; // General-purpose Segment
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// uint64_t fs; // General-purpose Segment
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// uint64_t es; // Extra Segment (used for string operations)
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uint64_t ds; // Data Segment
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uint64_t r15; // General purpose
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uint64_t r14; // General purpose
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uint64_t r13; // General purpose
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uint64_t r12; // General purpose
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uint64_t r11; // General purpose
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uint64_t r10; // General purpose
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uint64_t r9; // General purpose
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uint64_t r8; // General purpose
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uint64_t rbp; // Base Pointer (meant for stack frames)
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uint64_t rdi; // Destination index for string operations
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uint64_t rsi; // Source index for string operations
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uint64_t rdx; // Data (commonly extends the A register)
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uint64_t rcx; // Counter
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uint64_t rbx; // Base
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uint64_t rax; // Accumulator
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uint64_t int_num; // Interrupt Number
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uint64_t error_code; // Error code
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uint64_t rip; // Instruction Pointer
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uint64_t cs; // Code Segment
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RFLAGS rflags; // Register Flags
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uint64_t rsp; // Stack Pointer
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uint64_t ss; // Stack Segment
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} TrapFrame;
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static inline void lgdt(void *gdt)
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{
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#if defined(__amd64__)
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asmv("lgdt (%0)"
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:
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: "r"(gdt));
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#endif
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}
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static inline void lidt(void *idt)
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{
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#if defined(__amd64__)
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asmv("lidt (%0)"
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:
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: "r"(idt));
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#endif
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}
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static inline void ltr(uint16_t Segment)
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{
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#if defined(__amd64__)
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asmv("ltr %0"
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:
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: "r"(Segment));
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#endif
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}
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static inline void invlpg(void *Address)
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{
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#if defined(__amd64__)
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asmv("invlpg (%0)"
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:
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: "r"(Address)
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: "memory");
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#endif
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}
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static inline void cpuid(uint32_t Function, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
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{
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#if defined(__amd64__)
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asmv("cpuid"
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: "=a"(*eax), "=b"(*ebx), "=c"(*ecx), "=d"(*edx)
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: "a"(Function));
|
|
#endif
|
|
}
|
|
}
|
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}
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#endif // !__FENNIX_KERNEL_CPU_H__
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