mirror of
https://github.com/Fennix-Project/Kernel.git
synced 2025-05-25 22:14:37 +00:00
552 lines
12 KiB
C++
552 lines
12 KiB
C++
/*
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This file is part of Fennix Kernel.
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Fennix Kernel is free software: you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation, either version 3 of
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the License, or (at your option) any later version.
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Fennix Kernel is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Fennix Kernel. If not, see <https://www.gnu.org/licenses/>.
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*/
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#include <cpu.hpp>
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#include <memory.hpp>
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#include <convert.h>
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#include <debug.h>
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#include <smp.hpp>
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#include "../kernel.h"
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#if defined(a64)
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using namespace CPU::x64;
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#elif defined(a32)
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using namespace CPU::x32;
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#elif defined(aa64)
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#endif
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namespace CPU
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{
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static bool SSEEnabled = false;
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const char *Vendor()
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{
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static char Vendor[13] = {0};
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if (Vendor[0] != 0)
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return Vendor;
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#if defined(a64)
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uint32_t eax, ebx, ecx, edx;
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x64::cpuid(0x0, &eax, &ebx, &ecx, &edx);
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memcpy(Vendor + 0, &ebx, 4);
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memcpy(Vendor + 4, &edx, 4);
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memcpy(Vendor + 8, &ecx, 4);
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#elif defined(a32)
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uint32_t eax, ebx, ecx, edx;
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x32::cpuid(0x0, &eax, &ebx, &ecx, &edx);
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memcpy(Vendor + 0, &ebx, 4);
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memcpy(Vendor + 4, &edx, 4);
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memcpy(Vendor + 8, &ecx, 4);
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#elif defined(aa64)
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#error "Not implemented"
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#endif
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return Vendor;
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}
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const char *Name()
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{
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static char Name[49] = {0};
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if (Name[0] != 0)
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return Name;
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#if defined(a64)
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uint32_t eax, ebx, ecx, edx;
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x64::cpuid(0x80000002, &eax, &ebx, &ecx, &edx);
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memcpy(Name + 0, &eax, 4);
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memcpy(Name + 4, &ebx, 4);
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memcpy(Name + 8, &ecx, 4);
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memcpy(Name + 12, &edx, 4);
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x64::cpuid(0x80000003, &eax, &ebx, &ecx, &edx);
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memcpy(Name + 16, &eax, 4);
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memcpy(Name + 20, &ebx, 4);
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memcpy(Name + 24, &ecx, 4);
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memcpy(Name + 28, &edx, 4);
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x64::cpuid(0x80000004, &eax, &ebx, &ecx, &edx);
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memcpy(Name + 32, &eax, 4);
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memcpy(Name + 36, &ebx, 4);
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memcpy(Name + 40, &ecx, 4);
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memcpy(Name + 44, &edx, 4);
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#elif defined(a32)
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uint32_t eax, ebx, ecx, edx;
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x32::cpuid(0x80000002, &eax, &ebx, &ecx, &edx);
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memcpy(Name + 0, &eax, 4);
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memcpy(Name + 4, &ebx, 4);
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memcpy(Name + 8, &ecx, 4);
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memcpy(Name + 12, &edx, 4);
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x32::cpuid(0x80000003, &eax, &ebx, &ecx, &edx);
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memcpy(Name + 16, &eax, 4);
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memcpy(Name + 20, &ebx, 4);
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memcpy(Name + 24, &ecx, 4);
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memcpy(Name + 28, &edx, 4);
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x32::cpuid(0x80000004, &eax, &ebx, &ecx, &edx);
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memcpy(Name + 32, &eax, 4);
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memcpy(Name + 36, &ebx, 4);
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memcpy(Name + 40, &ecx, 4);
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memcpy(Name + 44, &edx, 4);
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#elif defined(aa64)
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#error "Not implemented"
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#endif
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return Name;
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}
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const char *Hypervisor()
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{
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static char Hypervisor[13] = {0};
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if (Hypervisor[0] != 0)
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return Hypervisor;
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#if defined(a64)
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uint32_t eax, ebx, ecx, edx;
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x64::cpuid(0x1, &eax, &ebx, &ecx, &edx);
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if (!(ecx & (1 << 31))) /* Intel & AMD are the same */
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{
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Hypervisor[0] = 'N';
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Hypervisor[1] = 'o';
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Hypervisor[2] = 'n';
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Hypervisor[3] = 'e';
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return Hypervisor;
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}
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x64::cpuid(0x40000000, &eax, &ebx, &ecx, &edx);
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memcpy(Hypervisor + 0, &ebx, 4);
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memcpy(Hypervisor + 4, &ecx, 4);
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memcpy(Hypervisor + 8, &edx, 4);
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#elif defined(a32)
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uint32_t eax, ebx, ecx, edx;
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x32::cpuid(0x1, &eax, &ebx, &ecx, &edx);
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if (!(ecx & (1 << 31))) /* Intel & AMD are the same */
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{
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Hypervisor[0] = 'N';
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Hypervisor[1] = 'o';
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Hypervisor[2] = 'n';
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Hypervisor[3] = 'e';
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return Hypervisor;
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}
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x32::cpuid(0x40000000, &eax, &ebx, &ecx, &edx);
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memcpy(Hypervisor + 0, &ebx, 4);
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memcpy(Hypervisor + 4, &ecx, 4);
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memcpy(Hypervisor + 8, &edx, 4);
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#elif defined(aa64)
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#error "Not implemented"
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#endif
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return Hypervisor;
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}
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bool Interrupts(InterruptsType Type)
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{
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switch (Type)
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{
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case Check:
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{
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uintptr_t Flags;
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#if defined(a64)
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asmv("pushfq");
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asmv("popq %0"
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: "=r"(Flags));
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return Flags & (1 << 9);
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#elif defined(a32)
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asmv("pushfl");
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asmv("popl %0"
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: "=r"(Flags));
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return Flags & (1 << 9);
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#elif defined(aa64)
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asmv("mrs %0, cpsr"
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: "=r"(Flags));
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return Flags & (1 << 7);
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#endif
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}
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case Enable:
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{
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#if defined(a86)
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asmv("sti");
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#elif defined(aa64)
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asmv("cpsie i");
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#endif
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return true;
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}
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case Disable:
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{
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#if defined(a86)
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asmv("cli");
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#elif defined(aa64)
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asmv("cpsid i");
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#endif
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return true;
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}
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default:
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assert(!"Unknown InterruptsType");
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break;
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}
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return false;
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}
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void *PageTable(void *PT)
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{
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void *ret;
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#if defined(a64)
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asmv("movq %%cr3, %0"
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: "=r"(ret));
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if (PT)
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{
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asmv("movq %0, %%cr3"
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:
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: "r"(PT)
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: "memory");
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}
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#elif defined(a32)
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asmv("movl %%cr3, %0"
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: "=r"(ret));
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if (PT)
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{
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asmv("movl %0, %%cr3"
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:
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: "r"(PT)
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: "memory");
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}
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#elif defined(aa64)
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asmv("mrs %0, ttbr0_el1"
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: "=r"(ret));
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if (PT)
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{
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asmv("msr ttbr0_el1, %0"
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:
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: "r"(PT)
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: "memory");
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}
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#endif
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return ret;
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}
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struct SupportedFeat
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{
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bool PGE = false;
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bool SSE = false;
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bool UMIP = false;
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bool SMEP = false;
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bool SMAP = false;
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};
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SupportedFeat GetCPUFeat()
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{
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SupportedFeat feat{};
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if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
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{
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CPU::x86::AMD::CPUID0x00000001 cpuid1;
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CPU::x86::AMD::CPUID0x00000007_ECX_0 cpuid7;
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feat.PGE = cpuid1.EDX.PGE;
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feat.SSE = cpuid1.EDX.SSE;
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feat.SMEP = cpuid7.EBX.SMEP;
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feat.SMAP = cpuid7.EBX.SMAP;
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feat.UMIP = cpuid7.ECX.UMIP;
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}
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else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
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{
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CPU::x86::Intel::CPUID0x00000001 cpuid1;
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CPU::x86::Intel::CPUID0x00000007_0 cpuid7_0;
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feat.PGE = cpuid1.EDX.PGE;
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feat.SSE = cpuid1.EDX.SSE;
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feat.SMEP = cpuid7_0.EBX.SMEP;
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feat.SMAP = cpuid7_0.EBX.SMAP;
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feat.UMIP = cpuid7_0.ECX.UMIP;
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}
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return feat;
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}
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void InitializeFeatures(int Core)
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{
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static int BSP = 0;
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SupportedFeat feat = GetCPUFeat();
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CR0 cr0 = readcr0();
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CR4 cr4 = readcr4();
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if (Config.SIMD == false)
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{
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debug("Disabling SSE support...");
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feat.SSE = false;
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}
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if (feat.PGE)
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{
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debug("Enabling global pages support...");
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if (!BSP)
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KPrint("Global Pages is supported.");
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cr4.PGE = true;
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}
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bool SSEEnableAfter = false;
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/* Not sure if my code is not working properly or something else is the issue. */
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if ((strcmp(Hypervisor(), x86_CPUID_VENDOR_VIRTUALBOX) != 0) &&
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feat.SSE)
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{
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debug("Enabling SSE support...");
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if (!BSP)
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KPrint("SSE is supported.");
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cr0.EM = false;
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cr0.MP = true;
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cr4.OSFXSR = true;
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cr4.OSXMMEXCPT = true;
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CPUData *CoreData = GetCPU(Core);
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CoreData->Data.FPU.mxcsr = 0b0001111110000000;
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CoreData->Data.FPU.mxcsrmask = 0b1111111110111111;
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CoreData->Data.FPU.fcw = 0b0000001100111111;
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fxrstor(&CoreData->Data.FPU);
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SSEEnableAfter = true;
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}
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/* More info in AMD64 Architecture Programmer's Manual
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Volume 2: 3.1.1 CR0 Register */
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/* Not Write-Through
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This is ignored on recent processors.
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*/
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cr0.NW = false;
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/* Cache Disable
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Wether the CPU should cache memory or not.
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If it's enabled, PWT and PCD are ignored.
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*/
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cr0.CD = false;
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/* Write Protect
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When set, the supervisor can't write to read-only pages.
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*/
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cr0.WP = true;
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/* Alignment check
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The CPU checks the alignment of memory operands
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and generates #AC if the alignment is incorrect.
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The condition for an alignment check is:
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- The AM flag in CR0 is set.
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- The AC flag in the RFLAGS register is set.
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- CPL is 3.
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*/
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cr0.AM = true;
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debug("Updating CR0...");
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writecr0(cr0);
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debug("Updated CR0.");
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debug("CPU Prevention Features:%s%s%s",
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feat.SMEP ? " SMEP" : "",
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feat.SMAP ? " SMAP" : "",
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feat.UMIP ? " UMIP" : "");
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/* User-Mode Instruction Prevention
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This prevents user-mode code from executing these instructions:
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SGDT, SIDT, SLDT, SMSW, STR
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If any of these instructions are executed with CPL > 0, a #GP is generated.
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*/
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// cr4.UMIP = feat.UMIP;
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/* Supervisor Mode Execution Prevention
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This prevents user-mode code from executing code in the supervisor mode.
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*/
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cr4.SMEP = feat.SMEP;
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/* Supervisor Mode Access Prevention
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This prevents supervisor-mode code from accessing user-mode pages.
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*/
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cr4.SMAP = feat.SMAP;
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debug("Updating CR4...");
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writecr4(cr4);
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debug("Updated CR4.");
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debug("Enabling PAT support...");
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wrmsr(MSR_CR_PAT, 0x6 | (0x0 << 8) | (0x1 << 16));
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if (!BSP++)
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trace("Features for BSP initialized.");
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if (SSEEnableAfter)
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{
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SSEEnabled = true;
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debug("SSE support enabled.");
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}
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}
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uint64_t Counter()
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{
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// TODO: Get the counter from the x2APIC or any other timer that is available. (TSC is not available on all CPUs)
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uint64_t Counter;
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#if defined(a86)
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uint32_t eax, edx;
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asmv("rdtsc"
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: "=a"(eax),
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"=d"(edx));
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Counter = ((uint64_t)eax) | (((uint64_t)edx) << 32);
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#elif defined(aa64)
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asmv("mrs %0, cntvct_el0"
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: "=r"(Counter));
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#endif
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return Counter;
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}
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uint64_t CheckSIMD()
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{
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if (unlikely(!SSEEnabled))
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return SIMD_NONE;
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#warning "TODO: Proper SIMD support"
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return SIMD_NONE;
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#if defined(a86)
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static uint64_t SIMDType = SIMD_NONE;
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if (likely(SIMDType != SIMD_NONE))
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return SIMDType;
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if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
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{
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CPU::x86::AMD::CPUID0x00000001 cpuid;
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asmv("cpuid"
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: "=a"(cpuid.EAX.raw), "=b"(cpuid.EBX.raw),
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"=c"(cpuid.ECX.raw), "=d"(cpuid.EDX.raw)
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: "a"(0x1));
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if (cpuid.ECX.SSE42)
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SIMDType |= SIMD_SSE42;
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else if (cpuid.ECX.SSE41)
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SIMDType |= SIMD_SSE41;
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else if (cpuid.ECX.SSSE3)
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SIMDType |= SIMD_SSSE3;
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else if (cpuid.ECX.SSE3)
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SIMDType |= SIMD_SSE3;
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else if (cpuid.EDX.SSE2)
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SIMDType |= SIMD_SSE2;
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else if (cpuid.EDX.SSE)
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SIMDType |= SIMD_SSE;
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#ifdef DEBUG
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if (cpuid.ECX.SSE42)
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debug("SSE4.2 is supported.");
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if (cpuid.ECX.SSE41)
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debug("SSE4.1 is supported.");
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if (cpuid.ECX.SSSE3)
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debug("SSSE3 is supported.");
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if (cpuid.ECX.SSE3)
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debug("SSE3 is supported.");
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if (cpuid.EDX.SSE2)
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debug("SSE2 is supported.");
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if (cpuid.EDX.SSE)
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debug("SSE is supported.");
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#endif
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return SIMDType;
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}
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else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
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{
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CPU::x86::Intel::CPUID0x00000001 cpuid;
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asmv("cpuid"
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: "=a"(cpuid.EAX.raw), "=b"(cpuid.EBX.raw), "=c"(cpuid.ECX.raw), "=d"(cpuid.EDX.raw)
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: "a"(0x1));
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if (cpuid.ECX.SSE4_2)
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SIMDType |= SIMD_SSE42;
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else if (cpuid.ECX.SSE4_1)
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SIMDType |= SIMD_SSE41;
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else if (cpuid.ECX.SSSE3)
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SIMDType |= SIMD_SSSE3;
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else if (cpuid.ECX.SSE3)
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SIMDType |= SIMD_SSE3;
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else if (cpuid.EDX.SSE2)
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SIMDType |= SIMD_SSE2;
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else if (cpuid.EDX.SSE)
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SIMDType |= SIMD_SSE;
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#ifdef DEBUG
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if (cpuid.ECX.SSE4_2)
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debug("SSE4.2 is supported.");
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if (cpuid.ECX.SSE4_1)
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debug("SSE4.1 is supported.");
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if (cpuid.ECX.SSSE3)
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debug("SSSE3 is supported.");
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if (cpuid.ECX.SSE3)
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debug("SSE3 is supported.");
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if (cpuid.EDX.SSE2)
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debug("SSE2 is supported.");
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if (cpuid.EDX.SSE)
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debug("SSE is supported.");
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#endif
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return SIMDType;
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}
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debug("No SIMD support.");
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#endif // a64 || a32
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return SIMD_NONE;
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}
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bool CheckSIMD(x86SIMDType Type)
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{
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if (unlikely(!SSEEnabled))
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return false;
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#if defined(a86)
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if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_AMD) == 0)
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{
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CPU::x86::AMD::CPUID0x00000001 cpuid;
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asmv("cpuid"
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: "=a"(cpuid.EAX.raw), "=b"(cpuid.EBX.raw), "=c"(cpuid.ECX.raw), "=d"(cpuid.EDX.raw)
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: "a"(0x1));
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if (Type == SIMD_SSE42)
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return cpuid.ECX.SSE42;
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|
else if (Type == SIMD_SSE41)
|
|
return cpuid.ECX.SSE41;
|
|
else if (Type == SIMD_SSSE3)
|
|
return cpuid.ECX.SSSE3;
|
|
else if (Type == SIMD_SSE3)
|
|
return cpuid.ECX.SSE3;
|
|
else if (Type == SIMD_SSE2)
|
|
return cpuid.EDX.SSE2;
|
|
else if (Type == SIMD_SSE)
|
|
return cpuid.EDX.SSE;
|
|
}
|
|
else if (strcmp(CPU::Vendor(), x86_CPUID_VENDOR_INTEL) == 0)
|
|
{
|
|
CPU::x86::Intel::CPUID0x00000001 cpuid;
|
|
asmv("cpuid"
|
|
: "=a"(cpuid.EAX.raw), "=b"(cpuid.EBX.raw), "=c"(cpuid.ECX.raw), "=d"(cpuid.EDX.raw)
|
|
: "a"(0x1));
|
|
|
|
if (Type == SIMD_SSE42)
|
|
return cpuid.ECX.SSE4_2;
|
|
else if (Type == SIMD_SSE41)
|
|
return cpuid.ECX.SSE4_1;
|
|
else if (Type == SIMD_SSSE3)
|
|
return cpuid.ECX.SSSE3;
|
|
else if (Type == SIMD_SSE3)
|
|
return cpuid.ECX.SSE3;
|
|
else if (Type == SIMD_SSE2)
|
|
return cpuid.EDX.SSE2;
|
|
else if (Type == SIMD_SSE)
|
|
return cpuid.EDX.SSE;
|
|
}
|
|
#endif // a64 || a32
|
|
return false;
|
|
}
|
|
}
|